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Document overview

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Technical content

Features

  • Complete power conditioning solution from a 12 volt power bus.
  • Wide system input voltage range of 8V to 13.2V.
  • High and flat efficiency, up to 97.5%.
  • 4.5A Continuous Output Current Capability
  • Adjustable operating frequency with optional external clock input.
  • Master/Slave Mode for Parallel Operation
  • Output Enable pin, VOUT_OK, VIN_OK
  • Pre-programmed soft-start time.
  • Thermal shutdown, short circuit, Overload, OVLO and UVLO protection.
  • RoHS compliant, MSL level 3, 260C reflow.

Applications

  • Applications requiring down conversion from a 12V bus to a well regulated output voltage with high efficiency, in a compact foot print (Note: The total system application involves two or more Altera Enpirion products.)
  • Enterprise, Industrial, Embedded, and Telecommunication applications
  • Multi-rail computer & network interface applications such as PCIe and ATCA AMC cards.
  • 12V Industrial and Consumer Applications such as Audio/Video Home Theater, Tuners 22µF 1206 V IN V OUT CFLYP 47µF** 22µF VOUT AVIN AGND V P PVIN ENA PGND PGND CFLYN 1µF 47µF VBOOT 1µF FADJ 100kΩ 0402 EC2630QI 1206 1206 1206 30.1Ω 0402 1 www.altera.com/enpirion

Ordering Information

(°C) Package EC2630QI -40 to +85 36 pin 5.5 x5.5 EC2630QI-E QFN Evaluation Board Pin Configuration Below is a top view diagram of EC2630QI package. Figure 2: Pin-out diagram, top view of EC2630QI QFN Package. NOTE: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. Failure to follow this guideline may result in damage to the Device. NOTE: All pins must be soldered to PCB. 2 www.altera.com/enpirion

1 V3P3 Internal Regulated Supply Output. Connect bypass capacitor from V3P3 to GND. 2 FADJ Frequency Adjust pin used to set the switching frequency. See Theory of Operation Section for selecting the required resistor. 3, 8 GND Internal Regulated Supply Ground. Must tie directly to ground plane with a via right next to each pin.

4 VIN_OK Vin OK is an open drain transistor for power system state indication

for nominal 12V operation. VIN_OK is a logic high when Vin is greater than 9V.

5 VOUT_OK VOUT_OK is an open drain transistor for power system state

indication. VOUT_OK is a logic high when Vout is greater than 85% of expected nominal Vout. This pin should be used to control the ENABLE signals of downstream converters powered by the EC2630. 6 ENABLE This pin should be tied to VIN all the time. Contact Altera Power Applications support for more information.

7 NC NO CONNECT –– Do not electrically connect these pins to each

other or to any other electrical signal. CAUTION: May be internally connected. 9 M/S Mas ter/Slave pin for clock synchronization. Logic low = Master. Logic high = Slave.

10 NC NO CONNECT –– Do not electrically connect these pins to each

other or to any other electrical signal. CAUTION: May be internally connected. 11 SYNCH_I External Synchronizing Clock Input, input accepted in Slave mode. From an IBC in master mode. 12 SYNCH_O Synchronizing Clock Output. Frequency scaled output of internal oscillator. 13-18 PGND Power ground for the switching voltage attenuator 19-21 CFLYN Negative Terminal of Flying Capacitor 22-24 VOUT Converter Output Voltage 25-27 CFLYP Positive Terminal of Flying Capacitor 28-33 PVIN Main Input Supply

34 VBOOT Internal power Supply for high-side drive to which boot-strap

capacitor is tied.

35 AVIN Input Supply for Controller

36 NC NO CONNECT – Do not electrically connect these pins to each other

or to any other electrical signal. CAUTION: May be internally connected. 37 TGND This pad is a thermal gnd. Needs to be thermally and electrically connected to the ground plane through a matrix of vias. 3 www.altera.com/enpirion

BG _ Voltage Reference PGND EC2630QI N-Drive - 2 SYNC Logic Int. Voltage Regulator AVIN V3P3 CFLYP CFLYN SYNC_O GND VinOK VoutOK VoutOKVinOK UVLO VBOOT FADJ SYNC_I M_S Figure 3: Block diagram. 4 www.altera.com/enpirion

CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. PARAMETER SYMBOL MIN M AX UNITS Input Supply Voltage – PVIN, AVIN VIN -0.5 15 V Transient Input Supply Voltage, 2 ms maximum duration, 100 Hz repetition rate 20 V Input Voltage – ENA, VIN_OK, VOUT_OK, CFLYN, CFLYP, Vout -0.5 VIN V Input Voltage – V3P3, FADJ, M_S, SYNC_I, SYNC_O -0.5 3.5 V Input Voltage - VBOOT -0.5 VIN + 8 V Storage Temperature Range TSTG -65 150 °C Maximum Operating Junction Temperature TJ-ABS MAX 150 °C Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C ESD Rating (based on Human Body Model): AVIN Positive Negative 1500 2000 V ESD Rating (based on Human Body Model): All other pins 2000 V ESD Rating (based on Charged Device Model) 500 V Thermal Characteristics PARAMETER SYMBOL MIN TYP M AX UNITS Operating Junction Temp TJ -40 +125 °C Thermal Shutdown TSD 155 °C Thermal Shutdown Hysteresis TSDH 25 °C Thermal Resistance: Junction to Case θJC 1 °C/W Thermal Resistance: Junction to Ambient θJA 19 °C/W

Electrical Characteristics

NOTE: VIN=12.0V over operating temperature range unless otherwise noted. Typical values are at TA = 25°C. PARAMETER SYMBOL TEST CONDITIONS MIN TYP M AX UNITS Operating Input Voltage VIN 8 12 13.2 V Operating Boot Strap Voltage VBOOT @ Vin =12V, with 0.1uF capacitor between VBOOT and CFLYN 17 V Internal Regulated Supply Output V3P3 @ Vin =12V 2.97 3.3 3.63 V Under Voltage Lockout VUVLO 4.5 5 5.5 V Input Voltage Indication Rising VIN_OK 9 V Input Voltage Indication Falling 8 V Over Voltage Lockout VOVLO 13.35 14.2 15.05 V No Load Operating Current IOP @ 12V input and 125kHz switching 2 mA 5 www.altera.com/enpirion

PARAMETER SYMBOL TEST CONDITIONS MIN TYP M AX UNITS Switching Frequency (Internal Oscillator) FOSC RFADJUST= 100 KΩ, 68 115 165 kHz Frequency Adjust Voltage FADJ 1.2 V Output Voltage VOUT Fraction of input voltage with no load current 50 % Output Voltage Indication Threshold Rising VOUT_OK As a percentage of expected output voltage 85% V Output Voltage Indication Threshold Falling VOUT_OK As a percentage of expected output voltage 70% V Output Impedance ROUT ∆VOUT/∆ILOAD RFADJUST= 100 KΩ, 90 mΩ Continuous Output Current IOUT_Max 0 4.5 A Overload Trip Level VOCP Vin=12V, Overload sensed as a drop in output voltage 5.2 V Enable Threshold Logic Low ENA_VIL Max voltage to ensure the converter is disabled 0.3 V Enable Threshold Logic High ENA_VIH 6V ≤ VIN ≤ 13.2V 1.8 VIN V Logic Threshold Low M_S VIL -0.3 0.3 V Logic Threshold High M_S VIH V3P3 - 0.6 V3P3 V3P3 + 0.3 V External Clock frequency FEXT 0.01 1 MHz Clock Input Logic Low SYNC_I_VIL 0.3 V Clock Input Logic High SYNC_I_VI H 1.8 3.3 V Clock Output Logic Low SYNC_O_VOL 0.3 V Clock Output Logic High SYNC_O_VOH @ 1mA V3P3 - 0.6 V VIN_OK, VOUT_OK sink capability POK low voltage = 0.1V 1 mA 6 www.altera.com/enpirion

Typical Performance Characteristics Fig. 4: Nominal Efficiency (%) vs. Load (A) @ VIN = 13.2/ 12/10/8V, CIN=3x22uF, COUT=3X47uF, CFLY=3x47uF with RFADJUST= 100 KΩ , Start-up / Shutdown Wave forms with Enable tied to VIN Fig. 6a: Ch.1: VOUT, Ch.4: VIN Fig. 6b: Ch.1: VOUT, Ch.4: VIN Theory of Operation Bus Voltage Divider The EC2630QI is an open loop voltage divider. It generates an output voltage which is approximately half the input voltage value. The device uses switched capacitors to divide the input voltage by a factor of 2. External capacitors are charged in series during one half of a clock cycle and t he capacitors are then connected in parallel during the second half of the clock cycle. Since there is no feedback to regulate the output voltage, the output voltage depends on the input voltage as well as the load current. Temperature dependence is a function of load current. This device has been designed specifically for use along with Altera’s Enpirion point-of-load products for output voltage regulation. The Voltage Divider has the following features: Iout (A) Efficiency (%) Vin=13.2 Vin=12 Vin=11 Vin=10 Vin=9 Vin=8 7 www.altera.com/enpirion

  • Over-current protection (to protect the IC from excessive load current)
  • Thermal shutdown with hysteresis.
  • Under-voltage lockout circuit to disable the converter output when the input voltage is less than approximately 5V
  • Over-voltage lockout circuit to disable the converter output when the input voltage is greater than approximately 14.2V
  • Switching frequency is internally generated. However, a clock signal may be applied externally when the device is configured in Slave mode.
  • When in Master mode, the device will output its internal frequency scaled clock to the SYNCH_O pin.
  • Soft-start circuit, to limit the in-rush current when the converter is powered up.
  • VIN_OK and VOUT_OK indicator signals. Enable Operation A logic high on this pin will turn the device on, and logic low will disable the output. Under normal operation, the ENABLE pin needs to be tied to PVIN . The device is then turned on and off by ramping the input voltage up and down. Contact Altera Power Applications support for further details. Frequency Synch (Master/Slave) In Slave mode, an external clock may be used for switching the bus converter by connecting such a source to SYNC_I pin when the device is configured. In Master mode, the internal switching frequency of the Mas ter device is outputted through SYNCH_O pin. This clock signal can be used to drive other EC2630QI devices for synchronization or parallel operation. Soft-Start Operation Soft start is a me ans to reduce the in-rush current when the device is enabled. When the device is enabled by ramping up the input voltage, and the output capacitors are discharged, a large current flow is averted by modulating the gate drive of the NFET during the soft start interval. This interval is pre- programmed and not user programmable. Overload Protection The overload function is achieved by sensing the output voltage. An overload state is entered when the device is out of soft start and the output voltage drops below ~85% of the expected voltage. This overload state will initiate a fresh soft -start and the device will stay looping in soft -start as long as the over load condition exists. Over-Voltage Protection When the input voltage exceeds 14.2 V, the flying capacitor is placed in parallel with the output capacitor during OVLO and the device does not switch. Thermal Overload Protection Thermal shutdown will disable operation when the Junction temperature exceeds the value given in the Electrical Characteristics table. Once the junction temperature drops by the hysteresis tem perature, the converter will re- start with a normal soft-start. Input Under-voltage Lock-out Internal circuits ensure that the converter will not start switching until the input voltage is above the specified minimum voltage of ~5V. Frequency Adjustment The device is optimized to run at 125kHz switching frequency ( with RFADJ= 100 K Ω) independent of load current. The internal oscillator frequency can be adjusted by altering the value of the resistor between the FADJ pin and AGND (see chart below ). Contact Altera Power Applications support for further details. Frequency vs. Resistance 100 150 200 250 300 350 400 450 500 0 25 50 75 100 125 150 175 200 225 250 Resistance (K-Ohms) Oscillator Frequency (KHz) 8 www.altera.com/enpirion

3.3VDC EC2630 ENABLE EC2630 AVIN EC2630 FADJ 365k 137k 100k 499k 499k 20k 1uF 0.1uF

5 VCC

B A 74LVC1G02W5 B A B A External 3.3VDC DMN5L06DMK Figure 8: Optional External Over -Current Protection Circuit 11 www.altera.com/enpirion

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