DSP1620

DSP1620 AGERE | Alldatasheet

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devices. Specifically, it clarifies the function of the control register field that specifies the active clock frequency. as either the input clock frequency on the CKI pin or the output of an internal clock synthesizer (PLL). units named SIO and SSIO. The control register for SIO is sioc described on page 94 of the data sheet. Bits 8—7 within sioc (CLK1 field) specify the active clock frequency of the SIO. internal clock, not of CKI or CKO. Table 1. Data Sheet and Serial I/O Information for the DSP1620/27/28/29 Devices Table 2. Corrected Description of CLK/CLK1/CLK2 Field

Lucent T echnologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1999 Lucent T echnologies Inc. All Rights Reserved May 1999 AY99-001WDSP (must accompany DS97-321WDSP , DS96-188WDSP , DS97-040WDSP , and DS96-039WDSP) For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA P ACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent T echnologies (China) Co., Ltd., A-F2, 23/F , Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P . R. China Tel. (86) 21 6440 0468, ext. 316, FAX (86) 21 6440 0652 JAP AN: Microelectronics Group, Lucent T echnologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, T okyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DA T ALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 T echnical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 594 607 00 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), IT AL Y: (39) 02 6608131 (Milan), SP AIN: (34) 1 807 1441 (Madrid)

DSP1628 Digital Signal Processor

1 Features

n Optimized for digital cellular applications with a bit manipulation unit for higher coding efficiency and an error correction coprocessor for equalization and channel coding support. n On-chip, programmable, PLL clock synthesizer. n 19.2 ns and 12.5 ns instruction cycle times at 2.7 V. n Mask-programmable memory map option: The DSP1628x16 features 16 Kwords on-chip dual- port RAM. The DSP1628x08 features 8 Kwords on-chip dual-port RAM. Both feature 48 Kwords on-chip ROM with a secure option. n Low power consumption: — <1.9 mW/MIPS typical at 2.7 V. n Flexible power management modes: —Standard sleep: 0.2 mW/MIPS at 2.7 V. —Sleep with slow internal clock: 0.7 mW at 2.7 V. —Hardware STOP (pin halts DSP): <20 µ n Mask-programmable clock options: small signal, and CMOS. n 144 PBGA package (13 mm x 13 mm) available. n Sequenced accesses to X and Y external memory. n Object code compatible with the DSP1618. n Single-cycle squaring. n 16 x 16-bit multiplication and 36-bit accumulation in one instruction cycle. n Instruction cache for high-speed, program- efficient, zero-overhead looping. n Dual 25 Mbit/s serial I/O ports with multiprocessor capability—16-bit data channel, 8-bit protocol channel. n 8-bit parallel host interface — Supports 8- or 16-bit transfers. Motorola or Intel compatible. n 8-bit control I/O interface. n 256 memory-mapped I/O ports. n IEEE P1149.1 test port (JTAG boundary scan). n Full-speed in-circuit emulation hardware develop- ment system on-chip. n Supported by DSP1628 software and hardware development tools.

2 Description

The DSP1628 digital signal processor offers 80 MIPS and 52 MIPS operation at 2.7 V. Designed specifically for applications requiring low power dissipation in dig- ital cellular systems, the DSP1628 is a signal-coding device that can be programmed to perform a wide variety of fixed-point signal processing functions. The device is based on the DSP1600 core with a bit manipulation unit for enhanced signal coding effi- ciency, an external memory sequencer, an error cor- rection coprocessor (ECCP) for more efficient Viterbi decoding, and an 8-bit parallel host interface for hard- ware flexibility. The DSP1628 includes a mix of peripherals specifically intended to support process- ing-intensive but cost-sensitive applications in the area of digital wireless communications. The DSP1628x16 contains 16 Kwords of internal dual-port RAM (DPRAM), which allows simultaneous access to two RAM locations in a single instruction cy- cle. The DSP1628x08 supports the use of 8 Kwords of DPRAM. Both devices contain 48 Kwords of inter- nal ROM (IROM). The DSP1628 is object code compatible with the DSP1618, while providing more memory. The DSP1628 is pin compatible with the DSP1627. Note that TRST (JTAG test reset), replaces a V DD pin. The DSP1628 supports 2.7 V operation with flexible power management modes required for portable cel- lular terminals. Several control mechanisms achieve low-power operation, including a STOP pin for placing the DSP into a fully static, halted state and a program- mable power control register used to power down un- used on-chip I/O units. These power management modes allow for trade-offs between power reduction and wake-up latency requirements. During system standby, power consumption is reduced to less than µ The on-chip clock synthesizer can be driven by an external clock whose frequency is a fraction of the instruction rate. The device is packaged in a 144-pin PBGA, a 100-pin BQFP, or a 100-pin TQFP and is available with 19.2 ns and 12.5 ns instruction cycle times at 2.7 V. Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel Corporation. IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

DSP1628 Digital Signal Processor February 1997 2 Lucent Technologies Inc. Table of Contents Contents Page

6.4 Parallel Host Interface or Serial

11.1 100-Pin BQFP (Bumpered Quad

3 Pin Information

• Note the difference from the DSP1627 pinout.

Figure 1. DSP1628 BQFP Pin Diagram

• Note the difference from the DSP1627 pinout.

Figure 2. DSP1628 TQFP Pin Diagram

Note: Solder balls viewed thru package. Figure 3. 144-Pin Plastic Ball Grid Array (Top View)

are designed to remain at full CMOS levels when not driven by the DSP.

• 3-states when RSTB = 0, or by JTAG control.

† 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO which is free-running. ** See Section 7, Mask-Programmable Options. external pull-up resistors to SADD1 and/or SADD2 for proper initialization. Table 1. Pin Descriptions DB[15:0] I/O* External Memory Data Bus 15—0. Data Address 0x4000 to 0x40FF I/O Enable. Program Address External ROM Enable. G1 27 14 EXM I External ROM Enable. AB[15:0] O* External Memory Address Bus 15—0. L5 47 34 INT1 I Vectored Interrupt 1. M5 48 35 INT0 I Vectored Interrupt 0. L6 50 37 IACK O* Interrupt Acknowledge. M6 51 38 STOP I STOP Input Clock. L7 52 39 TRAP I/O* Nonmaskable Program Trap/Breakpoint Indication. M8 56 43 TCK I JTAG Test Clock. K10 65 52 VEC0/IOBIT7 I/O* Vectored Interrupt Indication 0/Status/Control Bit 7. L12 66 53 VEC1/IOBIT6 I/O* Vectored Interrupt Indication 1/Status/Control Bit 6. K11 67 54 VEC2/IOBIT5 I/O* Vectored Interrupt Indication 2/Status/Control Bit 5. K12 68 55 VEC3/IOBIT4 I/O* Vectored Interrupt Indication 3/Status/Control Bit 4. J11 69 56 IOBIT3/PB7 I/O* Status/Control Bit 3/PHIF Data Bus Bit 7. J12 70 57 IOBIT2/PB6 I/O* Status/Control Bit 2/PHIF Data Bus Bit 6.

Functional descriptions of pins 1—100 are found in Section 6, Signal Descriptions.

• 3-states when RSTB = 0, or by JTAG control.

† 3-states when RSTB = 0 and INT0 = 1. Output = 1 when RSTB = 0 and INT0 = 0, except CKO which is free-running. ** See Section 7, Mask-Programmable Options. external pull-up resistors to SADD1 and/or SADD2 for proper initialization. H11 71 58 IOBIT1/PB5 I/O* Status/Control Bit 1/PHIF Data Bus Bit 5. H12 72 59 IOBIT0/PB4 I/O* Status/Control Bit 0/PHIF Data Bus Bit 4. F11 75 62 DOEN2/PB2 I/O* SIO2 Data Output Enable/PHIF Data Bus Bit 2. F12 77 64 DI2/PB1 I/O* SIO2 Data Input/PHIF Data Bus Bit 1. E11 78 65 ICK2/PB0 I/O* SIO2 Input Clock/PHIF Data Bus Bit 0. D11 80 67 IBF2/PIBF O* SIO2 Input Buffer Full/PHIF Input Buffer Full. D12 81 68 OLD2/PODS I/O* SIO2 Output Load/PHIF Output Data Strobe. C11 82 69 ILD2/PIDS I/O* SIO2 Input Load/PHIF Input Data Strobe. C10 84 71 DO2/PSTAT I/O* SIO2 Data Output/PHIF Status Register Select. B12 85 72 OCK2/PCSN I/O* SIO2 Output Clock/PHIF Chip Select Not. B11 86 73 DOEN1 I/O* SIO1 Data Output Enable. I/O* SIO1 Multiprocessor Address. A11 90 77 SYNC1 I/O* SIO1 Multiprocessor Synchronization. B10 91 78 DO1 O* SIO1 Data Output. A10 92 79 OLD1 I/O* SIO1 Output Load. B9 93 80 OCK1 I/O* SIO1 Output Clock. A9 94 81 ICK1 I/O* SIO1 Input Clock. B8 95 82 ILD1 I/O* SIO1 Input Load. A8 96 83 DI1 I SIO1 Data Input. B7 98 85 IBF1 O* SIO1 Input Buffer Full. A7 99 86 OBE1 O* SIO1 Output Buffer Empty. C9 — — — — No Die Connect—unused.

DSP1628 Digital Signal Processor February 1997 8 Lucent Technologies Inc.

4 Hardware Architecture

The DSP1628 device is a 16-bit, fixed-point program- mable digital signal processor (DSP). The DSP1628 consists of a DSP1600 core together with on-chip mem- ory and peripherals. Added architectural features give the DSP1628 high program efficiency for signal coding applications.

4.1 DSP1628 Architectural Overview

Figure 4 shows a block diagram of the DSP1628. The following modules make up the DSP1628. DSP1600 Core The DSP1600 core is the heart of the DSP1628 chip. The core contains data and address arithmetic units, and control for on-chip memory and peripherals. The core provides support for external memory wait-states and on-chip dual-port RAM and features vectored inter- rupts and a trap mechanism. Dual-Port RAM (DPRAM) The DSP1628x16 contains 16 banks of zero wait-state memory and the DSP1628x08 contains 8 banks of zero wait-state memory. Each bank consists of 1K 16-bit words and has separate address and data ports to the instruction/coefficient and data memory spaces. A pro- gram can reference memory from either space. The DSP1600 core automatically performs the required mul- tiplexing. If references to both ports of a single bank are made simultaneously, the DSP1600 core automatically inserts a wait-state and performs the data port access first, followed by the instruction/coefficient port access. A program can be downloaded from slow, off-chip mem- ory into DPRAM, and then executed without wait-states. DPRAM is also useful for improving convolution perfor- mance in cases where the coefficients are adaptive. Since DPRAM can be downloaded through the JTAG port, full-speed remote in-circuit emulation is possible. DPRAM can also be used for downloading self-test code via the JTAG port. Read-Only Memory (ROM) The DSP1628 contains 48K 16-bit words of zero wait- state mask-programmable ROM for program and fixed coefficients. External Memory Multiplexer (EMUX) The EMUX is used to connect the DSP1628 to external memory and I/O devices. It supports read/write opera- tions from/to instruction/coefficient memory (X memory space) and data memory (Y memory space). The DSP1600 core automatically controls the EMUX. In- structions can transparently reference external memory from either set of internal buses. A sequencer allows a single instruction to access both the X and the Y exter- nal memory spaces. Clock Synthesis The DSP powers up with a 1X input clock (CKI/CKI2) as the source for the processor clock. An on-chip clock synthesizer (PLL) can also be used to generate the sys- tem clock for the DSP, which will run at a frequency mul- tiple of the input clock. The clock synthesizer is deselected and powered down on reset. For low-power operation, an internally generated slow clock can be used to drive the DSP. If both the clock synthesizer and the internally generated slow clock are selected, the slow clock will drive the DSP; however, the synthesizer will continue to run. The clock synthesizer and other programmable clock sources are discussed in Section 4.13. The use of these programmable clock sources for power management is discussed in Section 4.14.

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 9

4 Hardware Architecture (continued)

Bit Manipulation Unit (BMU) The BMU extends the DSP1600 core instruction set to provide more efficient bit operations on accumulators. The BMU contains logic for barrel shifting, normaliza- tion, and bit field insertion/extraction. The unit also con- tains a set of 36-bit alternate accumulators. The data in the alternate accumulators can be shuffled with the data in the main accumulators. Flags returned by the BMU mesh seamlessly with the DSP1600 conditional instruc- tions. Error Correction Coprocessor (ECCP) The ECCP performs full Viterbi decoding with instruc- tions for MLSE equalization and convolutional decod- ing. It is designed for 2-tap to 6-tap MLSE equalization with Euclidean branch metrics and rate 1/1 to 1/6 con- volutional decoding using constraint lengths from 2 to 7 with Euclidean or Manhattan branch metrics. Two vari- ants of soft-decoded symbols, as well as hard-decoded symbols may be programmed. The ECCP operates in parallel with the DSP1600 core, increasing the through- put rate. Single instruction Viterbi decoding provides significant code compression required for single DSP solutions in modern digital cellular applications. The ECCP is the source of two interrupts and one flag to the DSP1600 core. Bit Input/Output (BIO) The BIO provides convenient and efficient monitoring and control of eight individually configurable pins. When configured as outputs, the pins can be individually set, cleared, or toggled. When configured as inputs, individ- ual pins or combinations of pins can be tested for pat- terns. Flags returned by the BIO mesh seamlessly with conditional instructions. Serial Input/Output Units (SIO and SIO2) SIO and SIO2 offer asynchronous, full-duplex, double- buffered channels that operate at up to 25 Mbits/s (for 20 ns instruction cycle in a nonmultiprocessor configu- ration), and easily interface with other Lucent Technol- ogies fixed-point DSPs in a multiple-processor environment. Commercially available codecs and time- division multiplex (TDM) channels can be interfaced to the serial I/O ports with few, if any, additional compo- nents. SIO2 is identical to SIO. An 8-bit serial protocol channel may be transmitted in addition to the address of the called processor in multi- processor mode. This feature is useful for transmitting high-level framing information or for error detection and correction. SIO2 and BIO are pin-multiplexed with the PHIF.

• These registers are accessible through the pins only.

Figure 4. DSP1628 Block Diagram

Table 2. DSP1628 Block Diagram Legend aa<0—1> Alternate Accumulators. ar<0—3> Auxiliary BMU Registers. BREAKPOINT Four Instruction Breakpoint Registers. BYPASS JTAG Bypass Register. cbit Control Register for BIO. Dual-Port RAM Internal RAM (16 Kwords for DSP1628x16, 8 Kwords for DSP1628x08). ECCP Error Correction Coprocessor. ear Error Correction Coprocessor Address Register. edr Error Correction Coprocessor Data Register. eir Error Correction Coprocessor Instruction Register. EMUX External Memory Multiplexer. HDS Hardware Development System. ID JTAG Device Identification Register. ioc I/O Configuration Register. JCON JTAG Configuration Registers. jtag 16-bit Serial/Parallel Register. pdx0(in) Parallel Data Transmit Input Register 0. pdx0(out) Parallel Data Transmit Output Register 0. PHIF Parallel Host Interface. phifc Parallel Host Interface Control Register. pllc Phase-Locked Loop Control Register. powerc Power Control Register. PSTAT Parallel Host Interface Status Register. saddx Multiprocessor Protocol Register. saddx2 Multiprocessor Protocol Register for SIO2. sbit Status Register for BIO. sdx(in) Serial Data Transmit Input Register. sdx2(in) Serial Data Transmit Input Register for SIO2. sdx(out) Serial Data Transmit Output Register. sdx2(out) Serial Data Transmit Output Register for SIO2. SIO Serial Input/Output Unit. SIO2 Serial Input/Output Unit #2. sioc Serial I/O Control Register. sioc2 Serial I/O Control Register for SIO2. srta Serial Receive/Transmit Address Register. srta2 Serial Receive/Transmit Address Register for SIO2. tdms Serial I/O Time-division Multiplex Signal Control Register. tdms2 Serial I/O Time-division Multiplex Signal Control Register for SIO2. timer0 Timer Running Count Register. timerc Timer Control Register. TRACE Program Discontinuity Trace Buffer. XAB Program Memory Address Bus. XDB Program Memory Data Bus. YAB Data Memory Address Bus.

DSP1628 Digital Signal Processor February 1997 12 Lucent Technologies Inc. Parallel Host Interface (PHIF) The PHIF is a passive, 8-bit parallel port which can in- terface to an 8-bit bus containing other Lucent Technol- ogies DSPs (e.g., DSP1620, DSP1627, DSP1628, DSP1629, DSP1611, DSP1616, DSP1617, DSP1618), microprocessors, or peripheral I/O devices. The PHIF port supports either Motorola or Intel protocols, as well as 8-bit or 16-bit transfers, configured in software. The port data rate depends upon the instruction cycle rate. A 25 ns instruction cycle allows the PHIF to support data rates up to 11.85 Mbytes/s, assuming the external host device can transfer 1 byte of data in 25 ns. The PHIF is accessed in two basic modes, 8-bit or 16-bit mode. In 16-bit mode, the host determines an ac- cess of the high or low byte. In 8-bit mode, only the low byte is accessed. Software-programmable features al- low for a glueless host interface to microprocessors (see Section 4.8, Parallel Host Interface). Timer The timer can be used to provide an interrupt at the ex- piration of a programmed interval. The interrupt may be single or repetitive. More than nine orders of magnitude of interval selection are provided. The timer may be stopped and restarted at any time. Hardware Development System (HDS) Module The on-chip HDS performs instruction breakpointing and branch tracing at full speed without additional off- chip hardware. Using the JTAG port, the breakpointing is set up, and the trace history is read back. The port works in conjunction with the HDS code in the on-chip ROM and the hardware and software in a remote com- puter. The HDS code must be linked to the user's appli- cation code and reside in the first 4 Kwords of ROM. The on-chip HDS cannot be used with the secure ROM masking option (see Section 7.2, ROM Security Op- tions). Four hardware breakpoints can be set on instruction ad- dresses. A counter can be preset with the number of breakpoints to receive before trapping the core. Break- points can be set in interrupt service routines. Alternate- ly, the counter can be preset with the number of cache instructions to execute before trapping the core. Every time the program branches instead of executing the next sequential instruction, the addresses of the in- structions executed before and after the branch are caught in circular memory. The memory contains the last four pairs of program discontinuities for hardware tracing. In systems with multiple processors, the processors may be configured such that any processor reaching a breakpoint will cause all the other processors to be trapped (see Section 4.3, Interrupts and Trap). Pin Multiplexing In order to allow flexible device interfacing while main- taining a low package pin count, the DSP1628 multi- plexes 16 package pins between BIO, PHIF, VEC[3:0], and SIO2. Upon reset, the vectored interrupt indication signals, VEC[3:0], are connected to the package pins while IOBIT[4:7] are disconnected. Setting bit 12, EBIOH, of the ioc register connects IOBIT[4:7] to the package pins and disconnects VEC[3:0]. Upon reset, the parallel host interface (PHIF) is con- nected to the package pins while the second serial port (SIO2) and IOBIT[3:0] are disconnected. Setting bit 10, ESIO2, of the ioc register connects the SIO2 and IOBIT[3:0] and disconnects the PHIF. Power Management Many applications, such as portable cellular terminals, require programmable sleep modes for power manage- ment. There are three different control mechanisms for achieving low-power operation: the powerc control register, the STOP pin, and the AWAIT bit in the alf reg- ister. The AWAIT bit in the alf register allows the pro- cessor to go into a power-saving standby mode until an interrupt occurs. The powerc register configures vari- ous power-saving modes by controlling internal clocks and peripheral I/O units. The STOP pin controls the in- ternal processor clock. The various power management options may be chosen based on power consumption and/or wake-up latency requirements.

4.2 DSP1600 Core Architectural Overview

Figure 5 shows a block diagram of the DSP1600 core. System Cache and Control Section (SYS) This section of the core contains a 15-word cache mem- ory and controls the instruction sequencing. It handles vectored interrupts and traps, and also provides decod- ing for registers outside of the DSP1600 core. SYS stretches the processor cycle if wait-states are required (wait-states are programmable for external memory ac- cesses). SYS sequences downloading via JTAG of self- test programs to on-chip, dual-port RAM. The cache loop iteration count can be specified at run time under program control as well as at assembly time.

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 13 Data Arithmetic Unit (DAU) The data arithmetic unit (DAU) contains a 16 x 16-bit parallel multiplier that generates a full 32-bit product in one instruction cycle. The product can be accumulated with one of two 36-bit accumulators. The accumulator data can be directly loaded from, or stored to, memory in two 16-bit words with optional saturation on overflow. The arithmetic logic unit (ALU) supports a full set of arithmetic and logical operations on either 16- or 32-bit data. A standard set of flags can be tested for condition- al ALU operations, branches, and subroutine calls. This procedure allows the processor to perform as a power- ful 16- or 32-bit microprocessor for logical and control applications. The available instruction set is compatible with the DSP1618 instruction set. See Section 5.1 for more information on the instruction set. The user also has access to two additional DAU regis- ters. The psw register contains status information from the DAU (see Table 30, Processor Status Word Regis- ter). The arithmetic control register, auc, is used to con- figure some of the features of the DAU (see Table 31) including single-cycle squaring. The auc register align- ment field supports an arithmetic shift left by one and left or right by two. The auc register is cleared by reset. The counters c0 to c2 are signed, 8 bits wide, and may be used to count events such as the number of times the program has executed a sequence of code. They are controlled by the conditional instructions and pro- vide a convenient method of program looping. Y Space Address Arithmetic Unit (YAAU) The YAAU supports high-speed, register-indirect, com- pound, and direct addressing of data (Y) memory. Four general-purpose, 16-bit registers, r0 to r3, are available in the YAAU. These registers can be used to supply the read or write addresses for Y space data. The YAAU also decodes the 16-bit data memory address and out- puts individual memory enables for the data access. The YAAU can address the six 1 Kword banks of on- chip DPRAM or three external data memory segments. Up to 48 Kwords of off-chip RAM are addressable, with 16K addresses reserved for internal RAM. Two 16-bit registers, rb and re, allow zero-overhead modulo addressing of data for efficient filter implemen- tations. Two 16-bit signed registers, j and k, are used to hold user-defined postmodification increments. Fixed increments of +1, –1, and +2 are also available. Four compound-addressing modes are provided to make read/write operations more efficient. The YAAU allows direct (or indexed) addressing of data memory. In direct addressing, the 16-bit base register (ybase) supplies the 11 most significant bits of the ad- dress. The direct data instruction supplies the remaining 5 bits to form an address to Y memory space and also specifies one of 16 registers for the source or destina- tion. X Space Address Arithmetic Unit (XAAU) The XAAU supports high-speed, register-indirect, in- struction/coefficient memory addressing with postmodi- fication of the register. The 16-bit pt register is used for addressing coefficients. The signed register i holds a user-defined postincrement. A fixed postincrement of +1 is also available. Register PC is the program counter. Registers pr and pi hold the return address for subroutine calls and interrupts, respectively. The XAAU decodes the 16-bit instruction/coefficient ad- dress and produces enable signals for the appropriate X memory segment. The addressable X segments are

48 Kwords of internal ROM, up to 16 Kwords of DPRAM

for the DSP1628x16 or up to 8 Kwords of DPRAM for the DSP1628x08, and external ROM. The locations of these memory segments depend upon the memory map selected (see Table 5). A security mode can be selected by mask option. This prevents unauthorized access to the contents of on-chip ROM (see Section 7, Mask-Programmable Options).

4.3 Interrupts and Trap

The DSP1628 supports prioritized, vectored interrupts and a trap. The device has eight internal hardware sources of program interrupt and two external interrupt pins. Additionally, there is a trap pin and a trap signal from the hardware development system (HDS). A soft- ware interrupt is available through the icall instruction. The icall instruction is reserved for use by the HDS. Each of these sources of interrupt and trap has a unique vector address and priority assigned to it. DSP16A in- terrupt compatibility is not maintained. The software interrupt and the traps are always enabled and do not have a corresponding bit in the ins register. Other vectored interrupts are enabled in the inc register (see Table 33, Interrupt Control (inc) Register) and monitored in the ins register (see Table 34, Interrupt Status (ins) Register). When the DSP1628 goes into an interrupt or trap service routine, the IACK pin is assert- ed. In addition, pins VEC[3:0] encode which interrupt/ trap is being serviced. Table 4 details the encoding used for VEC[3:0].

Figure 5. DSP1600 Core Block Diagram

• F3 ALU instructions with immediates require specifying the high half of the accumulators as a0h and a1h.

Table 3. DSP1600 Core Block Diagram Legend 16 x 16 MPY 16-bit x 16-bit Multiplier. a0—a1 Accumulators 0 and 1 (16-bit halves specified as a0, a0l, a1, and a1l)*. ALU/SHIFT Arithmetic Logic Unit/Shifter. auc Arithmetic Unit Control. DAU Digital Arithmetic Unit. i Increment Register for the X Address Space. j Increment Register for the Y Address Space. k Increment Register for the Y Address Space. mwait External Memory Wait-states Register. p Product Register (16-bit halves specified as p, pl). pi Program Interrupt Return Register. r0—r3 Y Address Space Pointers. rb Modulo Addressing Register (begin address). re Modulo Addressing Register (end address). SYS System Cache and Control Section. x Multiplier Input Register. XAAU X Space Address Arithmetic Unit. YAAU Y Space Address Arithmetic Unit. ybase Direct Addressing Base Register. y DAU Register (16-bit halves specified as y, yl).

DSP1628 Digital Signal Processor February 1997 16 Lucent Technologies Inc. Vectored interrupts are serviced only after the execution of an interruptible instruction. If more than one vectored interrupt is asserted at the same time, the in- terrupts are serviced sequentially according to their as- signed priorities. See Table 4 for the priorities assigned to the vectored interrupts. Interrupt service routines, branch and conditional branch instructions, cache loops, and instructions that only decrement one of the RAM pointers, r0 to r3 (e.g., *r3− −), are not interrupt- ible. A trap is similar to an interrupt, but it gains control of the processor by branching to the trap service routine even when the current instruction is noninterruptible. It may not be possible to return to normal instruction execution from the trap service routine since the machine state cannot always be saved. In particular, program execu- tion cannot be continued from a trapped cache loop or interrupt service routine. While in a trap service routine, another trap is ignored. When set to 1, the status bits in the ins register indicate that an interrupt has occurred. The processor must reach an interruptible state (completion of an interrupt- ible instruction) before an enabled vectored interrupt will be acted on. An interrupt will not be serviced if it is not enabled. Polled interrupt service can be implemented by disabling the interrupt in the inc register and then polling the ins register for the expected event. Vectored Interrupts Tables 33 and 34 show the inc and ins registers. A logic 1 written to any bit of inc enables (or unmasks) the as- sociated interrupt. If the bit is cleared to a logic 0, the in- terrupt is masked. Note that neither the software interrupt nor traps can be masked. The occurrence of an interrupt that is not masked will cause the program execution to transfer to the memory location pointed to by that interrupt's vector address, assuming no other interrupt is being serviced (see Table 4, Interrupt Vector Table). The occurrence of an interrupt that is masked causes no automatic processor action, but will set the corresponding status bit in the ins register. If a masked interrupt occurs, it is latched in the ins register, but the interrupt is not taken. When un- latched, this latched interrupt will initiate automatic pro- cessor interrupt action. See the DSP1611/17/18/27 Digital Signal Processor Information Manual for a more detailed description of the interrupts. Signaling Interrupt Service Status Five pins of DSP1628 are devoted to signaling interrupt service status. The IACK pin goes high while any inter- rupt or user trap is being serviced, and goes low when the ireturn instruction from the service routine is issued. Four pins, VEC[3:0], carry a code indicating which of the interrupts or trap is being serviced. Table 4 contains the encodings used by each interrupt. Traps due to HDS breakpoints have no effect on either the IACK or VEC[3:0] pins. Instead, they show the inter- rupt state or interrupt source of the DSP when the trap occurred. Clearing Interrupts The PHIF interrupts (PIBF and POBE) are cleared by reading or writing the parallel host interface data trans- mit registers pdx0[in] and pdx0[out], respectively. The SIO and SIO2 interrupts (IBF, IBF2, OBE, and OBE2) are cleared one instruction cycle AFTER reading or writ- ing the serial data registers, (sdx[in], sdx2[in], sdx[out], or sdx2[out]). To account for this added latency, the user must ensure that a single instruction (NOP or any other valid DSP16XX instruction) follows the sdx regis- ter read or write instruction prior to exiting an interrupt service routine (via an ireturn or goto pi instruction) or before checking the ins register for the SIO flag status. Adding this instruction ensures that interrupts are not reported incorrectly following an ireturn or that stale flags are not read from the ins register.The JTAG inter- rupt (JINT) is cleared by reading the jtag register. Five of the vectored interrupts are cleared by writing to the ins register. Writing a 1 to the INT0, INT1, EREADY, EOVF, or TIME bits in the ins will cause the corre- sponding interrupt status bit to be cleared to a logic 0. The status bit for these vectored interrupts is also cleared when the ireturn instruction is executed, leaving set any other vectored interrupts that are pending. Traps The TRAP pin of the DSP1628 is a bidirectional signal. At reset, it is configured as an input to the processor. Asserting the TRAP pin will force a user trap. The trap mechanism is used for two purposes. It can be used by an application to rapidly gain control of the processor for asynchronous time-critical event handling (typically for catastrophic error recovery). It is also used by the HDS for breakpointing and gaining control of the processor. Separate vectors are provided for the user trap (0x46) and the HDS trap (0x3). Traps are not maskable.

routine, the value of the pi register may be overwritten. service routine from a user trap (0x46) service routine. ing a cache loop is also not possible. the HDS code, if present, resides in the on-chip ROM. cessor's TRAP pin is configured to be an output. wakes up and continues executing. terrupt service routine is executed.

• Traps due to HDS breakpoints have no effect on VEC[3:0] pins.

Table 4. Interrupt Vector Table

DSP1628 Digital Signal Processor February 1997 18 Lucent Technologies Inc. The AWAIT bit should be set from within the cache if the code which is executing resides in external ROM where more than one wait-state has been programmed. This ensures that an interrupt will not disturb the device from completely entering the sleep state. For additional power savings, set ioc = 0x0180 and tim- erc = 0x0040 in addition to setting alf = 0x8000. This will hold the CKO pin low and shut down the timer and prescaler (see Table 42 and Table 35). For a description of the control mechanisms for putting the DSP into low-power modes, see Section 4.13, Pow- er Management.

4.4 Memory Maps and Wait-States

The DSP1600 core implements a modified Harvard ar- chitecture that has separate on-chip 16-bit address and data buses for the instruction/coefficient (X) and data (Y) memory spaces. Table 5 shows the instruction/coef- ficient memory space maps for both the DSP1628x16 and DSP1628x08. The DSP1628 provides a multiplexed external bus which accesses external RAM (ERAM) and ROM (ER- OM). Programmable wait-states are provided for exter- nal memory accesses. The instruction/coefficient memory map is configurable to provide application flex- ibility. Table 6 shows the data memory space, which has one map. Instruction/Coefficient Memory Map Selection In determining which memory map to use, the proces- sor evaluates the state of two parameters. The first is the LOWPR bit (bit 14) of the alf register. The LOWPR bit of the alf register is initialized to 0 automatically at re- set. LOWPR controls the starting address in memory assigned to 1K banks of dual-port RAM. If LOWPR is low, internal dual-port RAM begins at address 0xC000. If LOWPR is high, internal dual-port RAM begins at ad- dress 0x0. LOWPR also moves IROM from 0x0 in MAP1 to 0x4000 in MAP3, and EROM from 0x0 in MAP2 to 0x4000 in MAP4. The second parameter is the value at reset of the EXM pin (pin 27 or pin 14, depending upon the package type). EXM determines whether the internal 48 Kwords ROM (IROM) will be addressable in the memory map. The Lucent Technologies development system tools, together with the on-chip HDS circuitry and the JTAG port, can independently set the memory map. Specifi- cally, during an HDS trap, the memory map is forced to MAP1. The user's map selection is restored when the trap service routine has completed execution. MAP1 MAP1 has the IROM starting at 0x0 and 1 Kword banks of DPRAM starting at 0xC000. MAP1 is used if DSP1628 has EXM low at reset and the LOWPR pa- rameter is programmed to zero. It is also used during an HDS trap. MAP2 MAP2 differs from MAP1 in that the lowest 48 Kwords reference external ROM (EROM). MAP2 is used if EXM is high at reset, the LOWPR parameter is programmed to zero, and an HDS trap is not in progress. MAP3 MAP3 has the 1 Kword banks of DPRAM starting at address 0x0. In MAP3, the 48 Kwords of IROM start at 0x4000. MAP3 is used if EXM is low at reset, the LOWPR bit is programmed to 1, and an HDS trap is not in progress. Note that this map is not available if the secure mask-programmable option has been ordered. MAP4 MAP4 differs from MAP3 in that addresses above 0x4000 reference external ROM (EROM). This map is used if the LOWPR bit is programmed to 1, an HDS trap is not in progress, and, either EXM is high during reset, or the secure mask-programmable option has been or- dered. Whenever the chip is reset using the RSTB pin, the de- fault memory map will be MAP1 or MAP2, depending upon the state of the EXM pin at reset. A reset through the HDS will not reinitialize the alf register, so the previ- ous memory map is retained. Boot from External ROM After RSTB goes from low to high, the DSP1628 comes out of reset and fetches an instruction from address zero of the instruction/coefficient space. The physical location of address zero is determined by the memory map in effect. If EXM is high at the rising edge of RSTB, MAP2 is selected. MAP2 has EROM at location zero; thus, program execution begins from external memory. If EXM is high and INT1 is low when RSTB rises, the mwait register defaults to 15 wait-states for all external memory segments. If INT1 is high, the mwait register defaults to 0 wait-states.

Table 5. Instruction/Coefficient Memory Maps

• MAP1 is set automatically during an HDS trap. The user-selected map is restored at the end of the HDS trap service routine.

† LOWPR is an alf register bit. The Lucent Technologies development system tools can independently set the memory map. ‡ MAP3 is not available if the secure mask-programmable option is selected.

Table 6. Data Memory Maps ence high external data RAM (ERAMHI). ured in the appropriate field of the mwait register.

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 21

4.5 External Memory Interface (EMI)

The external memory interface supports read/write op- erations from instruction/coefficient memory, data memory, and memory-mapped I/O devices. The DSP1628 provides a 16-bit external address bus, AB[15:0], and a 16-bit external data bus, DB[15:0]. These buses are multiplexed between the internal bus- es for the instruction/coefficient memory and the data memory. Four external memory segment enables, ERAMLO, IO, ERAMHI, and EROM, select the external memory segment to be addressed. If a data memory location with an address between 0x4100 and 0x7FFF is addressed, ERAMLO is asserted low. If one of the 256 external data memory locations, with an address greater than or equal to 0x4000, and less than or equal to 0x40FF, is addressed, IO is asserted low. IO is intended for memory-mapped I/O. If a data memory location with an address greater than or equal to 0x8000 is addressed, ERAMHI is asserted low. When the external instruction/coefficient memory is addressed, EROM is asserted low. The flexibility provided by the programmable options of the external memory interface (see Table 40, mwait Register and Table 42, ioc Register) allows the DSP1628 to interface gluelessly with a variety of com- mercial memory chips. Each of the four external memory segments, ERAMLO, IO, ERAMHI, and EROM, has a number of wait-states that is programmable (from 0 to 15) by writing to the mwait register. When the program references memory in one of the four external segments, the internal multi- plexer is automatically switched to the appropriate set of internal buses, and the associated external enable of ERAMLO, IO, ERAMHI, or EROM is issued. The exter- nal memory cycle is automatically stretched by the num- ber of wait-states in the appropriate field of the mwait register. When writing to external memory, the RWN pin goes low for the external cycle. The external data bus, DB[15:0], is driven by the DSP1628 starting halfway through the cycle. The data driven on the external data bus is automatically held after the cycle for one addi- tional clock period unless an external read cycle imme- diately follows. The DSP1628 has one external address bus and one external data bus for both memory spaces. Since some instructions provide the capability of simultaneous ac- cess to both X space and Y space, some provision must be made to avoid collisions for external accesses. The DSP1628 has a sequencer that does the external X ac- cess first, and then the external Y access, transparently to the programmer. Wait-states are maintained as pro- grammed in the mwait register. For example, let two in- structions be executed: the first reads a coefficient from EROM and writes data to ERAM; the second reads a coefficient from EROM and reads data from ERAM. The sequencer carries out the following steps at the external memory interface: read EROM, write ERAM, read ER- OM, and read ERAM. Each step is done in sequential one-instruction cycle steps, assuming zero wait-states are programmed. Note that the number of instruction cycles taken by the two instructions is four. Also, in this case, the write hold time is zero. The DSP1628 allows writing into external instruction/ coefficient memory. By setting bit 11, WEROM, of the ioc register (see Table 42), writing to (or reading from) data memory or memory-mapped I/O asserts the EROM strobe instead of ERAMLO, IO, or ERAMHI. Therefore, with WEROM set, EROM appears in both Y space (replacing ERAM) and X space, in its normal po- sition. Bit 14 of the ioc register (see Table 42), EXTROM, may be used with WEROM to download to a full 64K of ex- ternal memory. When WEROM and EXTROM are both asserted, address bit 15 (AB15) is held low, aliasing the upper 32K of external memory into the lower 32K. When an access to internal memory is made, the AB[15:0] bus holds the last valid external memory ad- dress. Asserting the RSTB pin low 3-states the AB[15:0] bus. After reset, the AB[15:0] value is undefined. The leading edge of the memory segment enables can be delayed by approximately one-half a CKO period by programming the ioc register (see Table 42). This is used to avoid a situation in which two devices drive the data bus simultaneously. Bits 7, 8, and 13 of the ioc register select the mode of operation for the CKO pin (see Table 42). Available op- tions are a free-running unstretched clock, a wait-stated sequenced clock (runs through two complete cycles during a sequenced external memory access), and a wait-stated clock based on the internal instruction cycle. These clocks drop to the low-speed internal ring oscilla- tor when SLOWCKI is enabled (see 4.13, Power Man- agement). The high-to-low transitions of the wait-stated clock are synchronized to the high-to-low transition of the free-running clock. Also, the CKO pin provides ei- ther a continuously high level, a continuously low level, or changes at the rate of the internal processor clock. This last option, only available with the small-signal in- put clock options, enables the DSP1628 CKI input buff- er to deliver a full-rate clock to other devices while the DSP1628 itself is in one of the low-power modes.

DSP1628 Digital Signal Processor February 1997 22 Lucent Technologies Inc.

4.6 Bit Manipulation Unit (BMU)

The BMU interfaces directly to the main accumulators in the DAU providing the following features: n Barrel shifting—logical and arithmetic, left and right shift n Normalization and extraction of exponent n Bit-field extraction and insertion These features increase the efficiency of the DSP in ap- plications such as control or data encoding and decod- ing. For example, data packing and unpacking, in which short data words are packed into one 16-bit word for more efficient memory storage, is very easy. In addition, the BMU provides two auxiliary accumula- tors, aa0 and aa1. In one instruction cycle, 36-bit data can be shuffled, or swapped, between one of the main accumulators and one of the alternate accumulators. The ar<0—3> registers are 16-bit registers that control the operations of the BMU. They store a value that de- termines the amount of shift or the width and offset fields for bit extraction or insertion. Certain operations in the BMU set flags in the DAU psw register and the alf register (see Table 30, Processor Status Word (psw ) Register, and Table 39, alf Register). The ar<0—3> registers can also be used as general-purpose regis- ters. The BMU instructions are detailed in Section 5.1. For a thorough description of the BMU, see the DSP1611/17/ 18/27 Digital Signal Processor Information Manual.

4.7 Serial I/O Units (SIOs)

The serial I/O ports on the DSP1628 device provide a serial interface to many codecs and signal processors with little, if any, external hardware required. Each high- speed, double-buffered port (sdx and sdx2) supports back-to-back transmissions of data. SIO and SIO2 are identical. The output buffer empty (OBE and OBE2) and input buffer full (IBF and IBF2) flags facilitate the read- ing and/or writing of each serial I/O port by program- or interrupt-driven I/O. There are four selectable active clock speeds. A bit-reversal mode provides compatibility with either the most significant bit (MSB) first or least significant bit (LSB) first serial I/O formats (see Table 26, Serial I/O Control Registers (sioc and sioc2)). A multiprocessor I/O configuration is supported. This feature allows up to eight DSP161X devices to be connected together on an SIO port without requiring external glue logic. The serial data may be internally looped back by setting the SIO loopback control bit, SIOLBC, of the ioc regis- ter. SIOLBC affects both the SIO and SIO2. The data output signals are wrapped around internally from the output to the input (DO1 to DI1 and DO2 to DI2). To ex- ercise loopback, the SIO clocks (ICK1, ICK2, OCK1, and OCK2) should either all be in the active mode, 16-bit condition, or each pair should be driven from one external source in passive mode. Similarly, pins ILD1 (ILD2) and OLD1 (OLD2) must both be in active mode or tied together and driven from one external frame clock in passive mode. During loopback, DO1, DO2, DI1, DI2, ICK1, ICK2, OCK1, OCK2, ILD1, ILD2, OLD1, OLD2, SADD1, SADD2, SYNC1, SYNC2, DOEN1, and DOEN2 are 3-stated. Setting DODLY = 1 (sioc and sioc2) delays DO by one phase of OCK so that DO changes on the falling edge of OCK instead of the rising edge (DODLY = 0). This re- duces the time available for DO to drive DI and to be val- id for the rising edge of ICK, but increases the hold time on DO by half a cycle on OCK. Programmable Modes Programmable modes of operation for the SIO and SIO2 are controlled by the serial I/O control registers (sioc and sioc2). These registers, shown in Table 26, are used to set the ports into various configurations. Both input and output operations can be independently configured as either active or passive. When active, the DSP1628 generates load and clock signals. When pas- sive, load and clock signal pins are inputs. Since input and output can be independently config- ured, each SIO has four different modes of operation. Each of the sioc registers is also used to select the fre- quency of active clocks for that SIO. Finally, these reg- isters are used to configure the serial I/O data formats. The data can be 8 or 16 bits long, and can also be input/ output MSB first or LSB first. Input and output data for- mats can be independently configured. Multiprocessor Mode The multiprocessor mode allows up to eight devices that support multiprocessor mode (codecs or DSP16XX devices) to be connected together to provide data trans- mission among any of the multiprocessor devices in the system. Either of the DSP1628’s SIO ports (SIO or SIO2) may be independently used for the multiproces- sor mode. The multiprocessor interface is a four-wire in- terface, consisting of a data channel, an address/ protocol channel, a transmit/receive clock, and a sync signal (see Figure 6). The DI1 and DO1 pins of all the DSPs are connected to transmit and receive the data channel. The SADD1 pins of all the DSPs are connect- ed to transmit and receive the address/protocol chan- nel. ICK1 and OCK1 should be tied together and driven from one source. The SYNC1 pins of all the DSPs are connected. In the configuration shown in Figure 6, the master DSP (DSP0) generates active SYNC1 and OCK1 signals while the slave DSPs use the SYNC1 and OCK1 signals in passive mode to synchronize operations. In addition, all DSPs must have their ILD1 and OLD1 signals in ac- tive mode.

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 23 While ILD1 and OLD1 are not required externally for multiprocessor operation, they are used internally in the DSP's SIO. Setting the LD field of the master's sioc reg- ister to a logic level 1 will ensure that the active genera- tion of SYNC1, ILD1, and OLD1 is derived from OCK1 (see Table 26). With this configuration, all DSPs should use ICK1 (tied to OCK1) in passive mode to avoid con- flicts on the clock (CK) line (see the DSP1611/17/18/27 Digital Signal Processor Information Manual for more information). Four registers (per SIO) configure the multiprocessor mode: the time-division multiplexed slot register (tdms or tdms2 ), the serial receive and transmit address reg- ister (srta or srta2), the serial data transmit register (sdx or sdx2), and the multiprocessor serial address/ protocol register (saddx or saddx2). Multiprocessor mode requires no external logic and uses a TDM interface with eight 16-bit time slots per frame. The transmission in any time slot consists of 16 bits of serial data in the data channel and 16 bits of address and protocol information in the address/proto- col channel. The address information consists of the transmit address field of the srta register of the trans- mitting device. The address information is transmitted concurrently with the transmission of the first 8 bits of data. The protocol information consists of the transmit protocol field written to the saddx register and is trans- mitted concurrently with the last 8 bits of data (see Table 29, Multiprocessor Protocol Register). Data is re- ceived or recognized by other DSP(s) whose receive address matches the address in the address/protocol channel. Each SIO port has a user-programmable re- ceive address and transmit address associated with it. The transmit and receive addresses are programmed in the srta register. In multiprocessor mode, each device can send data in a unique time slot designated by the tdms register transmit slot field (bits 7—0). The tdms register has a fully decoded transmit slot field in order to allow one DSP1628 device to transmit in more than one time slot. This procedure is useful for multiprocessor systems with less than eight DSP1628 devices when a higher bandwidth is necessary between certain devices in that system. The DSP operating during time slot 0 also drives SYNC1. In order to prevent multiple bus drivers, only one DSP can be programmed to transmit in a particular time slot. In addition, it is important to note that the address/pro- tocol channel is 3-stated in any time slot that is not being driven. Therefore, to prevent spurious inputs, the address/pro- tocol channel should be pulled up to V DD with a 5 kΩ re- sistor, or it should be guaranteed that the bus is driven in every time slot. (If the SYNC1 signal is externally gen- erated, then this pull-up is required for correct initializa- tion.) Each SIO also has a fully decoded transmitting address specified by the srta register transmit address field (bits 7—0). This is used to transmit information regarding the destination(s) of the data. The fully decoded receive ad- dress specified by the srta register receive address field (bits 15—8) determines which data will be received. The SIO protocol channel data is controlled via the saddx register. When the saddx register is written, the lower 8 bits contain the 8-bit protocol field. On a read, the high- order 8 bits read from saddx are the most recently re- ceived protocol field sent from the transmitting DSP's saddx output register. The low-order 8 bits are read as 0s. An example use of the protocol channel is to use the top 3 bits of the saddx value as an encoded source address for the DSPs on the multiprocessor bus. This leaves the remaining 5 bits available to convey additional control information, such as whether the associated field is an opcode or data, or whether it is the last word in a trans- fer, etc. These bits can also be used to transfer parity in- formation about the data. Alternatively, the entire field can be used for data transmission, boosting the band- width of the port by 50%. Using SIO2 The SIO2 functions the same as the SIO. Please refer to Pin Multiplexing in Section 4.1 for a description of pin multiplexing of BIO, PHIF, VEC[3:0], and SIO2.

Figure 6. Multiprocessor Communication and Connections

4.8 Parallel Host Interface (PHIF)

the programmable options for this port. Intel and Motorola protocols. causes the DSP1628 device to recognize an interrupt. register. Setting PMODE selects 16-bit transfer mode. ble through bit 2, PSTRB, of the phifc register.

polarity of the POBE flag in the status register, PSTAT, can be changed. PSOBEF has no effect on the POBE pin. Please refer to Pin Multiplexing in Section 4.1 for a description of BIO, PHIF, VEC[3:0], and SIO2 pins. Table 7. PHIF Function (8-bit and 16-bit Modes) Table 8. pstat Register as Seen on PB[7:0]

4.9 Bit Input/Output Unit (BIO)

(DIREC[7:0]) controls the direction of each of the pins. sbit register is cleared upon reset. rection selected for the associated IOBIT pin. the alf register (see Table 39). description of BIO, PHIF, VEC[3:0], and SIO2 pins. Table 9. BIO Operations

DSP1628 Digital Signal Processor February 1997 26 Lucent Technologies Inc.

4.10 Timer

The interrupt timer is composed of the timerc (control) register, the timer0 register, the prescaler, and the counter itself. The timer control register (see Table 35, timerc Register) sets up the operational state of the tim- er and prescaler. The timer0 register is used to hold the counter reload value (or period register) and to set the initial value of the counter. The prescaler slows the clock to the timer by a number of binary divisors to allow for a wide range of interrupt delay periods. The counter is a 16-bit down counter that can be loaded with an arbitrary number from software. It counts down to 0 at the clock rate provided by the prescaler. Upon reaching 0 count, a vectored interrupt to program ad- dress 0x08 is issued to the DSP1628, providing the in- terrupt is enabled (bit 8 of inc and ins registers). The counter will then either wait in an inactive state for an- other command from software, or will automatically re- peat the last interrupting period, depending upon the state of the RELOAD bit in the timerc register. When RELOAD is 0, the counter counts down from its initial value to 0, interrupts the DSP1628, and then stops, remaining inactive until another value is written to the timer0 register. Writing to the timer0 register caus- es both the counter and the period register to be written with the specified 16-bit number. When RELOAD is 1, the counter counts down from its initial value to 0, inter- rupts the DSP1628, automatically reloads the specified initial value from the period register into the counter, and repeats indefinitely. This provides for either a single timed interrupt event or a regular interrupt clock of arbi- trary period. The timer can be stopped and started by software, and can be reloaded with a new period at any time. Its count value, at the time of the read, can also be read by soft- ware. Due to pipeline stages, stopping and starting the timer may result in one inaccurate count or prescaled period. When the DSP1628 is reset, the bottom 6 bits of the timerc register and the timer0 register and counter are initialized to 0. This sets the prescaler to CKO/2 turns off the reload feature, disables timer counting, and initializes the timer to its inactive state. The act of reset- ting the chip does not cause a timer interrupt. Note that the period register is not initialized on reset. The T0EN bit of the timerc register enables the clock to the timer. When T0EN is a 1, the timer counts down to- wards 0. When T0EN is a 0, the timer holds its current count. The PRESCALE field of the timerc register selects one of 16 possible clock rates for the timer input clock (see Table 35, timerc Register). Setting the DISABLE bit of the timerc register to a logic * Frequency of CKO/2 is equivalent to either CKI/2 for the PLL by- passed or related to CKI by the PLL multiplying factors. See Section 4.13, Clock Synthesis. 1 shuts down the timer and the prescaler for power sav- ings. Setting the TIMERDIS, bit 4, in the powerc regis- ter has the same effect of shutting down the timer. The DISABLE bit and the TIMERDIS bit are cleared by writ- ing a 0 to their respective registers to restore the normal operating mode.

4.11 Error Correction Coprocessor

The error correction coprocessor (ECCP) performs full Viterbi decoding with single instructions for a wide range of maximum likelihood sequence estimation (MLSE) equalization and convolutional decoding. The ECCP operates in parallel with the DSP core, increas- ing the throughput rate, and single-instruction Viterbi decoding provides significant code compression re- quired for a single DSP solution for modern digital cellu- lar applications. System Description The ECCP is a loosely coupled, programmable, internal coprocessor that operates in parallel with the DSP1600 core. A complete Viterbi decoding for MLSE equaliza- tion or convolutional decoding is performed with a single DSP instruction. The core communicates with the ECCP module via three interface registers. An address register, ear, is used to indirectly access the ECCP internal memory- mapped registers. A data register, edr, works in concert with the address register to indirectly read from or write to an ECCP internal memory-mapped register ad- dressed by the contents of the address register. After each edr access, the contents of the address register is postincremented by one. Upon writing an ECCP op code to instruction register, eir, either MLSE equaliza- tion, convolutional decoding, a simple traceback opera- tion, or ECCP reset is invoked. The mode of operation of the ECCP is set up by writing appropriate fields of a memory-mapped control register. In MLSE equalization, the control register may be con- figured for 2-tap to 6-tap equalization. In convolutional decoding, the control register may be configured for constraint lengths 2 through 7 and code rates 1/1 through 1/6. One of two variants of the soft-decoded output may be programmed, or a hard-decoded output may be chosen. Usually, convolutional decoding is performed after MLSE equalization. For receiver configuration with MLSE equalization followed by convolutional decoding, a Manhattan branch metric computation for convolu- tional decoding may be selected by setting a branch metric select bit in the control register.

branch metric select bit to zero. the traceback decode length. Figure 7. Error Correction Coprocessor Block through the address and data registers, ear and edr. RAM4, are not accessible to the user's DSP code. add-compare-select operation of the Viterbi algorithm. the channel occupies the lower byte.

state transitions, k = 0, 1, 2C – 1. ating polynomials G(5) and G(4) are stored in the upper and lower bytes of the G54 register, respectively. detection of a near overflow in the accumulated path cost, an internal vectored interrupt, EOVF, is provided. from the minimum cost index associated with the state with the minimum cost, min {Acc(j, p1), . . . , Acc(j, p2C – 1)}. sired end state into the minimum cost index register, MIDX. core to indicate when the ECCP is in operation. Traceback RAM: The fourth 1 Kword bank of dual-port RAM is shared between the DSP1600 core and the ECCP. Table 10. Incremental Branch Metrics

is explained with the operation flow diagram in Figure 7. Figure 8. DSP Core Operation Sequence

ECCP. The operation of the ECCP is captured in the signal flow diagram in Figure 8. Figure 9. ECCP Operation Sequence

ed for both the read and the write operation. Table 11. ECCP Instruction Encoding

0000 UpdateMLSE

0001 UpdateConv

0002 TraceBack

0003 Reserved

0004 ResetECCP

Table 12. Reset State of ECCP Registers

for control and status purposes and to hold data. A summary of the contents of these registers is given in Table 13. Table 13. Memory-Mapped Registers Bit 31:16 is addressed by even address. Bit 23:16 most significant byte of path cost. 0x0080—0x01FF Reserved Bit 15: 0 is addressed by odd address. Bit 15:0 lower 2 bytes of path cost. Bit 31:16 is addressed by even address. Bit 23:16 most significant byte of path cost. 0x0280—0x03FF Reserved Bit 15:0 is addressed by odd address. Bit 15:0 lower 2 bytes of path cost. Bit 0 is soft decision select. Bit 1 is Manhattan/Euclidean branch metric select. Bit 2 is soft/hard decision select. Bit 10:8 is code rate select. Bit 14:12 is constraint length select.

Table 13. Memory-Mapped Registers (continued) Bit 9:0 is in-phase part of received signal. Bit 9:0 is quadrature-phase part of received signal. Bit 7:0 is upper byte of the minimum accumulated cost 0x040F. Bit 15:0 is the lower 2 bytes of the minimum accumulated cost. 0x411—0x7FF Reserved Registers Reserved.

4.12 JTAG Test Port

marized in Table 14. Cell 0 is the LSB (closest to TDO). shifted out during SHIFT-IR controller states. Table 14. JTAG Instruction Register

Table 15. JTAG Boundary-Scan Register

• Please refer to Pin Multiplexing in Section 4.1 for a description of pin multiplexing of BIO, PHIF, VEC[3:0], and SIO2.

† Note that shifting a zero into this cell in the mode to scan a zero into the chip will disable the processor clocks just as the STOP pin will. ‡ When the JTAG SAMPLE instruction is used, this cell will have a logic one regardless of the state of the pin. Note: The direction of shifting is from TDI to cell 104 to cell 103 . . . to cell 0 of TDO.

0 OE Controls cells 1, 27—31 69 B OCK2/PCSN *

1 O CKO 70 DC Controls cell 71

2 I RSTB 71 B DO2/PSTAT *

3 DC Controls cell 4 72 DC Controls cell 73

4 B TRAP 73 B SYNC2/PBSEL *

6 O IACK 75 B ILD2/PIDS*

7 I INT0 76 DC Controls cell 77

8 OE Controls cells 6, 10—25, 49, 50, 78, 79 77 B OLD2/PODS *

9 I INT1 78 O IBF2/PIBF*

26 I EXM 80 DC Controls cell 81

27 O RWN 81 B ICK2/PB0*

37 DC Controls cells 32—36, 38—48 84 DC Controls cell 85

49 O OBE1 86 DC Controls cell 87

50 O IBF1 87 B SADD2/PB3 *

51 I DI1 88 DC Controls cell 89

52 DC Controls cell 53 89 B IOBIT0/PB4*

53 B ILD1 90 DC Controls cell 91

54 DC Controls cell 55 91 B IOBIT1/PB5*

55 B ICK1 92 DC Controls cell 93

56 DC Controls cell 57 93 B IOBIT2/PB6*

57 B OCK1 94 DC Controls cell 95

58 DC Controls cell 59 95 B IOBIT3/PB7*

59 B OLD1 96 DC Controls cell 97

60 OE Controls cell 61 97 B VEC3/IOBIT4*

61 O DO1 98 DC Controls cell 99

62 DC Controls cell 63 99 B VEC2/IOBIT5*

63 B SYNC1 100 DC Controls cell 101

64 DC Controls cell 65 101 B VEC1/IOBIT6*

65 B SADD1 102 DC Controls cell 103

66 DC Controls cell 67 103 B VEC0/IOBIT7*

67 B DOEN1 104 I CKI‡

68 DC Controls cell 69 — — —

4.13 Clock Synthesis

Figure 10. Clock Source Block Diagram programmable clock options: CMOS, or small-signal. The PLL cannot operate without an external input clock. is written, the LOCK flag is reset.

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 37 The frequency of the PLL output clock, fVCO , is deter- mined by the values loaded into the 3-bit N divider and the 5-bit M divider. When the PLL is selected and locked, the frequency of the internal processor clock is related to the frequency of CKI by the following equa- tions: f VCO = fCKI * M/N fINTERNAL CLOCK = fCKO = fVCO ÷ 2 The frequency of the VCO, fVCO , must fall within the range listed in Table 63. Also note that fVCO must be at least twice fCKI. The coding of the Mbits and Nbits is described as fol- lows: Mbits = M − 2 if (N = 1) Nbits = 0x7 else Nbits = N − 2 where N ranges from 1 to 8 and M ranges from 2 to 20. The loop filter bits LF[3:0] should be programmed ac- cording to Table 64. Two other bits in the pllc register control the PLL. Clear- ing the PLLEN bit powers down the PLL; setting this bit powers up the PLL. Clearing the PLLSEL bit deselects the PLL so that the DSP is clocked by a 1X version of the CKI input; setting the PLLSEL bit selects the PLL- generated clock for the source of the DSP internal pro- cessor clock. The pllc register is cleared on reset and powerup. Therefore, the DSP comes out of reset with the PLL deselected and powered down. M and N should be changed only while the PLL is deselected. The val- ues of M and N should not be changed when powering down or deselecting the PLL. As previously mentioned, the PLL also provides a user flag, LOCK, to indicate when the loop has locked. When this flag is not asserted, the PLL output is unstable. The DSP should not be switched to the PLL-based clock without first checking that the lock flag is set. The lock flag is cleared by writing to the pllc register. When the PLL is deselected, it is necessary to wait for the PLL to relock before the DSP can be switched to the PLL- based clock. Before the input clock is stopped, the PLL should be powered down. Otherwise, the LOCK flag will not be reset and there may be no way to determine if the PLL is stable, once the input clock is applied again. The lock-in time depends on the frequency of operation and the values programmed for M and N (see Table 64).

The device would come out of reset with the PLL disabled and deselected. the DSP, and thus, this clock should not be used as an input to jitter-sensitive devices in the system. Table 16. Latency Times for Switching Between CKI and PLL-Based Clocks

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 39

4.14 Power Management

There are three different control mechanisms for putting the DSP1628 into low-power modes: the powerc con- trol register, the STOP pin, and the AWAIT bit in the alf register. The PLL can also be disabled with the PLLEN bit of the pllc register for more power saving. Powerc Control Register Bits The powerc register has 10 bits that power down vari- ous portions of the chip and select the clock source: XTLOFF: Assertion of the XTLOFF bit powers down the small-signal input circuit, disabling the internal proces- sor clock. Since the small-signal input circuit takes many cycles to stabilize, care must be taken with the turn-on sequence, as described later. SLOWCKI: Assertion of the SLOWCKI bit selects the ring oscillator as the clock source for the internal pro- cessor clock instead of CKI or the PLL. When CKI or the PLL is selected, the ring oscillator is powered down. Switching of the clocks is synchronized so that no par- tial or short clock pulses occur. Two nop s should follow the instruction that sets or clears SLOWCKI. NOCK: Assertion of the NOCK bit synchronously turns off the internal processor clock, regardless of whether its source is provided by CKI, the PLL, or the ring oscil- lator. The NOCK bit can be cleared by resetting the chip with the RSTB pin, or asserting the INT0 or INT1 pins. Two nop s should follow the instruction that sets NOCK. The PLL remains running, if enabled, while NOCK is set. INT0EN: This bit allows the INT0 pin to asynchronously clear the NOCK bit, thereby allowing the device to con- tinue program execution from where it left off without any loss of state. No chip reset is required. It is recom- mended that, when INT0EN is to be used, the INT0 interrupt be disabled in the inc register so that an unin- tended interrupt does not occur. After the program re- sumes, the INT0 interrupt in the ins register should be cleared. INT1EN: This bit enables the INT1 pin to be used as the NOCK clear, exactly like INT0EN previously described. The following control bits power down the peripheral I/O units of the DSP. These bits can be used to further reduce the power consumption during standard sleep mode. SIO1DIS: This is a powerdown signal to the SIO1 I/O unit. It disables the clock input to the unit, thus elimi- nating any sleep power associated with the SIO1. Since the gating of the clocks may result in incomplete transactions, it is recommended that this option be used in applications where the SIO1 is not used or when reset may be used to reenable the SIO1 unit. Otherwise, the first transaction after reenabling the unit may be corrupted. SIO2DIS: This bit powers down the SIO2 in the same way SIO1DIS powers down the SIO1. PHIFDIS: This is a powerdown signal to the parallel host interface. It disables the clock input to the unit, thus eliminating any sleep power associated with the PHIF. Since the gating of the clocks may result in in- complete transactions, it is recommended that this op- tion be used in applications where the PHIF is not used, or when reset may be used to reenable the PHIF. Otherwise, the first transaction after reenabling the unit may be corrupted. TIMERDIS: This is a timer disable signal which dis- ables the clock input to the timer unit. Its function is identical to the DISABLE field of the timerc control register. Writing a 0 to the TIMERDIS field will continue the timer operation. Figure 11 shows a functional view of the effect of the bits of the powerc register on the clock circuitry. It shows only the high-level operation of each bit. Not shown are the bits that power down the peripheral units. STOP Pin Assertion (active-low) of the STOP pin has the same effect as setting the NOCK bit in the powerc register. The internal processor clock is synchronously disabled until the STOP pin is returned high. Once the STOP pin is returned high, program execution will continue from where it left off without any loss of state. No chip reset is required. The PLL remains running, if enabled, during STOP assertion. The pllc Register Bits The PLLEN bit of the pllc register can be used to pow- er down the clock synthesizer circuitry. Before shutting down the clock synthesizer circuitry, the system clock should be switched to either CKI using the PLLSEL bit of pllc, or to the ring oscillator using the SLOWCKI bit of powerc .

Deep sleep is the state arrived at either by a hardware or software stop of the internal processor clock. The switching of the multiplexers and the synchronous gate is designed so that no partial clocks or glitching will occur. PLL select is the PLLSEL bit of pllc; PLL powerdown is the PLLEN bit of pllc. Figure 11. Power Management Using the powerc and the pllc Registers

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 41 Await Bit of the alf Register Setting the AWAIT bit of the alf register causes the processor to go into the standard sleep state or power-saving standby mode. Operation of the AWAIT bit is the same as in the DSP1610, DSP1611, DSP1616, DSP1617, and DSP1618. In this mode, the minimum circuitry required to process an incoming interrupt remains active, and the PLL remains active if enabled. An interrupt will return the processor to the previous state, and program execution will continue. The action resulting from setting the AWAIT bit and the action resulting from setting bits in the powerc register are mostly independent. As long as the processor is receiving a clock, whether slow or fast, the DSP may be put into standard sleep mode with the AWAIT bit. Once the AWAIT bit is set, the STOP pin can be used to stop and later restart the processor clock, returning to the standard sleep state. If the processor clock is not running, how- ever, the AWAIT bit cannot be set. Power Management Sequencing There are important considerations for sequencing the power management modes. The small-signal clock input circuit has a start-up delay which must be taken into account, and the PLL requires a delay to reach lock-in. Also, the chip may or may not need to be reset following a return from a low-power state. Devices with a small-signal input clocking option may use the XTLOFF bit in the powerc register to power down the on-chip oscillator or small-signal circuitry, thereby reducing the power dissipation. When reenabling the oscillator or the small-signal circuitry, it is important to bear in mind that a start-up interval exists during which time the clocks are not stable. Two scenarios exist here: 1. Immediate Turn-Off, Turn-On with RSTB: This scenario applies to situations where the target device is not re- quired to execute any code while the small-signal input circuit is powered down and where restart from a reset state can be tolerated. In this case, the processor clock derived from either the oscillator or the small-signal input is running when XTLOFF is asserted. This effectively stops the internal processor clock. When the system choos- es to reenable the oscillator or small-signal input, a reset of the device will be required. The reset pulse must be of sufficient duration for the small-signal start-up interval to be satisfied (required for the small-signal input circuit to reach its dc operating point). A minimum reset pulse of 20 µs will be adequate. The falling edge of the reset signal, RSTB, will asynchronously clear the XTLOFF field, thus reenabling the power to the small-signal circuitry. The target DSP will then start execution from a reset state, following the rising edge of RSTB. 2. Running from Slow Clock While XTLOFF Active: The second scenario applies to situations where the device needs to continue execution of its target code. In this case, the device switches to the slow ring oscillator clock first, by enabling the SLOWCKI field. Then, if the small-signal input is being used, power down this circuitry by writing a 1 to the XTLOFF field. Two nop s are needed in between the two write operations to the powerc register. The target device will then continue execution of its code at slow speed, while the small-signal input clock is turned off. Switching from the slow clock back to the high-speed clock is then accomplished in three user steps. First, XTLOFF is cleared. Then, a user-programmed routine sets the internal timer to a delay to wait for the small- signal input oscillations to become stable. When the timer counts down to zero, the high-speed clock is selected by clearing the SLOWCKI field, either in the timer's interrupt service routine or following a timer polling loop. If PLL operation is desired, then an additional routine is necessary to enable the PLL and wait for it to lock.

DSP1628 Digital Signal Processor February 1997 42 Lucent Technologies Inc. Power Management Examples Without the PLL The following examples show the more significant options for reducing the power dissipation. These are valid only if the pllc register is set to disable and deselect the PLL (PLLEN = 0, PLLSEL = 0). Standard Sleep Mode. This is the standard sleep mode. While the processor is clocked with a high-speed clock, CKI, the alf register's AWAIT bit is set. Peripheral units may be turned off to further reduce the sleep power. powerc = 0X00F0 /* Turn off peripherals, core running with CKI */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Only sleep power */ nop /* consumed here until.... interrupt wakes up the device */ cont: . . . /* User code executes here */ powerc = 0x0 /* Turn peripheral units back on */ Sleep with Slow Internal Clock. In this case, the ring oscillator is selected to clock the processor before the device is put to sleep. This will reduce the power dissipation while waiting for an interrupt to continue program execution. powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for it to take effect */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Reduced sleep power */ nop /* consumed here.... Interrupt wakes up the device */ cont: . . . /* User code executes here */ powerc = 0x00F0 /* Select high-speed clock */ 2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripheral units back on */ Note that, in this case, the wake-up latency is determined by the period of the ring oscillator clock. Sleep with Slow Internal Clock and Small-Signal Disabled. If the target device contains the small-signal clock option, the clock input circuitry can be powered down to further reduce power. In this case, the slow clock must be selected first. powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for it to take effect */ powerc = 0xC0F0 /* Turn off the small-signal input buffer */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Reduced sleep power */ nop /* consumed here.... Interrupt wakes up the device */ powerc = 0x40F0 /* Clear XTLOFF, reenable small-signal */ call xtlwait /* Wait until small-signal is stable */ cont:powerc = 0x00F0 /* Select high-speed clock */ 2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripheral units back on */ Note that, in this case, the wake-up latency is dominated by the small-signal start-up period.

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 43 Software Stop. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to reenable the clocks. The power management must be done in correct sequence. powerc = 0x4000 /* SLOWCKI asserted */ 2*nop /* Wait for it to take effect */ powerc = 0xD000 /* XTLOFF asserted if applicable and INT0EN asserted */ inc = NOINT0 /* Disable the INT0 interrupt */ sopor:powerc = 0xF000 /* NOCK asserted, all clocks stop */ /* Minimum switching power consumed here */ 3*nop /* Some nops will be needed */ /* INT0 pin clears the NOCK field, clocking resumes */ cont:powerc = 0x4000 /* INT0EN cleared and XTLOFF cleared, if applicable*/ call waitxtl /* Wait for the small-signal to */ /* stabilize, if applicable*/ powerc = 0x0 /* Clear SLOWCKI field, back to high speed */ 2*nop /* Wait for it to take effect */ ins = 0x0010 /* Clear the INT0 status bit */ In this case also, the wake-up latency is dominated by the small-signal start-up period. The previous examples do not provide an exhaustive list of options available to the user. Many different clocking possibilities exist for which the target device may be programmed, depending on: n The clock source to the processor. n Whether the user chooses to power down the peripheral units. n The operational state of the small-signal clock input, powered or unpowered. n Whether the internal processor clock is disabled through hardware or software. n The combination of power management modes the user chooses. n Whether or not the PLL is enabled. An example subroutine for xtlwait follows: xtlwait: timer0 = 0x2710 /* Load a count of 10,000 into the timer */ timerc = 0x0010 /* Start the timer with a PRESCALE of two */ inc = 0x0000 /* Disable the interrupts */ loop1: a0 = ins /* Poll the ins register */ a0 = a0 & 0x0100 /* Check bit 8 (TIME) of the ins register */ if eq goto loop1 /* Loop if the bit is not set */ ins = 0x0100 /* Clear the TIME interrupt bit */ return /* Return to the main program */

DSP1628 Digital Signal Processor February 1997 44 Lucent Technologies Inc. Power Management Examples with the PLL The following examples show the more significant options for reducing power dissipation if operation with the PLL clock synthesizer is desired. Standard Sleep Mode, PLL Running. This mode would be entered in the same manner as without the PLL. While the input to the clock synthesizer, CKI, remains running, the alf register's AWAIT bit is set. The PLL will continue to run and dissipate power. Peripheral units may be turned off to further reduce the sleep power. powerc = 0x00F0 /* Turn off peripherals, core running with PLL */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Only sleep power plus PLL */ nop /* power consumed here.... Interrupt wakes up the device */ cont: . . . /* User code executes here */ powerc = 0x0 /* Turn peripheral units back on */ Sleep with Slow Internal Clock, PLL Running. In this case, the ring oscillator is selected to clock the processor before the device is put to sleep. This will reduce power dissipation while waiting for an interrupt to continue program execution. powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for slow clock to take effect */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Reduced sleep power, PLL */ nop /* power, and ring oscillator power consumed here... */ /* Interrupt wakes up the device */ cont: . . . /* User code executes here */ powerc = 0x00F0 /* Select high-speed PLL based clock */ 2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripheral units back on */

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 45 Sleep with Slow Internal Clock and Small-Signal Disabled, PLL Disabled. If the target device contains the small- signal clock option, the clock input circuitry can be powered down to further reduce power. In this case, the slow clock must be selected first, and then the PLL must be disabled, since the PLL cannot run without the clock input circuitry being active. powerc = 0x40F0 /* Turn off peripherals and select slow clock */ 2*nop /* Wait for slow clock to take effect */ pllc = 0x29F2 /* Disable PLL (assume N = 1,M = 20, LF = 1001) */ powerc = 0xC0F0 /* Disable small-signal input buffer */ sleep:a0 = 0x8000 /* Set alf register in cache loop if running from */ do 1 { /* external memory with >1 wait state */ alf = a0 /* Stop internal processor clock, interrupt circuits */ nop /* active */ nop /* Needed for bedtime execution. Reduced sleep power nop /* consumed here.... Interrupt wakes up device */ powerc = 0x40F0 /* Clear XTLOFF, leave PLL disabled */ call xtlwait /* Wait until small-signal is stable */ pllc = 0xE9F2 /* Enable PLL, continue to run off slow clock */ call pllwait /* Loop to check for LOCK flag assertion */ cont:powerc = 0x00F0 /* Select high-speed PLL based clock */ 2*nop /* Wait for it to take effect */ powerc = 0x0000 /* Turn peripherals back on */ Software Stop, PLL Disabled. In this case, all internal clocking is disabled. INT0, INT1, or RSTB may be used to reenable the clocks. The power management must be done in the correct sequence, with the PLL being disabled before shutting down the clock input buffer. powerc = 0x4000 /* SLOWCKI asserted */ 2*nop /* Wait for slow clock to take effect */ pllc = 0x29F2 /* Disable PLL (assume N = 1, M = 20, LF = 1001) */ powerc = 0xD000 /* XTLOFF asserted, if applicable and INT0EN /* asserted */ sopor:powerc = 0xF000 /* NOCK asserted, all clocks stop */ /* Minimum switching power consumed here */ 3*nop /* Some nops will be needed */ /* INT0 pin clears NOCK field, clocking resumes */ cont: powerc = 0x4000 /* INTOEN cleared and XTLOFF cleared, if applicable */ call xtlwait /* Wait until small-signal is stable */ /* if applicable */ pllc = 0xE9F2 /* Enable PLL, continue to run off slow clock */ call pllwait /* Loop to check for LOCK flag assertion */ powerc = 0x0 /* Select high-speed PLL based clock */ 2*nop /* Wait for it to take effect */ ins = 0x0010 /* Clear the INT0 status bit */

DSP1628 Digital Signal Processor February 1997 46 Lucent Technologies Inc.

5 Software Architecture

5.1 Instruction Set

The DSP1628 processor has seven types of instruc- tions: multiply/ALU, special function, control, F3 ALU, BMU, cache, and data move. The multiply/ALU instruc- tions are the primary instructions used to implement sig- nal processing algorithms. Statements from this group can be combined to generate multiply/accumulate, log- ical, and other ALU functions and to transfer data be- tween memory and registers in the data arithmetic unit. The special function instructions can be conditionally executed based on flags from the previous ALU or BMU operation, the condition of one of the counters, or the value of a pseudorandom bit in the DSP1628 device. Special function instructions perform shift, round, and complement functions. The F3 ALU instructions enrich the operations available on accumulators. The BMU in- structions provide high-performance bit manipulation. The control instructions implement the goto and call commands. Control instructions can also be executed conditionally. Cache instructions are used to implement low-overhead loops, conserve program memory, and decrease the execution time of certain multiply/ALU in- structions. Data move instructions are used to transfer data between memory and registers or between accu- mulators and registers. See the DSP1611/17/18/27 Digital Signal Processor Information Manual for a de- tailed description of the instruction set. The following operators are used in describing the in- struction set: * 16 x 16-bit –> 32-bit multiplication or register-in- direct addressing when used as a prefix to an ad- dress register or denotes direct addressing when used as a prefix to an immediate + 36-bit addition – 36-bit subtraction† >> Arithmetic right shift >>> Logical right shift << Arithmetic left shift <<< Logical left shift | 36-bit bitwise OR & 36-bit bitwise AND† ^ 36-bit bitwise EXCLUSIVE OR† : Compound address swapping, accumulator shuffling ~ One's complement † These are 36-bit operations. One operand is 36-bit data in an accu- mulator; the other operand may be 16, 32, or 36 bits. Object Code Compatibility The DSP1628 is object code compatible with the DSP1618 with the following exceptions: n ECCP user flag, EBUSY, which indicates error correction coprocessor activity, has changed its condition field. The EBUSY flag is used in conjunction with the if CON F2 or if CON goto/call/return instructions to monitor the ECCP operation. The object code corresponding to ifc EBUSY, for example, must be modified to reflect the change in condition codes. Alternately, the source code can be assembled using DSP1628 development tools. n The SIO and SIO2 interrupts (IBF , IBF2, OBE, and OBE2) are cleared one instruction cycle AFTER reading or writing the serial data registers, (sdx[in], sdx2[in], sdx[out], or sdx2[out]). To account for this added latency, the user must ensure that a single instruction (NOP or any other valid DSP16XX instruction) follows the sdx register read or write instruction prior to exiting an interrupt service routine (via an ireturn or goto pi instruction) or before check- ing the ins register for the SIO flag status. Adding this instruction ensures that interrupts are not reported incorrectly following an ireturn or that stale flags are not read from the ins register. Refer to TECHNICAL ADVISORY #23. Multiply/ALU Instructions Note that the function statements and transfer state- ments in Table 17 are chosen independently. Any func- tion statement (F1) can be combined with any transfer statement to form a valid multiply/ALU instruction. If ei- ther statement is not required, a single statement from either column also constitutes a valid instruction. The number of cycles to execute the instruction is a function of the transfer column. (An instruction with no transfer statement executes in one instruction cycle.) Whenever PC, pt, or rM is used in the instruction and points to ex- ternal memory, the programmed number of wait-states must be added to the instruction cycle count. All multi- ply/ALU instructions require one word of program mem- ory. The no-operation (nop ) instruction is a special case encoding of a multiply/ALU instruction and executes in one cycle. The assembly-language representation of a nop is either nop or a single semicolon. Condition CON DSP1618 DSP1628 11100 ebusy lock 11101 reserved ebusy

5 Software Architecture (continued)

X space fetch occurs (even though its value is not used). † The l in [ ] is an optional argument that specifies the low 16 bits of aT or y.

1. When an external memory access is made in X or Y space and wait-states are programmed, add the number of wait-states.
2. If an X space access and a Y space access are made to the same bank of DPRAM in one instruction, add one cycle.

register is zero. auc is cleared by reset. Table 17. Multiply/ALU Instructions Table 18. Replacement Table for Multiply/ALU Instructions aD, aS, aT a0, a1 One of two DAU accumulators. 0, +1, –1, or j, respectively. Z *rMzp, *rMpz, *rMm2, *rMjk Read/Write compound addressing. rM (M = 0, 1, 2, 3) is used twice. modified by +1, 0, +2, or k, respectively.

The above special function statements can be executed unconditionally by writing them directly, e.g., a0 = a1. † This function is not available for the DSP16A. Table 19. Replacement Table for Special Function Instructions a0, a1 One of two DAU accumulators. See Table 21 for definitions of mnemonics.

‡ The icall instruction is reserved for development system use. Table 20. Replacement Table for Control Instructions See Table 21 for definitions of mnemonics. within the same 4 Kwords memory section.

Table 21 lists mnemonics used in conditional execution of special function and control instructions.

• Result is not representable in the 36-bit accumulators (36-bit overflow).

† Bits 35—31 are not the same (32-bit overflow). Testing the state of the counters (c0 or c1) automatically increments the counter by one. Table 21. DSP1628 Conditional Mnemonics lvs Logical overflow set.* lvc Logical overflow clear. mvs Mathematical overflow set.† mvc Mathematical overflow clear. c0ge Counter 0 greater than or equal to 0. c0lt Counter 0 less than 0. c1ge Counter 1 greater than or equal to 0. c1lt Counter 1 less than 0. heads Pseudorandom sequence bit set. tails Pseudorandom sequence bit clear. oddp Odd Parity, from BMU operation. evenp Even Parity, from BMU operation. mns1 Minus 1, result of BMU operation. nmns1 Not Minus 1, result of BMU operation.

by programming two consecutive 16-bit immediate operations. The F3 ALU instructions are shown in Table 22. Table 22. F3 ALU Instructions operations, i.e., bit test operations. † If PC points to external memory, add programmed wait-states. ‡ The h and l are required notation in these instructions. 27 Digital Signal Processor Information Manual for further discussion of the BMU instructions.

aD = aS >> IM16 Arithmetic right shift by immediate (36-bit, sign filled in); 2-cycle, 2-word. aD = aS >> arM Arithmetic right shift by arM (36-bit, sign filled in); 1-cycle. aD = aS >> aS Arithmetic right shift by aS (36-bit, sign filled in); 2-cycle. aD = aS >>> IM16 Logical right shift by immediate (32-bit shift, 0s filled in); 2-cycle, 2-word. aD = aS >>> arM Logical right shift by arM (32-bit shift, 0s filled in); 1-cycle. aD = aS >>> aS Logical right shift by aS (32-bit shift, 0s filled in); 2-cycle. aD = aS << IM16 Arithmetic left shift† by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word. aD = aS << arM Arithmetic left shift† by arM (36-bit shift, 0s filled in); 1-cycle. aD = aS << aS Arithmetic left shift† by aS (36-bit shift, 0s filled in); 2-cycle. aD = aS <<< IM16 Logical left shift by immediate (36-bit shift, 0s filled in); 2-cycle, 2-word. aD = aS <<< arM Logical left shift by arM (36-bit shift, 0s filled in); 1-cycle. aD = aS <<< aS Logical left shift by aS (36-bit shift, 0s filled in); 2-cycle. † Not the same as the special function arithmetic left shift. Here, the guard bits in the destination accumulator are shifted into, not sign-extended. aD = exp(aS) Detect the number of redundant sign bits in accumulator; 1-cycle. aD = norm(aS, arM) Normalize aS with respect to bit 31, with exponent in arM; 1-cycle. aD = extracts(aS, IM16) Extraction with sign extension, field specified as immediate; 2-cycle, 2-word. aD = extracts(aS, arM) Extraction with sign extension, field specified in arM; 1-cycle. aD = extractz(aS, IM16) Extraction with zero extension, field specified as immediate; 2-cycle, 2-word. aD = extractz(aS, arM) Extraction with zero extension, field specified in arM; 1-cycle. aD = insert(aS, IM16) Bit field insertion, field specified as immediate; 2-cycle, 2-word. aD = insert(aS, arM) Bit field insertion, field specified in arM; 2-cycle. byte of the operand (immediate or arM), and the offset from the LSB is in the lower byte. aD = aS:aa0 Shuffle accumulators with alternate accumulator 0 (aa0); 1-cycle. aD = aS:aa1 Shuffle accumulators with alternate accumulator 1 (aa1); 1-cycle. Note: The alternate accumulator gets what was in aS. aD gets what was in the alternate accumulator. Table 23. Replacement Table for F3 ALU Instructions and F4 BMU Instructions aD, aT, aS a0 or a1 One of the two accumulators. IM16 immediate 16-bit data, sign-, zero-, or one-extended as appropriate. arM ar<0—3> One of the auxiliary BMU registers.

register. K is encoded as 0 in the instruction encoding to select cloop.

1. In the first pass, the instructions are fetched from program memory and the cycle times are the normal out-of-

cache values, except for the last instruction in the block of N instructions. This instruction executes in two cycles.

1. During pass two through pass K – 1, each instruction is fetched from cache and the in-cache timings apply.
2. During the last (Kth) pass, the block of instructions is fetched from cache and the in-cache timings apply, except

that the timing of the last instruction is the same as if it were out-of-cache.

1. If any of the instructions access external memory, programmed wait-states must be added to the cycle counts.

The redo instruction treats the instructions currently in the cache memory as another loop to be executed K times. Using the redo instruction, instructions are reexecuted from the cache without reloading the cache. value of cloop is decremented to 0; hence, cloop needs to be written before each do cloop or redo cloop. Table 24. Replacement Table for Cache Instructions 1 to 127 Number of times the instructions to be executed is encoded in the instruction. N 1 to 15 1 to 15 instructions can be included.

sioc, sioc2, tdms , tdms2 , srta, and srta2 registers are not readable. than 16 bits wide are read, their contents are zero-extended to 16 bits. Loading an accumulator with a data move instruction does not affect the flags. Table 25. Replacement Table for Data Move Instructions pt, pr, psw Subset of registers accessible with direct addressing. aS, aT a0, a1 High half of accumulator. Y *rM, *rM++, *rM--, *rM++j Same as in multiply/ALU instructions. Z *rMzp, *rMpz, *rMm2, *rMjk Same as in multiply/ALU instructions. IM16 16-bit value Long immediate data. IM9 9-bit value Short immediate data for YAAU registers. SR r<0—3>, rb, re, j, k Subset of registers for short immediate.

5.2 Register Settings

Table 26. Serial I/O Control Registers † See tdms register, SYNC field. ‡ The bit definitions of the sioc2 register are identical to the sioc register bit definitions. DO changes on the rising edge of OCK. time on DO by half a cycle of OCK. In active mode, ILD1 and/or OLD1 = ICK1/16, active SYNC1 = ICK1/[128/256†]. In active mode, ILD1 and/or OLD1 = OCK1/16, active SYNC1 = OCK1/[128/256†]. OLD1 is an input (passive mode). OLD1 is an output (active mode). ILD1 is an input (passive mode). ILD1 is an output (active mode). OCK1 is an input (passive mode). OCK1 is an output (active mode). ICK1 is an input (passive mode). ICK1 is an output (active mode).

Table 27. Time-Division Multiplex Slot Registers † See sioc register, LD field. ‡ Select this mode when in multiprocessor mode. § The tdms2 register bit definitions are identical to the tdms register bit definitions.

1 Multiprocessor mode on; DOEN1 is an output (active

TRANSMIT SLOT 1xxxxxx Transmit slot 7. SYNC 1 Transmit slot 0, SYNC1 is an output (active mode). 0 SYNC1 is an input (passive mode).

Table 28. Serial Receive/Transmit Address Registers † The srta2 field definitions are identical to the srta register field definitions. Table 29. Multiprocessor Protocol Registers ‡ The saddx2 field definitions are identical to the saddx register field definitions. RECEIVE ADDRESS 1xxxxxxx Receive address 7. TRANSMIT ADDRESS 1xxxxxxx Transmit address 7. x1xxxxxx Transmit address 6. xx1xxxxx Transmit address 5. xxx1xxxx Transmit address 4. xxxx1xxx Transmit address 3. xxxxx1xx Transmit address 2. xxxxxx1x Transmit address 1. xxxxxxx1 Transmit address 0.

• The DAU flags can be set by either BMU or DAU operations.

compatible with future chip versions. The auc register is cleared at reset. Table 30. Processor Status Word (psw) Register DAU FLAGS* Wxxx LMI—logical minus when set (bit 35 = 1). xWxx LEQ—logical equal when set (bit [35:0] = 0). xxWx LLV—logical overflow when set. xxxW LMV—mathematical overflow when set. a1[V] W Accumulator 1 ( a1) overflow when set. a1[35:32] Wxxx Accumulator 1 ( a1) bit 35. xWxx Accumulator 1 ( a1) bit 34. xxWx Accumulator 1 ( a1) bit 33. xxxW Accumulator 1 ( a1) bit 32. a0[V] W Accumulator 0 ( a0) overflow when set. a0[35:32] Wxxx Accumulator 0 ( a0) bit 35. xWxx Accumulator 0 ( a0) bit 34. xxWx Accumulator 0 ( a0) bit 33. xxxW Accumulator 0 ( a0) bit 32. Table 31. Arithmetic Unit Control (auc) Register pi register only outside an interrupt service routine. PSG never reset by writing the pi register. load the x register, allowing single-cycle squaring with p = x * y. CLR 1xx Clearing yl is disabled (enabled when 0). x1x Clearing a1l is disabled (enabled when 0). xx1 Clearing a0l is disabled (enabled when 0). SAT 1x a1 saturation on overflow is disabled (enabled when 0). x1 a0 saturation on overflow is disabled (enabled when 0). 10 a0, a1 ← p x 4 (and zeros written to the two LSBs). 11 a0, a1 ← p x 2 (and zero written to the LSB).

• JINT is a JTAG interrupt and is controlled by the HDS. It may be made unmaskable by the Lucent Technologies development system tools.

Encoding: A 0 disables an interrupt; a 1 enables an interrupt. viced. If a 1 is written to bits 4, 5, 8, 12, or 13 of ins, the corresponding interrupt is cleared. Table 32. Parallel Host Interface Control (phifc) Register Intel protocol: PIDS and PODS data strobes. Motorola protocol: PRWN and PDS data strobes. When PSTROBE = 1, PODS pin (PDS) active-low. When PSTROBE = 1, PODS pin (PDS) active-high. In either mode, PBSEL pin = 0 -> pdx0 low byte. See Table 7. If PMODE = 0, PBSEL pin = 1 -> pdx0 low byte. If PMODE = 1, PBSEL pin = 0 -> pdx0 high byte. PIBF and POBE pins active-high. PIBF and POBE pins active-low. changed (output buffer empty). POBE flag as read through PSTAT register is active-low. Table 33. Interrupt Control (inc) Register Table 34. Interrupt Status (ins) Register

Table 35. timerc Register Timer stops after counting down to 0. Timer automatically reloads and repeats indefinitely.

0000 CKO/2 1000 CKO/512

0001 CKO/4 1001 CKO/1024

0010 CKO/8 1010 CKO/2048

0011 CKO/16 1011 CKO/4096

0100 CKO/32 1100 CKO/8192

0101 CKO/64 1101 CKO/16384

0110 CKO/128 1110 CKO/32768

0111 CKO/256 1111 CKO/65536

Table 36. Phase-Locked Loop Control (pllc) Register DSP internal clock taken directly from CKI. DSP internal clock taken from PLL. ICP — Charge pump current selection (see Table 64 for proper value). LF[3:0] — Loop filter setting (see Table 64 for proper value). INTERNAL CLOCK = fCKI x (M/(2N)).

Table 37. sbit Register DIREC 1xxxxxxx IOBIT7 is an output (input when 0). x1xxxxxx IOBIT6 is an output (input when 0). xx1xxxxx IOBIT5 is an output (input when 0). xxx1xxxx IOBIT4 is an output (input when 0). xxxx1xxx IOBIT3 is an output (input when 0). xxxxx1xx IOBIT2 is an output (input when 0). xxxxxx1x IOBIT1 is an output (input when 0). xxxxxxx1 IOBIT0 is an output (input when 0). VALUE Rxxxxxxx Reads the current value of IOBIT7. xRxxxxxx Reads the current value of IOBIT6. xxRxxxxx Reads the current value of IOBIT5. xxxRxxxx Reads the current value of IOBIT4. xxxxRxxx Reads the current value of IOBIT3. xxxxxRxx Reads the current value of IOBIT2. xxxxxxRx Reads the current value of IOBIT1. xxxxxxxR Reads the current value of IOBIT0. Table 38. cbit Register

external memory). Otherwise, the mwait register is initialized to all 0s (0 wait-states) upon reset.

• The ebusy flag cannot be written by the user.

Table 39. alf Register Power-saving standby mode or standard sleep enabled. The internal DPRAM is addressed beginning at 0x0000 in X space. The internal DPRAM is addressed beginning at 0xc000 in X space. Table 40. mwait Register Table 41. DSP1628 32-Bit JTAG ID Register Small-signal input clock option. CMOS level input clock option.

• The field definitions for the ioc register are different from the DSP1610.

1. The phase of CKI is synchronized by the rising edge of RSTB.
2. When SLOWCKI is enabled in the powerc register, these options reflect the low-speed internal ring oscillator.
3. The wait-stated clock reflects the internal instruction cycle and may be stretched based on the mwait register setting (see Table 40).

During sequenced external memory accesses, it completes one cycle.

1. The sequenced wait-stated clock completes two cycles during a sequenced external memory access and may be stretched based

on the mwait register setting (see Table 40). Table 42. ioc Register* EXTROM If 1, sets AB15 low during external memory accesses when WEROM = 1. CKO2 CKO configuration (see below). EBIOH If 1, enables high half of BIO, IOBIT[4:7], and disables VEC[3:0] from pins. WEROM If 1, allows writing into external program (X) memory. ESIO2 If 1, enables SIO2 and low half of BIO, and disables PHIF from pins. SIOLBC If 1, DO1 and DO2 looped back to DI1 and DI2. CKO[1:0] CKO configuration (see below). 0 0 0 CKI CKI x M/(2N) Free-running clock. 1 0 0 CKI CKI Output of CKI buffer. 1 0 1 CKI/(1 + W) CKI x (M/(2N)) / [1 + W] Sequenced, wait-stated clock.

Table 43. powerc Register Note: The reserved (rsrvd) bits should always be written with zeros to make the program compatible with future chip versions. The powerc register configures various power management modes. XTLOFF 1 = power down small-signal clock input. SLOWCKI 1 = select ring oscillator clock (internal slow clock). NOCK 1 = disable internal processor clock. INT0EN 1 = INT0 clears NOCK field. INT1EN 1 = INT1 clears NOCK field.

Table 44. Register Settings After Reset † If EXM is high and INT1 is low when RSTB goes high, mwait will contain all ones instead of all zeros.

DSP1628 Digital Signal Processor February 1997 66 Lucent Technologies Inc.

5.3 Instruction Set Formats

This section defines the hardware-level encoding of the DSP1628 device instructions. Multiply/ALU Instructions Special Function Instructions Format 1: Multiply/ALU Read/Write Group Field TD S F 1 X Y Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 1a: Multiply/ALU Read/Write Group Field Ta T SF 1 X Y Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 2: Multiply/ALU Read/Write Group Field TD S F 1 X Y Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 2a: Multiply/ALU Read/Write Group Field Ta T SF 1 X Y Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 3: F2 ALU Special Functions Field T D S F2 CON Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Format 3a: F3 ALU Operations Field T D S F3 SRC2 aT 0 1 Immediate Operand (IM16) Bit 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Format 3b: BMU Operations Field T D S F4[3—1] 0 F4[0] AR Immediate Operand (IM16) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 67 Format 4: Branch Direct Group Field TJ A Bit 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Format 5: Branch Indirect Group Field T B reserved 0 Bit 1 5 1 4 1 3 1 2 1 1 1 0 98765432 10 Format 6: Conditional Branch Qualifier/Software Interrupt (icall) Note that a branch instruction immediately follows except for a software interrupt (icall). Field T SI reserved CON Bit 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Format 7: Data Move Group Field Ta T R Y/Z Bit 1 5 1 4 1 3 1 2 1 1 1 09 8765 43 210 Format 8: Data Move (immediate operand — 2 words) Field T D R reserved Immediate Operand (IM16) Bit 1 5 1 4 1 3 1 2 1 1 1 0 98765 43 210 Format 9: Short Immediate Group Field T I Short Immediate Operand (IM9) Bit 1 5 1 4 1 3 1 2 1 1 1 0 98 76543210 Format 9a: Direct Addressing Field T R/W DR 1 OFFSET Bit 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 Format 10: Do/Redo Field TN K Bit 1 5 1 4 1 3 1 2 1 1 1 0 9876543210

Table 45. T Field Table 46. D Field Table 47. aT Field Table 48. S Field Table 49. F1 Field Table 50. X Field Specifies the type of instruction.

00010 Short imm j, k, rb, re 9

00011 Short imm r0, r1, r2, r3 9

00100 Y = a1[l] F1 1

00101 Z : aT[l] F1 2a

00110 Y F1 1

01000 Bit 0 = 0, aT = R 7

01000 Bit 0 = 1, aTl = R 7

01001 Bit 10 = 0, R = a0 7

01001 Bit 10 = 1, R = a0l 7

01010 R = IM16 8

01011 Bit 10 = 0, R = a1 7

01011 Bit 10 = 1, R = a1l 7

01100 Y = R 7

01101 Z : R 7

01111 R = Y 7

10100 Y = y[l] F1 1

10101 Z : y[l] F1 2

11000 Bit 0 = 0, branch indirect 5

11000 Bit 0 = 1, F3 ALU 3a

11100 Y = a0[l] F1 1

11101 Z : y x = X F1 2

11110 Bit 5 = 0, F4 ALU (BMU) 3b

11110 Bit 5 = 1, direct addressing 9a

Specifies a destination accumulator.

0 Accumulator 0

1 Accumulator 1

Specifies transfer accumulator.

0 Accumulator 1

1 Accumulator 0

Specifies a source accumulator. Specifies the multiply/ALU function.

Table 51. Y Field Table 52. Z Field Table 53. F2 Field Table 54. CON Field dressing with postmodification. Specifies the special function to be performed. tional control instructions.

Table 55. R Field Table 56. B Field Table 58. I Field Table 59. SI Field Specifies the register for data move instructions.

001111 Reserved 101111 eir

011110 Reserved 111110 ear

Table 57. DR Field

0 Not a software interrupt

1 Software interrupt

executed. Zero specifies use of value in cloop register. A zero specifies a write, *(OFFSET) = DR. A one specifies a read, DR = *(OFFSET). Table 60. F3 Field Table 61. SRC2 Field Specifies the operation in an F3 ALU instruction. Specifies operands in an F3 ALU instruction. Table 62. BMU Encodings

6 Signal Descriptions

Figure 12. DSP1628 Pinout by Interface nals can be separated into five interfaces as shown.

6.1 System Interface

and reset signals for the processor. Reset clears IACK, VEC[3:0]/IOBIT[4:7], IBF, and IBF2. The DAU condition flags are not affected by reset. (see Section 4.4, Memory Maps and Wait-States). at a lower frequency than the internal processor clock.

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 73

6 Signal Descriptions (continued)

Input Clock 2: Used with mask-programmable input clock options which require an external small signal dif- ferential across CKI and CKI2 (see Table 1, Pin De- scriptions). When the CMOS option is selected, this pin should be tied to V SSA . STOP Stop Input Clock: Negative assertion. A high-to-low transition synchronously stops all of the internal proces- sor clocks leaving the processor in a defined state. Re- turning the pin high will synchronously restart the processor clocks to continue program execution from where it left off without any loss of state. This hardware feature has the same effect as setting the NOCK bit in the powerc register (see Table 43). CKO Clock Out: Buffered output clock with options pro- grammable via the ioc register (see Table 42). The se- lectable CKO options (see Tables 42 and 33) are as follows: n A free-running output clock at the frequency of the internal processor clock; runs at the internal ring os- cillator frequency when SLOWCKI is enabled. n A wait-stated clock based on the internal instruction cycle; runs at the internal ring oscillator frequency when SLOWCKI is enabled. n A sequenced, wait-stated clock based on the EMI sequencer cycle; runs at the internal ring oscillator frequency when SLOWCKI is enabled. n A free-running output clock that runs at the CKI rate, independent of the powerc register setting. This option is only available with the small-signal clock options. When the PLL is selected, the CKO fre- quency equals the input CKI frequency regardless of how the PLL is programmed. n A logic 0. n A logic 1. INT[1:0] Processor Interrupts 0 and 1: Positive assertion. Hardware interrupt inputs to the DSP1628. Each is en- abled via the inc register. When enabled and asserted, each cause the processor to vector to the memory loca- tion described in Table 4. INT1 is used in conjunction with EXM to select the desired reset initialization of the mwait register (see Table 40). When both INT0 and RSTB are asserted, all output and bidirectional pins (except TDO, which 3-states by JTAG control) are put in a 3-state condition. VEC[3:0] Interrupt Output Vector: These four pins indicate which interrupt is currently being serviced by the device. Table 4 shows the code associated with each interrupt condition. VEC[3:0] are multiplexed with IOBIT[4:7]. IACK Interrupt Acknowledge: Positive assertion. IACK signals when an interrupt is being serviced by the DSP1628. IACK remains asserted while in an interrupt service routine, and is cleared when the ireturn instruc- tion is executed. TRAP Trap Signal: Positive assertion. When asserted, the processor is put into the trap condition, which normally causes a branch to the location 0x0046. The hardware development system (HDS) can configure the trap pin to cause an HDS trap, which causes a branch to loca- tion 0x0003. Although normally an input, the pin can be configured as an output by the HDS. As an output, the pin can be used to signal an HDS breakpoint in a multi- ple processor environment.

DSP1628 Digital Signal Processor February 1997 74 Lucent Technologies Inc.

6.2 External Memory Interface

The external memory interface is used to interface the DSP1628 to external memory and I/O devices. It sup- ports read/write operations from/to program and data memory spaces. The interface supports four external memory segments. Each external memory segment can have an independent number of software-program- mable wait-states. One hardware address is decoded, and an enable line is provided, to allow glueless I/O in- terfacing. AB[15:0] External Memory Address Bus: Output only. This 16-bit bus supplies the address for read or write operations to the external memory or I/O. During exter- nal memory accesses, AB[15:0] retain the value of the last valid external access. DB[15:0] External Memory Data Bus: This 16-bit bidirectional data bus is used for read or write operations to the ex- ternal memory or I/O. RWN Read/Write Not: When a logic 1, the pin indicates that the memory access is a read operation. When a logic 0, the memory access is a write operation. EXM External Memory Select: Input only. This signal is latched into the device on the rising edge of RSTB. The value of EXM latched in determines whether the internal ROM is addressable in the instruction/coefficient mem- ory map. If EXM is low, internal ROM is addressable. If EXM is high, only external ROM is addressable in the instruction/coefficient memory map (see Table 5, In- struction/Coefficient Memory Maps). EXM chooses be- tween MAP1 or MAP2 and between MAP3 or MAP4. EROM External ROM Enable Signal: Negative assertion. When asserted, the signal indicates an access to external program memory (see Table 5, Instruction/ Coefficient Memory Maps). This signal's leading edge can be delayed via the ioc register (see Table 42). ERAMHI External RAM High Enable Signal: Negative asser- tion. When asserted, the signal indicates an access to external data memory addresses 0x8000 through 0xFFFF (see Table 6, Data Memory Map). This signal's leading edge can be delayed via the ioc register (see Table 42). ERAMLO External RAM Low Enable Signal: Negative asser- tion. When asserted, the signal indicates an access to external data memory addresses 0x4100 through 0x7FFF (see Table 6, Data Memory Map). This signal's leading edge can be delayed via the ioc register (see Table 42). IO External I/O Enable Signal: Negative assertion. When asserted, the signal indicates an access to external data memory addresses 0x4000 through 0x40FF (see Table , Data Memory Map). This memory segment is in- tended for memory-mapped I/O. This signal's leading edge can be delayed via the ioc register (see Table 42).

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 75

6.3 Serial Interface #1

The serial interface pins implement a full-featured syn- chronous/asynchronous serial I/O channel. In addition, several pins offer a glueless TDM interface for multipro- cessing communication applications (see Figure 6, Mul- tiprocessor Communications and Connections). DI1 Data Input: Serial data is latched on the rising edge of ICK1, either LSB or MSB first, according to the sioc reg- ister MSB field (see Table 26). ICK1 Input Clock: The clock for serial input data. In active mode, ICK1 is an output; in passive mode, ICK1 is an input, according to the sioc register ICK field (see Table 26). Input has typically 0.7 V hysteresis. ILD1 Input Load: The clock for loading the input buffer, sdx[in], from the input shift register isr. A falling edge of ILD1 indicates the beginning of a serial input word. In active mode, ILD1 is an output; in passive mode, ILD1 is an input, according to the sioc register ILD field (see Table 26). Input has typically 0.7 V hysteresis. IBF1 Input Buffer Full: Positive assertion. IBF1 is asserted when the input buffer, sdx[in], is filled. IBF1 is negated by a read of the buffer, as in a0 = sdx. IBF1 is also ne- gated by asserting RSTB. DO1 Data Output: The serial data output from the output shift register (osr), either LSB or MSB first (according to the sioc register MSB field). DO1 changes on the rising edges of OCK1. DO1 is 3-stated when DOEN1 is high. DOEN1 Data Output Enable: Negative assertion. An input when not in the multiprocessor mode. DO1 and SADD1 are enabled only if DOEN1 is low. DOEN1 is bidirection- al when in the multiprocessor mode (tdms register MODE field set). In the multiprocessor mode, DOEN1 indicates a valid time slot for a serial output. OCK1 Output Clock: The clock for serial output data. In ac- tive mode, OCK1 is an output; in passive mode, OCK1 is an input, according to the sioc register OCK field (see Table 26). Input has typically 0.7 V hysteresis. OLD1 Output Load: The clock for loading the output shift reg- ister, osr, from the output buffer sdx[out]. A falling edge of OLD1 indicates the beginning of a serial output word. In active mode, OLD1 is an output; in passive, OLD1 is an input, according to the sioc register OLD field (see Table 26). Input has typically 0.7 V hysteresis. OBE1 Output Buffer Empty: Positive assertion. OBE1 is as- serted when the output buffer, sdx[out], is emptied (moved to the output shift register for transmission). It is cleared with a write to the buffer, as in sdx = a0. OBE1 is also set by asserting RSTB. SADD1 Serial Address: Negative assertion. A 16-bit serial bit stream typically used for addressing during multipro- cessor communication between multiple DSP16xx de- vices. In multiprocessor mode, SADD1 is an output when the tdms time slot dictates a serial transmission; otherwise, it is an input. Both the source and destination DSP can be identified in the transmission. SADD1 is al- ways an output when not in multiprocessor mode and can be used as a second 16-bit serial output. See the DSP1611/17/18/27 Digital Signal Processor Informa- tion Manual for additional information. SADD1 is 3- stated when DOEN1 is high. When used on a bus, SADD1 should be pulled high through a 5 kΩ resistor. SYNC1 Multiprocessor Synchronization: Typically used in the multiprocessor mode, a falling edge of SYNC1 indi- cates the first word (time slot 0) of a TDM I/O stream and causes the resynchronization of the active ILD1 and OLD1 generators. SYNC1 is an output when the tdms register SYNC field is set (i.e., selects the master DSP and uses time slot 0 for transmit). As an input, SYNC1 must be tied low unless part of a TDM interface. When used as an output, SYNC1 = [ILD1/OLD1]/8 or 16, depending on the setting of the SYNCSP field of the tdms register. When configured as described above, SYNC1 can be used to generate a slow clock for SIO operations. Input has typically 0.7 V hysteresis.

DSP1628 Digital Signal Processor February 1997 76 Lucent Technologies Inc. Interface #2 and Control I/O Interface This interface pin multiplexes a parallel host interface with a second serial I/O interface and a 4-bit I/O inter- face. The interface selection is made by writing the ESIO2 bit in the ioc register (see Table 42 and Section 4.1). The functions and signals for the second SIO correspond exactly with those in SIO #1. Therefore, the pin descriptions below discuss only PHIF and BIO pin functionality. PB[7:0] Parallel I/O Data Bus: This 8-bit bidirectional bus is used to input data to, or output data from, the PHIF. Note that PB[3:0] are pin multiplexed with SIO2 func- tionality, and PB[7:4] are pin multiplexed with BIO unit pins IOBIT[3:0] (see Section 4.1). PCSN Peripheral Chip Select Not: Negative assertion. PCSN is an input. While PCSN is low, the data strobes PIDS and PODS are enabled. While PCSN is high, the DSP1628 ignores any activity on PIDS and PODS. PBSEL Peripheral Byte Select: An input pin, configurable in software. Selects the high or low byte of pdx0 available for host accesses. PSTAT Peripheral Status Select: PSTAT is an input. When a logic 0, the PHIF will output the pdx0[out] register on the PB bus. When a logic 1, the PHIF will output the contents of the PSTAT register on PB[7:0]. PIDS Parallel Input Data Strobe: An input pin, software con- figurable to support both Intel and Motorola protocols. In Intel mode: Negative assertion. PIDS is pulled low by an external device to indicate that data is available on the PB bus. The DSP latches data on the PB bus on the rising edge (low-to-high transition) of PIDS or PCSN, whichever comes first. In Motorola mode: PIDS/PRWN functions as a read/ write strobe. The external device sets PIDS/PRWN to a logic 0 to indicate that data is available on the PB bus (write operation by the external device). A logic 1 on PIDS/PRWN indicates an external read operation by the external device. PODS Parallel Output Data Strobe: An input pin, software configurable to support both Intel and Motorola proto- cols. In Intel mode: Negative assertion. When PODS is pulled low by an external device, the DSP1628 places the contents of the parallel output register, pdx0, onto the PB bus. In Motorola mode: Software-configurable assertion level. The external device uses PODS/PDS as its data strobe for both read and write operations. PIBF Parallel Input Buffer Full: An output pin with positive assertion; configurable in software. This flag is cleared after reset, indicating an empty input buffer pdx0[in]. PIBF is set immediately after the rising edge of PIDS or PCSN, indicating that data has been latched into the pdx0[in] register. When the DSP1628 reads the con- tents of this register, emptying the buffer, the flag is cleared. Configured in software, PIBF may become the logical OR of the PIBF and POBE flags. POBE Parallel Output Buffer Empty: An output pin with pos- itive assertion; configurable in software. This flag is set after reset, indicating an empty output buffer pdx0[out]. POBE is set immediately after the rising edge of PODS or PCSN, indicating that the data in pdx0[out] has been driven onto the PB bus. When the DSP1628 writes to pdx0[out], filling the buffer, this flag is cleared.

6.5 Control I/O Interface

This interface is used for status and control operations provided by the bit I/O unit of the DSP1628. It is pin mul- tiplexed with the PHIF and VEC[3:0] pins (see Section 4.1). Setting the ESIO2 and EBIOH bits in the ioc reg- ister provides a full 8-bit BIO interface at the associated pins. IOBIT[7:0] I/O Bits [7:0]: Each of these bits can be independently configured as either an input or an output. As outputs, they can be independently set, toggled, or cleared. As inputs, they can be tested independently or in combina- tions for various data patterns.

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 77

6.6 JTAG Test Interface

The JTAG test interface has features that allow pro- grams and data to be downloaded into the DSP via four pins. This provides extensive test and diagnostic capa- bility. In addition, internal circuitry allows the device to be controlled through the JTAG port to provide on-chip in-circuit emulation. Lucent Technologies provides hardware and software tools to interface to the on-chip HDS via the JTAG port. Note: The DSP1628 provides all JTAG/ IEEE 1149.1 standard test capabilities including boundary scan. See the DSP1611/17/18/27 Digital Signal Processor Information Manual for additional in- formation on the JTAG test interface. TDI Test Data Input: JTAG serial input signal. All serial- scanned data and instructions are input on this pin. This pin has an internal pull-up resistor. TDO Test Data Output: JTAG serial output signal. Serial- scanned data and status bits are output on this pin. TMS Test Mode Select: JTAG mode control signal that, when combined with TCK, controls the scan operations. This pin has an internal pull-up resistor. TCK Test Clock: JTAG serial shift clock. This signal clocks all data into the port through TDI, and out of the port through TDO, and controls the port by latching the TMS signal inside the state-machine controller. TRST Test Reset: Negative assertion. JTAG test reset. When asserted low, asynchronously resets JTAG TAP con- troller. In an application environment, this pin must be asserted prior to or concurrent with RSTB. This pin has an internal pull-up resistor.

7 Mask-Programmable Options

memory map option, and the hardware emulation or ROM security option, as summarized in Table 63. and must reside in the first 4 Kwords of ROM. of ROM. See the DSP1600 Support Tools Manual for detailed information.

7.1 Input Clock Options

CKI frequency is the internal clock frequency.

7.2 Memory Map Options

of DPRAM. See Section 4.4 Memory Maps and Wait-States for further description.

7.3 ROM Security Options

DSP1600 Support Tools Manual for more detailed information. Table 63. DSP1628 ROM Options

16 Kwords DPRAM

8 Kwords DPRAM

8 Device Characteristics

8.1 Absolute Maximum Ratings

periods can adversely affect device reliability.

8.2 Handling Precautions

1500 Ω are the most common and are the values used in the Lucent Technologies human-body model test circuit. The breakdown voltage for the DSP1628 is greater than 2000 V.

8.3 Recommended Operating Conditions

Table 64. Recommended Operating Conditions

DSP1628 Digital Signal Processor February 1997 80 Lucent Technologies Inc.

8 Device Characteristics (continued)

8.4 Package Thermal Considerations

The recommended operating temperature specified above is based on the maximum power, package type, and maximum junction temperature. The following equations describe the relationship between these parameters. If the applications' maximum power is less than the worst-case value, this relationship determines a higher maximum am- bient temperature or the maximum temperature measured at top dead center of the package. T A = TJ – P x Θ JA TTDC = TJ – P x Θ J-TDC where TA is the still-air ambient temperature and TTDC is the temperature measured by a thermocouple at the top dead center of the package. WARNING: Due to package thermal constraints, proper precautions in the user's application should be taken to avoid exceeding the maximum junction temperature of 100 °C. Otherwise, the device will be affected adversely. The applications' maximum power, the package type, and the maximum ambient temperature determine the maxi- mum activity factors for the error correction coprocessor as well as for the DSP core and its peripherals. The follow- ing equations describe the relationship between these parameters. If the applications' maximum power is less than the worst-case value, this relationship permits higher activity factors. For these calculations, refer to Section 4.13, Power Management and Section 9.1, Power Dissipation. P = MIPS x [AF ECCP (PECCP /MIPS) + AFDSP (PDSP /MIPS) + (1 – AFDSP ) (PSLEEP /MIPS)] P x Θ JA + 85 °C <= 125 °C where: P = Maximum power in mW MIPS = Device speed (internal clock speed ÷ 106) AF ECCP = Activity factor for error correction coprocessor (ECCP) AF DSP = Activity factor for DSP core and peripherals AF SLEEP = Activity factor for sleep mode operation = 1 – AFDSP PECCP = Power dissipation in mW for ECCP PDSP = Power dissipation in mW for DSP core and peripherals PSLEEP = Power dissipation in mW for sleep mode operation For example, for a TQFP device operating at 50 MIPS in a 3 V application with 40% ECCP activity, 100% DSP ac- tivity, and 0% sleep activity, the equation would look like this: 50 MIPS x [0.4 (35 mW/50 MIPS) + 1.0(125 mW/50 MIPS) + 0] = 139 mW 139 mW x 64 °C/W + 85 °C = 94 °C <= 100 °C The above example demonstrates the maximum operating capability in the TQFP package. Note: The power calculations listed are for internal power dissipation only. The external power dissipation due to output pins switching must also be included.

9 Electrical Characteristics and Requirements

Recommended Operating Conditions. Table 61. Electrical Characteristics and Requirements Table 62. Electrical Requirements for Mask-Programmable Input Clock Options

Table 63. PLL Electrical Specifications, VCO Frequency Ranges Table 64. PLL Electrical Specifications and pllc Register Settings

Figure 9. Plot of V Figure 10. Plot of V

9.1 Power Dissipation

• T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).

= PLL lock time (see Table 64). Table 65. Power Dissipation and Wake-Up Latency

3 V 3 V 3 V 3 V

• T = CKI clock cycle for 1X input clock option or T = CKI clock cycle divided by M/(2N) for PLL clock option (see Section 4.12).

= PLL lock time (see Table 64). wise, high currents may flow.

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 86 10 Timing Characteristics for 2.7 V Operation The following timing characteristics and requirements are preliminary information and are subject to change. Timing characteristics refer to the behavior of the device under specified conditions. Timing requirements refer to conditions imposed on the user for proper operation of the device. All timing data is valid for the following conditions: T A = –40 °C to +85 °C (See Section 8.3.) VDD = 3 V ± 10%, VSS = 0 V (See Section 8.3.) Capacitance load on outputs (CL) = 50 pF, except for CKO, where CL = 20 pF Output characteristics can be derated as a function of load capacitance (CL). All outputs: 0.03 ns/pF ≤ dt/dCL ≤ 0.07 ns/pF for 10 ≤ CL ≤ 100 pF at VIH for rising edge and at VIL for falling edge For example, if the actual load capacitance is 30 pF instead of 50 pF, the derating for a rising edge is (30 – 50) pF x 0.06 ns/pF = 1.2 ns less than the specified rise time or delay that includes a rise time. Test conditions for inputs: n Rise and fall times of 4 ns or less n Timing reference levels for delays = VIH, VIL Test conditions for outputs (unless noted otherwise): n C LOAD = 50 pF; except for CKO, where CLOAD = 20 pF n Timing reference levels for delays = VIH, VIL n 3-state delays measured to the high-impedance state of the output driver For the timing diagrams, see Table 62 for input clock requirements. Unless otherwise noted, CKO in the timing diagrams is the free-running CKO.

10.1 DSP Clock Generation

• See Table 62 for input clock electrical requirements.

‡ Wait-stated clock (see Table 38). § W = number of wait-states. Figure 11. I/O Clock Timing Diagram

• Device speeds greater than 50 MIPS do not support 1X operation. Use the PLL.

† Device is fully static, t1 is tested at 100 ns for 1X input clock option, and memory hold time is tested at 0.1 s.

• T = internal clock period, set by CKI or by CKI and the PLL parameters.

Table 66. Timing Requirements for Input Clock Table 67. Timing Characteristics for Input Clock and Output Clock

10.2 Reset Circuit

1. Chip reset at initial powerup.
2. Chip reset following a drop in power supply.

Note: The TRST pin must be asserted even if the JTAG controller is not used by the application.

• See Table 60, Recommended Operating Conditions.

remains a free-running clock. † See Table 62 for input clock electrical requirements. Figure 12. Powerup Reset and Chip Reset Timing Diagram Table 68. Timing Requirements for Powerup Reset and Chip Reset Table 69. Timing Characteristics for Powerup Reset and Chip Reset

10.3 Reset Synchronization

• See Table 62 for input clock electrical requirements.

Note 1: CKO1 and CKO2 are two possible CKO states before reset. CKO is free-running. Figure 13. Reset Synchronization Timing Table 70. Timing Requirements for Reset Synchronization Timing

10.4 JTAG I/O Specifications

Figure 14. JTAG Timing Diagram Table 71. Timing Requirements for JTAG Input/Output Table 72. Timing Characteristics for JTAG Input/Output

10.5 Interrupt

† IACK assertion is guaranteed to be enclosed by VEC[3:0] assertion. Figure 15. Interrupt Timing Diagram Table 73. Timing Requirements for Interrupt Table 74. Timing Characteristics for Interrupt Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts. Note: Interrupt is asserted during an interruptible instruction and no other pending interrupts.

10.6 Bit Input/Output (BIO)

Figure 16. Write Outputs Followed by Read Inputs (cbit = Immediate; a1 = sbit) Figure 17. Write Outputs and Test Inputs (cbit = Immediate) Table 75. Timing Requirements for BIO Input Read Table 76. Timing Characteristics for BIO Output Table 77. Timing Requirements for BIO Input Test

10.7 External Memory Interface

detailed description of the external memory interface including other functional diagrams.

• W = number of wait-states.

Figure 18. Enable Transition Timing Table 78. Timing Characteristics for External Memory Enables (EROM, ERAMHI, IO, ERAMLO) Table 79. Timing Characteristics for Delayed External Memory Enables (ioc = 0x000F)

• W = number of wait-states.

Figure 19. External Memory Data Read Timing Diagram Table 80. Timing Characteristics for External Memory Access Table 81. Timing Requirements for External Memory Read (EROM, ERAMHI, IO, ERAMLO)

• W = number of wait-states.

Figure 20. External Memory Data Write Timing Diagram Table 82. Timing Characteristics for External Memory Data Write (All Enables)

• W = number of wait-states.

Figure 21. Write Cycle Followed by Read Cycle Table 83. Timing Characteristics for Write Cycle Followed by Read Cycle

10.8 PHIF Specifications

writes are identical to one-half of a 16-bit access. Figure 22. PHIF Intel Mode Signaling (Read and Write) Timing Diagram first. All requirements referenced to PCSN apply to PIDS or PODS, if PIDS or PODS is the controlling signal. Table 84. Timing Requirements for PHIF Intel Mode Signaling Table 85. Timing Characteristics for PHIF

Figure 23. PHIF Intel Mode Signaling (Pulse Period and Flags) Timing Diagram PCSN or PIDS, whichever comes first. t54 apply to the inverted levels as well as those shown. Table 86. Timing Requirements for PHIF Intel Mode Signaling Table 87. Timing Characteristics for PHIF

Figure 24. PHIF Motorola Mode Signaling (Read and Write) Timing Diagram should be referenced to PDS, if PDS is the controlling signal. PRWN should never be used to initiate or complete a transaction. the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. Table 88. Timing Requirements for PHIF Motorola Mode Signaling Table 89. Timing Characteristics for PHIF Motorola Mode Signaling

Figure 25. PHIF Motorola Mode Signaling (Pulse Period and Flags) Timing Diagram to PDS going low, if PDS goes low after PCSN. An input/output transaction is completed by PCSN or PDS going high, whichever comes first. be the opposite logic levels shown in the diagram. t53 and t54 apply to the inverted levels as well as those shown. Table 90. Timing Characteristics for PHIF Motorola Mode Signaling Table 91. Timing Requirements for PHIF Motorola Mode Signaling

101 Lucent Technologies Inc.

• Motorola mode signal name.

Figure 26. PHIF Intel or Motorola Mode Signaling (Status Register Read) Timing Diagram † t45, t47, and t49 are referenced to the falling edge of PCSN or PODS(PDS), whichever occurs last. ‡ t46, t48, t154, and t50 are referenced to the rising edge of PCSN or PODS(PDS), whichever occurs first. Table 92. Timing Requirements for Intel and Motorola Mode Signaling (Status Register Read) Table 93. Timing Characteristics for Intel and Motorola Mode Signaling (Status Register Read)

103 Lucent Technologies Inc.

10.9 Serial I/O Specifications

Figure 29. SIO Passive Mode Input Timing Diagram † For multiprocessor mode, see note in Section 10.10. ‡ Device is fully static; t70 is tested at 200 ns. Table 96. Timing Requirements for Serial Inputs Table 97. Timing Characteristics for Serial Outputs

• ILD goes high during bit 6 (of 0:15), N = 8 or 16.

Figure 30. SIO Active Mode Input Timing Diagram Table 98. Timing Requirements for Serial Inputs Table 99. Timing Characteristics for Serial Outputs

105 Lucent Technologies Inc. Figure 31. SIO Passive Mode Output Timing Diagram † For multiprocessor mode, see note in Section 10.10. ‡ Device is fully static; t80 is tested at 200 ns. Table 100. Timing Requirements for Serial Inputs Table 101. Timing Characteristics for Serial Outputs

• OLD goes high at the end of bit 6 of 0:15.

Figure 32. SIO Active Mode Output Timing Diagram Table 102. Timing Characteristics for Serial Output

107 Lucent Technologies Inc.

• See sioc register, LD field.

Figure 33. Serial I/O Active Mode Clock Timing Table 103. Timing Characteristics for Signal Generation

10.10 Multiprocessor Communication

• Negative edge initiates time slot 0.

Figure 34. SIO Multiprocessor Timing Diagram multiprocessor mode, assuming 50% duty cycle, is calculated as (t77 + t116) x 2.

• With capacitance load on ICK, OCK, DO, SYNC, and SADD = 100 pF, add 4 ns to t116—t122.

Table 104. Timing Requirements for SIO Multiprocessor Communication Table 105. Timing Characteristics for SIO Multiprocessor Communication

DSP1628 Digital Signal Processor February 1997 109 Lucent Technologies Inc.

11 Outline Diagrams

11.1 100-Pin BQFP (Bumpered Quad Flat Pack) All dimensions are in millimeters. 5-1970.r10 PIN #1 IDENTIFIER ZONE 89113 39 63 19.050 ± 0.405 22.350 ± 0.255 22.860 ± 0.305 22.350 ± 0.255 19.050 ± 0.405 22.860 ± 0.305 EDGE CHAMFER DETAIL A

4.570 MAXDETAIL B

0.760 ± 0.2550.635 TYP 0.10 SEATING PLANE 3.555 ± 0.255 DETAIL A 0.255 0.91/1.17 GAGE PLANE SEATING PLANE DETAIL B 0.280 ± 0.075 0.150 M 0.175 ± 0.025

February 1997 DSP1628 Digital Signal Processor Lucent Technologies Inc. 110

11 Outline Diagrams (continued)

11.2 100-Pin TQFP (Thin Quad Flat Pack) All dimensions are in millimeters. 5-2146.r14

0.50 TYP

1.60 MAX

0.08 1.40 ± 0.05 0.05/0.15 DETAIL A DETAIL B 14.00 ± 0.20 16.00 ± 0.20 76100 26 50 14.00 ± 0.20 16.00 ± 0.20 PIN #1 IDENTIFIER ZONE DETAIL A 0.45/0.75 GAGE PLANE SEATING PLANE

1.00 REF

0.25 DETAIL B 0.19/0.27 0.08 M 0.106/0.200

DSP1628 Digital Signal Processor February 1997 111 Lucent Technologies Inc. 11.3 144-Pin PBGA (Plastic Ball Grid Array) All dimensions are in millimeters. 5-5205 (C) – 0.21 SEATING PLANE SOLDER BALL0.40 ± 0.10 0.20 PWB MOLD COMPOUND PIN A1 CORNER 13.00 ± 0.20 13.00 ± 0.20 11.50 +0.70 –0.00 11.50 +0.70 –0.00 A B C D E F G H J K L M 1 2 3 4 5 6 7 8 9 10 11 12 11 SPACES @ 1.00 = 11.00 PIN A1 CORNER

11 SPACES @

1.00 = 11.00 0.50 ± 0.10 TOP VIEW SIDE VIEW BOTTOM VIEW

For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro U.S.A.: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18103 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106), e-mail docmaster@micro.lucent.com ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 For data requests in Europe: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1734 324 299, FAX (44) 1734 328 148 For technical inquiries in Europe: CENTRAL EUROPE: (49) 89 95086 0 (Munich), NORTHERN EUROPE: (44) 1344 865 900 (Bracknell UK), FRANCE: (33) 1 41 45 77 00 (Paris), SOUTHERN EUROPE: (39) 2 6601 1800 (Milan) or (34) 1 807 1700 (Madrid) Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. Copyright © 1997 Lucent Technologies Inc. All Rights Reserved Printed in U.S.A. February 1997 DS97-040WDSP Printed On Recycled Paper