DS89C440-MNL

DS89C430 DALLAS | Alldatasheet

Document overview

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Technical content

1 of 48 REV: 060805 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS89C430, DS89C440, and DS89C450 offer the highest performance available in 8051-compatible microcontrollers. They feature newly designed processor cores that execute instructions up to 12 times faster than the original 8051 at the same crystal speed. Typical applications will experience a speed improvement up to 10x. At 1 million instructions per second (MIPS) per megahertz, the microcontrollers achieve 33 MIPS performance from a maximum 33MHz clock rate. The Ultra-High-Speed Flash Microcontroller User’s Guide should be used in conjunction with this data sheet. Download it at www.maxim-ic.com/microcontrollers.

ORDERING INFORMATION

DS89C430-MNL+ 16kB 40 PDIP DS89C430-QNL 16kB 44 PLCC DS89C430-QNL+ 16kB 44 PLCC DS89C430-ENL 16kB 44 TQFP DS89C430-ENL+ 16kB 44 TQFP DS89C440-MNL 32kB 40 PDIP DS89C440-MNL+ 32kB 40 PDIP DS89C440-QNL 32kB 44 PLCC DS89C440-QNL+ 32kB 44 PLCC DS89C440-ENL 32kB 44 TQFP DS89C440-ENL 32kB 44 TQFP DS89C450-MNL 64kB 40 PDIP DS89C450-MNL+ 64kB 40 PDIP DS89C450-QNL 64kB 44 PLCC DS89C450-QNL+ 64kB 44 PLCC DS89C450-ENL 64kB 44 TQFP DS89C450-ENL+ 64kB 44 TQFP + Denotes a lead-free/RoHS-compliant device. Complete Selector Guide appears at end of data sheet. Pin Configurations appear at end of data sheet.

FEATURES

/g167/g32High-Speed 8051 Architecture One Clock-Per-Machine Cycle DC to 33MHz Operation Single Cycle Instruction in 30ns Optional Variable Length MOVX to Access Fast/Slow Peripherals Dual Data Pointers with Automatic Increment/Decrement and Toggle Select Supports Four Paged Memory-Access Modes /g167/g32On-Chip Memory 16kB/32kB/64kB Flash Memory In-Application Programmable In-System Programmable Through Serial Port 1kB SRAM for MOVX /g167/g3280C52 Compatible

8051 Pin and Instruction Set Compatible

Four Bidirectional, 8-Bit I/O Ports Three 16-Bit Timer Counters

256 Bytes Scratchpad RAM

/g167/g32Power-Management Mode Programmable Clock Divider Automatic Hardware and Software Exit /g167/g32ROMSIZE Feature Selects Internal Program Memory Size from 0 to 64kB Allows Access to Entire External Memory Map Dynamically Adjustable by Software /g167/g32Peripheral Features Two Full-Duplex Serial Ports Programmable Watchdog Timer

13 Interrupt Sources (Six External)

Five Levels of Interrupt Priority Power-Fail Reset Early Warning Power-Fail Interrupt Electromagnetic Interference (EMI) Reduction

APPLICATIONS

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers www.maxim-ic.com

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 2 of 48 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL MIN TYP MAX UNITS Supply Voltage (Notes 2, 3) V CC 4.5 5.0 5.5 V Power-Fail Warning (Notes 2, 4) V PFW 4.2 4.375 4.6 V Reset Trip Point (Min Operating Voltage) (Notes 2, 3, 4) V RST 3.95 4.125 4.35 V Supply Current, Active Mode (Note 5) I CC 75 110 mA Supply Current, Idle Mode at 33MHz (Note 6) I IDLE 40 50 mA Supply Current, Stop Mode, Bandgap Disabled (Note 7) I STOP 1 100 /g109A Supply Current, Stop Mode, Bandgap Enabled (Note 7) I SPBG 150 300 /g109A Input Low Level (Note 2) V IL -0.3 +0.8 V Input High Level (Note 2) V IH 2.0 V CC + 0.3 V Input High Level XTAL and RST (Note 2) V IH2 3.5 V CC + 0.3 V Output Low Voltage, Port 1 and 3 at IOL = 1.6mA (Note 2) V OL1 0.15 0.45 V Output Low Voltage, Port 0 and 2, ALE, PSEN at IOL = 3.2mA (Note 2) VOL2 0.15 0.45 V Output High Voltage, Port 1, 2, and 3, at IOH = -50/g109A (Notes 2, 8) VOH1 2.4 V Output High Voltage, Port 1, 2, and 3 at IOH = -1.5mA (Notes 2, 9) V OH2 2.4 V Output High Voltage, Port 0, 1, 2, ALE, PSEN, RD, WR in Bus Mode at IOH = -8mA (Notes 2, 10) VOH3 2.4 V Output High Voltage, RST at IOL = -0.4mA (Note 2, 11) V OH4 2.4 V Input Low Current, Port 1, 2, and 3 at 0.4V I IL -50 /g109A Transition Current from 1 to 0, Port 1, 2, and 3 at 2V (Note 12) I TL -650 /g109A Input Leakage Current, Port 0 in I/O Mode and EA (Note 13) I L -10 +10 /g109A Input Current, Port 0 in Bus Mode (Note 14) I L -300 +300 /g109A RST Pulldown Resistance (Note 13) R RST 50 120 200 k /g87

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 3 of 48 Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: The user should note that this part is tested and guaranteed to operate down to 4.5V (10%) and that VRST (min) is specified below that point. This indicates that there is a range of voltages [(VMIN to VRST (min)] where the processor's operation is not guaranteed, but the reset trip point has not been reached. This should not be an issue in most applications, but should be considered when proper operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset. Note 4: While the specifications for VPFW and VRST overlap, the design of the hardware makes it so this is not possible. Within the ranges given, there is guaranteed separation between these two voltages. Note 5: Active current is measured with a 33MHz clock source driving XTAL1, VCC = RST = 5.5V. All other pins are disconnected. Note 6: Idle mode current is measured with a 33MHz clock source driving XTAL1, VCC = 5.5V, RST at ground. All other pins are disconnected. Note 7: Stop mode is measured with XTAL and RST grounded, VCC = 5.5V. All other pins are disconnected. Note 8: RST = 5.5V. This condition mimics the operation of pins in I/O mode. Note 9: During a 0-to-1 transition, a one shot drives the ports hard for two clock cycles. This measurement reflects a port pin in transition mode. Note 10: When addressing external memory. Note 11: Guaranteed by design. Note 12: Ports 1, 2, and 3 source transition current when pulled down externally. The current reaches its maximum at approximately 2V. Note 13: RST = 5.5V. Port 0 is floating during reset and when in the logic-high state during I/O mode. Note 14: This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latch at approximately 2V.

DS89C430/DS89C440/DS89C450 4 of 48 AC CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.) 1-CYCLE PAGE MODE 1 2-CYCLE PAGE MODE 1 4-CYCLE PAGE MODE 1 PAGE MODE 2 NONPAGE MODE PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS System Clock External Oscillator (Note 15) 1/tCLCL 0 33 0 33 0 33 0 33 0 33 System Clock External Crystal (Note 15) 1/tCLCL 1 33 1 33 1 33 1 33 1 33 MHz ALE Pulse Width (Note 16) t LHLL 0.5tCLCL - 2 + tSTC3 tCLCL - 2 + tSTC3 2tCLCL - 4 + tSTC3 1.5tCLCL - 5 + tSTC3 1.5tCLCL - 5 + tSTC3 ns Port 0 Instruction Address Valid to ALE Low tAVLL t CLCL - 3 0.5t CLCL - 3 ns Port 2 Instruction Address Valid to ALE Low tAVLL2 0.5t CLCL - 4 0.5t CLCL - 4 1.5t CLCL - 4 0.5t CLCL - 4 t CLCL - 4 ns Port 0 Data AddressValid to ALE Low tAVLL3 tCLCL - 3 + tSTC3 0.5tCLCL - 3 + tSTC3 ns Program Address Hold After ALE Low tLLAX 0.5t CLCL - 8 1.5t CLCL - 8 2.5t CLCL - 8 1t CLCL - 10 1t CLCL - 10 ns Address Hold after ALE Low MOVX Write tLLAX2 0.5tCLCL - 8 + tSTC4 1.5tCLCL - 8 + tSTC4 2.5tCLCL - 8 + tSTC3 0.5tCLCL - 8 + tSTC2 0.5tCLCL - 8 + tSTC2 ns Address Hold after ALE Low MOVX Read tLLAX3 0.5tCLCL - 8 + tSTC4 1.5tCLCL - 8 + tSTC4 2.5tCLCL - 8 + tSTC3 0.5tCLCL - 8 + tSTC3 0.5tCLCL - 8 + tSTC2 ns ALE Low to Valid Instruction In t LLIV 2 t CLCL - 6 2t CLCL - 6 ns ALE Low to PSEN Low t LLPL 1.5t CLCL - 6 0.5t CLCL - 2 ns PSEN Pulse Width for Program Fetch tPLPH t CLCL - 5 t CLCL - 5 2t CLCL - 5 t CLCL - 5 2t CLCL - 5 ns

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 5 of 48 AC CHARACTERISTICS (continued) (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.) 1-CYCLE PAGE MODE 1 2-CYCLE PAGE MODE 1 4-CYCLE PAGE MODE 1 PAGE MODE 2 NONPAGE MODE PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS PSEN Low to Valid Instruction In tPLIV t CLCL - 20 t CLCL - 20 2t CLCL - 20 t CLCL - 20 2t CLCL - 20 ns Input Instruction Hold After PSEN tPXIX 0 0 0 0 0 ns Input Instruction Float After PSEN tPXIZ t CLCL - 5 t CLCL - 5 ns Port 0 Address to Valid Instruction In tAVIV0 1.5t CLCL - 22 3t CLCL - 22 ns Port 2 Address to Valid Instruction In tAVIV2 t CLCL - 20 1.5t CLCL - 20 2.5t CLCL - 20 3t CLCL - 20 3.5t CLCL - 20 ns PSEN Low to Port 0 Address Float tPLAZ 0 0 ns RD Pulse Width (P3.7) (Note 16) tRLRH tCLCL - 5 + tSTC1 tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 ns WR Pulse Width (P3.6) (Note 16) tWLWH tCLCL - 5 + tSTC1 tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 ns RD (P3.7) Low to Valid Data In (Note 16) tRLDV tCLCL - 18 + tSTC1 tCLCL - 18 + tSTC1 2tCLCL - 18 + tSTC1 2tCLCL - 18 + tSTC1 2tCLCL - 18 + tSTC1 ns Data Hold After RD (P3.7) t RHDX 0 0 0 0 0 ns Data Float After RD (P3.7) t RHDZ t CLCL - 5 t CLCL - 5 ns MOVX ALE Low to Input Data Valid (Note 16) tLLDV 2tCLCL - 8 + tSTC1 2tCLCL - 5 + tSTC1 ns

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 6 of 48 AC CHARACTERISTICS (continued) (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (See Figure 1, Figure 2, and Figure 3.) 1-CYCLE PAGE MODE 1 2-CYCLE PAGE MODE 1 4-CYCLE PAGE MODE 1 PAGE MODE 2 NONPAGE MODE PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS Port 0 Address to Valid Data In (Note 16) tAVDV0 3tCLCL - 20 + tSTC1 3tCLCL - 20 + tSTC1 ns Port 2 Address to Valid Data In (Note 16) tAVDV2 tCLCL - 20 + tSTC1 1.5tCLCL - 20 + tSTC1 3.5tCLCL - 20 + tSTC1 3.0tCLCL - 20 + tSTC1 3.5tCLCL - 20 + tSTC1 ns ALE Low to RD or WR Low (Note 16) tLLRL (tLLWL) 0.5tCLCL - 8 + tSTC2 0.5tCLCL + 6 + tSTC2 2tCLCL - 8 + tSTC2 2tCLCL + 6 + tSTC2 4tCLCL - 8 + tSTC2 4tCLCL + 6 + tSTC2 0.5tCLCL - 8 + tSTC2 0.5tCLCL + 4 + tSTC2 0.5tCLCL - 8 + tSTC2 0.5tCLCL + 5 + tSTC2 ns Port 0 Address Valid to RD or WR Low (Note 16) tAVRL0 (tAVWL0) 1.5tCLCL - 5 + tSTC2 tCLCL - 5 + tSTC2 ns Port 2 Address Valid to RD or WR Low (Note 16) tAVRL2 (tAVWL2) 0 + tSTC5 - 5 0.5tCLCL - 5 + tSTC5 1.5tCLCL - 5 + tSTC5 tCLCL - 5 + tSTC5 1.5tCLCL - 5 + tSTC5 ns Data Out Valid to WR Transition (Note 15) tQVWX -5 -5 -5 -5 -5 ns Data Hold After WR (Note 15) tWHQX tCLCL + tSTC2 - 10 tCLCL + tSTC2 - 10 tCLCL + tSTC2 - 10 tCLCL + tSTC2 - 10 tCLCL + tSTC2 - 10 ns RD or WR High to ALE High (Note 15) tRHLH (tWHLH) tSTC2 - 2 t STC2 + 4 t STC2 - 2 t STC2 + 4 t STC2 - 2 t STC2 + 4 t STC2 - 2 t STC2 + 4 t STC2 - 2 t STC2 + 4 ns Note: Specifications to -40°C are guaranteed by design and are not production tested. AC electrical characteristics assume 50% duty cycle for the oscillator and are not 100% tested, but are guaranteed by design.

exceed the rated speed of the device. In addition, the use of the crystal multiplier feature establishes a minimum external speed. terms “tSTC1, tSTC2, tSTC3” used in the variable timing table above are calculated through the use of the table given below. capacitance are dependent upon the frequency of the selected crystal. Figure 1. Nonpage Mode Timing

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 9 of 48 EXTERNAL CLOCK CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) PARAMETER SYMBOL MIN MAX UNITS Clock High Time t CHCX 10 ns Clock Low Time t CLCX 10 ns Clock Rise Time t CLCH 5 ns Clock Fall Time t CHCL 5 ns SERIAL PORT MODE 0 TIMING CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) (Figure 4) 33MHz VARIABLE PARAMETER SYMBOL CONDITIONS MIN MAX MIN MAX UNITS SM2 = 0 360 12t CLCL ns Clock Cycle Time t XLXL SM2 = 1 120 4t CLCL ns SM2 = 0 200 10tCLCL - 100 ns Output Data Setup to Clock Rising tQVXH SM2 = 1 40 3t CLCL - 10 ns SM2 = 0 50 2t CLCL - 10 ns Output Data Hold to Clock Rising tXHQX SM2 = 1 20 t CLCL - 100 SM2 = 0 0 0 ns Input Data Hold After Clock Rising tXHDX SM2 = 1 0 0 SM2 = 0 200 10t CLCL - 100 ns Clock Rising Edge to Input Data Valid tXHDV SM2 = 1 40 3t CLCL - 50 ns Note: SM2 is the serial port 0 mode bit 2. When serial port 0 is operating in mode 0 (SM0 = SM1 = 0), SM2 determines the number of crystal clocks in a serial port clock cycle.

Figure 4. Serial Port Timing

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 11 of 48 POWER-CYCLE TIMING CHARACTERISTICS (VCC = 4.5V to 5.5V, TO = -40°C to +85°C.) PARAMETER SYMBOL MIN TYP MAX UNITS Crystal Startup Time (Note 18) tCSU 8 ms Power-On Reset Delay (Note 19) tPOR 65,536 t CLCL Note 18: Startup time for a crystal varies with load capacitance and manufacturer. The time shown is for an 11.0592MHz crystal manufactured by Fox Electronics. Note 19: Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 pin meets the VIH2 criteria. At 33MHz, this time is 1.99ms. FLASH MEMORY PROGRAMMING CHARACTERISTICS (VCC = 4.5V to 5.5V) PARAMETER SYMBOL MIN TYP MAX UNITS Data Retention t DR 100 years Write/Erase Endurance t ENDURE 10,000 cycles Program/Time t PROG 40 /g109s Erase Time t ERASE 4 ms

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 12 of 48 PIN DESCRIPTION PIN PDIP PLCC TQFP NAME FUNCTION 40 12, 44 6, 38 V CC +5V 20 1, 22, 23, 16, 17, 28,

39 GND Logic Ground

External Reset. The RST input pin is bidirectional and contains a Schmitt Trigger to recognize external active-high reset inputs. The pin also employs an internal pulldown resistor to allow for a combination of wire-ORed external reset sources. An RC is not required for power-up, as the device provides this function internally. 19 21 15 XTAL1 18 20 14 XTAL2 Crystal Oscillators. These pins provide support for fundamental-mode parallel-resonant AT-cut crystals. XTAL1 also acts as an input if there is an external clock source in place of a crystal. XTAL2 serves as the output of the crystal amplifier. 29 32 26 PSEN Program Store Enable. This signal is commonly connected to optional external program memory as a chip enable. PSEN provides an active-low pulse and is driven high when external program memory is not being accessed. In one-cycle page mode 1, PSEN remains low for consecutive page hits. 30 33 27 ALE/PROG Address Latch Enable. This signal functions as a clock to latch the external address LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of an external 373-family transparent latch. In default mode, ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. In page mode, the ALE pulse width is altered according to the page mode selection. In traditional 8051 mode, ALE is high when using the EMI reduction mode and during a reset condition. ALE can be enabled by writing ALEON = 1 (PMR.2). Note that ALE operates independently of ALEON during external memory accesses. As an alternate mode, this pin (PROG) is used to execute the parallel program function. 39 43 37 P0.0 (AD0) 38 42 36 P0.1 (AD1) 37 41 35 P0.2 (AD2) 36 40 34 P0.3 (AD3) 35 39 33 P0.4 (AD4) 34 38 32 P0.5 (AD5) 33 37 31 P0.6 (AD6) 32 36 30 P0.7 (AD7) Port 0 (AD0–AD7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O port. As an alternate function, Port 0 can function as the multiplexed address/data bus to access off- chip memory. During the time when ALE is high, the LSB of a memory address is presented. When ALE falls to logic 0, the port transitions to a bidirectional data bus. This bus is used to read external program memory and read/write external RAM or peripherals. When used as a memory bus, the port provides weak pullups for logic 1 outputs. The reset condition of port 0 is tri-state. Pullup resistors are required only when using port 0 as an I/O port.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 13 of 48 PIN DESCRIPTION (continued) PIN PDIP PLCC TQFP NAME FUNCTION 1 2 40 P1.0 2 3 41 P1.1 3 4 42 P1.2 4 5 43 P1.3 5 6 44 P1.4 6 7 1 P1.5 7 8 2 P1.6 8 9 3 P1.7 Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for timer 2 I/O, new external interrupts, and new serial port 1. The reset condition of port 1 is with all bits at logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input state, since any external circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any port pin, the DS89C430/DS89C440/DS89C450 activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes the output high (and input) state. The alternate functions of port 1 are as follows: PORT ALTERNATE FUNCTION P1.0 T2 External I/O for Timer/Counter2 P1.1 T2EX Timer 2 Capture/Reload Trigger P1.2 RXD1 Serial Port 1 Receive P1.3 TXD1 Serial Port 1 Transmit P1.4 INT2 External Interrupt 2 (Positive Edge Detect) P1.5 INT3 External Interrupt 3 (Negative Edge Detect) P1.6 INT4 External Interrupt 4 (Positive Edge Detect) P1.7 INT5 External Interrupt 5 (Negative Edge Detect) 21 24 18 P2.0 (A8) 22 25 19 P2.1 (A9) 23 26 20 P2.2(A10) 24 27 21 P2.3(A11) 25 28 22 P2.4(A12) 26 29 23 P2.5(A13) 27 30 24 P2.6(A14) 28 31 25 P2.7(A15) Port 2 (A8–A15), I/O. Port 2 is an 8-bit, bidirectional I/O port. The reset condition of port 2 is logic high. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any port pin, the DS89C430/DS89C440/DS89C450 activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. As an alternate function, port 2 can function as the MSB of the external address bus when reading external program memory and read/write external RAM or peripherals. In page mode 1, port 2 provides both the MSB and LSB of the external address bus. In page mode 2, it provides the MSB and data. 10 11 5 P3.0 11 13 7 P3.1 12 14 8 P3.2 13 15 9 P3.3 14 16 10 P3.4 15 17 11 P3.5 16 18 12 P3.6 17 19 13 P3.7 Port 3, I/O. Port 3 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for external interrupts, serial port 0, timer 0 and 1 inputs, and RD and WR strobes. The reset condition of port 3 is with all bits at a logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any port pin, the DS89C430/DS89C440/DS89C450 activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. The alternate modes of port 3 are as follows: PORT ALTERNATE FUNCTION P3.0 RXD0 Serial Port 0 Receive P3.1 TXD0 Serial Port 0 Transmit P3.2 INT0 External Interrupt 0 P3.3 INT1 External Interrupt 1 P3.4 T0 Timer 0 External Input P3.5 T1 Timer 1 External Input P3.6 WR External Data Memory Write Strobe P3.7 RD External Data Memory Read Strobe 31 35 29 EA External Access. Allows selection of internal or external program memory. Connect to ground to force the DS89C430/DS89C440/DS89C450 to use an external memory program memory. The internal RAM is still accessible as determined by register settings. Connect to VCC to use internal flash memory.

Figure 5. Functional Diagram available parallel programmers. cycles for flexibility in selecting external memory and peripherals. mode to enable normal speed responses to interrupts.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 15 of 48 Terminology The term DS89C430 is used in the remainder of the document to refer to the DS89C430, DS89C440, and DS89C450, unless otherwise specified. Compatibility The DS89C430 is a fully static CMOS 8051-compatible microcontroller similar in functional features to the DS87C520, but it offers much higher performance. In most cases, the DS89C430 can drop into an existing socket for the 8xC51 family, immediately improving the operation. While remaining familiar to 8051 family users, the DS89C430 has many new features. In general, software written for existing 8051-based systems works without modification on the DS89C430, with the exception of critical timing routines, as the DS89C430 performs its instructions much faster for any given crystal selection. The DS89C430 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes of direct RAM plus 1kB of extra MOVX RAM. I/O ports can operate as in standard 80 51 products. Timers def ault to 12 clocks-per- cycle operation to keep their timing compatible with a legacy 8051 family systems. However, timers are individually programmable to run at the new one clock per cycle if desired. The DS89C430 provides several new hardware features, described in subsequent sections, implemented by new special-function registers (SFRs). Performance Overview Featuring a completely redesigned high-speed 8051-compatible core, the DS89C430 allows operation at a higher clock frequency. This updated core does not have the wasted memory cycles that are present in a standard 8051. A conventional 8051 generates machine cycles using the clock frequency divided by 12. The same machine cycle takes one clock in the DS89C430. Thus, the fastest instructions execute 12 times faster for the same crystal frequency (and actually 24 times faster for the INC data pointer instruction). It should be noted that this speed improvement is reduced when using external memory access modes that require more than one clock per cycle. Individual program improvement depends on the instructions used. Speed-sensitive applications would make the most use of instructions that are 12 times faster. However, the sheer number of 12-to-1 improved op codes makes dramatic speed improvements likely for any code. These architectural improvements produce instruction cycle times as low as 30ns. The dual data pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory. The new page modes allow for increased efficiency in external memory accesses. Instruction Set Summary All instructions have the same functionality as their 8051 counterparts, including their affect on bits, flags, and other status functions. However, the timing of each instruction is different, in both absolute and relative number of clocks. For absolute timing of real-time events, the duration of software loops can be calculated using information given in the Instruction Set table in the Ultra-High-Speed Flash Microcontroller User’s Guide . However, counter/timers default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at a reduced number of clocks per increment to take advantage of faster processor operation. The relative time of some instructions may be different in the new architecture. For example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS89C430, the MOVX instruction takes as little as two machine cycles or two oscillator cycles, but the “MOV direct, direct” uses three machine cycles or three oscillator cycles. While both are faster than their original counterparts, they now have different execution times. This is because the DS89C430 usually uses one machine cycle for each instruction byte and requires one cycle for execution. The user concerned with precise program timing should examine the timing of each instruction to become familiar with the changes. Special-Function Registers (SFRs) All peripherals and operations that are not explicit instructions in the DS89C430 are controlled through SFRs. The most common features basic to the architecture are mapped to the SFRs. These include the CPU registers (ACC, B, and PSW), data pointers, stack pointer, I/O ports, timer/counters, and serial ports. In many cases, an SFR controls an individual function or reports the function’s status. The SFRs reside in register locations 80h–FFh and are only accessible by direct addressing. SFRs with addresses ending in 0h or 8h are bit addressable.

feature, if selected, provides automatic incrementing or decrementing of the current DPTR. lower bytes are normally used for working registers. read. The I/O port has a latch that contains the value written by software. section of the Ultra-High-Speed Flash Microcontroller User’s Guide. Table 1. SFR Register Map

Table 1. SFR Register Map (continued) Note: Shaded bits are timed-access protected.

Table 2. SFR Reset Value

Table 2. SFR Reset Value (continued) low to serve as a chip enable or output enable when performing a code fetch from external program memory. ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory. stack, which are separated from the data memory. program/data memory. The upper 128 bytes are overlapped with the 128 bytes of SFRs in the memory map. using direct addressing. The lower 128 bytes can be accessed using direct or indirect addressing. of the working registers can be used for indirect addressing of the upper 128 bytes of scratchpad RAM. registers 20h–2Fh are bit addressable by software using Boolean operation instructions. select storage locations for program variables and for return addresses of control operations.

Figure 6. Memory Map (as shown for the DS89C430)

128 Bytes

128 Bytes SFR

address bus can address each memory area up to maximum of 64kB.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 21 of 48 Program Memory Access On-chip program memory begins at address 0000h and is contiguous through 3FFFh (16kB) on the DS89C430, through 7FFFh (32kB) on the DS89C440, and through FFFFh (64kB) on the DS89C450. Exceeding the maximum address of on-chip program memory causes the device to access off-chip memory. The maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the DS89C430 to behave like a device with less on-chip memory. This is beneficial when overlapping external memory is used. The maximum memory size is dynamically variable. Thus a portion of memory can be removed from the memory map to access off-chip memory and then be restored to access on-chip memory. In fact, all the on-chip memory can be removed from the memory map allowing the full 64kB memory space to be addressed from off-chip memory. Program memory addresses that are larger than the selected maximum are automatically fetched from outside the part through ports 0 and 2. Figure 6 shows a depiction of the memory map. The ROMSIZE register is used to select the maximum on-chip decoded address for program memory. Bits RMS2, RMS1, and RMS0 have the following effect: RMS2 RMS1 RMS0 Maximum On-Chip Program Memory Address (Size/Address) 0 0 0 0kB 0 0 1 1kB/03FFh 0 1 0 2kB/07FFh 0 1 1 4kB/0FFFh 1 0 0 8kB/1FFFh 1 0 1 16kB/3FFFh (DS89C430 default) 1 1 0 32kB/7FFFh (DS89C440 default) 1 1 1 64kB/FFFFh (DS89C450 default) The reset default condition for all devices is to their maximum on-chip program memory size. When accessing external program memory, that amount of external memory would be inaccessible. To select a smaller effective program memory size, software must alter bits RMS2–RMS0. Altering these bits requires a timed-access procedure, as explained later. Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For example, assume that a DS89C430 is executing instructions from internal program memory near the 12kB boundary (~3000h) and that the ROMSIZE register is currently configured for a 16kB internal program space. If software reconfigures the ROMSIZE r egister to 4kB (0000h–0FFFh) in the current state, the device immediately jumps to external program execution because program code from 4kB to 16kB (1000h–3FFFh) is no longer located on-chip. This could result in code misalignment and execution of an invalid instruction. The recommended method is to modify the ROMSIZE register from a location in memory that is internal (or external) both before and after the operation. In the above example, the instruction that modifies the ROMSIZE register should be located below the 4kB (1000h) boundary or above the 16kB (3FFFh) boundary so that it is unaffected by the memory modification. The same precaution should be applied if the internal program memory size is modified while executing from external program memory. For nonpage mode operations, off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. While serving as a memory bus, these pins are not I/O ports. This convention follows the standard 8051 method of expanding on-chip memory. Off-chip program memory access also occurs if the EA pin is a logic 0. EA overrides all ROMSIZE bit settings. The PSEN signal goes active (low) to serve as a chip enable or output enable when ports 0 and 2 fetch from external program memory. The RD and WR signals are used to control the external data memory device. Data memory is accessed by MOVX instructions. The MOVX@Ri instruction uses the value in the designated working register to provide the LSB of the address, while port 2 supplies the address MSB. The MOVX@DPTR instruction uses one of the two data pointers to move data over the entire 64kB external data memory space. Software selects the data pointer used by writing to the SEL bit (DPS.0). The DS89C430 also provides a user option for high-speed external memory access by reconfiguring the external memory interface into page mode operation. Note: When using the original 8051 expanded bus structure, the throughput is reduced by 75% compared with that of internal operations. This is because of the CPU being stalled for three out of four clocks, waiting for the data

stalls for external memory access, but page misses result in reduced external access performance. all interrupt vectors are located in the lower 128 bytes of the on-chip program memory. byte in the encryption array during verification. erase these bits and allow reprogramming the security level to a less restricted protection. Table 3. Flash Memory Lock Bits 1 1 1 1 No program lock. Encrypted verify if encryption array is programmed. program memory loader programming. 4 X X 0 Level 3 plus no external execution. application programming mode.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 23 of 48 Note: The read/write accessibility of the flash memory during in-application programming is not affected by the state of the lock bits. However, the lock bits do affect the read/write accessibility in ROM loader and parallel programming modes. In-Application Programming by User Software The DS89C430 supports in-application programming of on-chip flash memory by user software. In-application programming is initiated by writing a flash command into the flash control (FCNTL:D5h) register to enable the flash memory for erase/program/verify operations. Address and data are input into the MMU through the flash data (FDATA:D6h) register. The flash command also enables read/write accesses to the FDATA. The MMU’s sequencer provides the operation sequences and control functions to the flash memory. The MMU is designed to operate independently from the processor, except for read/write access to the SFRs. Only the upper bank of the on-chip program memory can be in-application programmed by the user software. The lower bank of the on-chip program memory contains system hardware-dependent codes that are crucial to system operation and should not be altered during in-application programming. All flash operations are self-timed. The user software can monitor the progress of an erase or programming operation through the flash busy (FBUSY;FCNTL.7) bit with a reset value at logic 1. A selected operation automatically starts when required data is written to the FDATA SFR. The MMU clears the FBUSY bit to indicate the start of a write/erase operation. The FBUSY bit may not change state for up to 1 /g109s after the operation is requested. During this time, the application should poll the status of the FBUSY bit waiting for it to change state. This bit is held low until either the end of the operation or until an error indicator is returned. A flash operating failure terminates the current operation and sets the flash error flag (FERR;FCNTL.6) to logic 1. Both the busy and error flags are read-only bits. Read/write access during in-application programming is not affected by the state of the lock bits. A sample programming sequence for a "w rite upper program memory bank " is shown below. The command must be reentered each time an operation is requested, i.e., it is not permissible to issue the “write upper program memory bank” command once and then repeatedly load address and data values to program a block of memory. 1. Make sure the FBUSY bit is 1 to indicate flash MMU is idle. 2. Write 0Bh to the FCNTL register using the timed access sequence. 3. Write address_MSB to the FDATA register. 4. Write address_LSB to the FDATA register. 5. Write data_value to the FDATA register. 6. Make sure the FBUSY bit is 0 to indicate programming has started. 7. Wait for FBUSY bit to return to 1 to indicate end of programming operation. 8. Make sure FERR is 0 to indicate no programming error. The flash command (FC3–FC0;FCNTL.3:0) bits provide flash commands as listed in Table 4

Table 4. In-Application Programming Commands

0000 Read Mode

in the read mode (0000b) state.

0001 Verify Option Control Register

value of the watchdog POR default setting.

0010 Verify Security Block

0011 Verify Upper Program

0100 Reserved for Future Use This command should not be modified by user programs. 1000 Reserved for Future Use This command should not be modified by user programs. the data byte represents the watchdog POR default setting.

1010 Write Security Block

1011 Write Upper Program

1100 Erase Option Control Register

1101 Erase Security Block

1110 Erase Upper Program

memory location are returned to FFh. 1111 System Reset This command is used to cause a system reset. and error flags have no function in normal flash-read mode. program operation is interrupted by a reset.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 25 of 48 ROM Loader The full on-chip flash program memory space, security flash block, and external SRAM can be programmed in- system from an external source through serial port 0 under the control of a built-in ROM loader. The ROM loader also has an auto-baud feature that determines which baud-rate frequencies are being used for communication and sets the baud-rate generator for that speed. When the DS89C430 is powered up and has entered its user operating mode, the ROM loader mode can be invoked at any time by forcing RST = 1, EA = 0, and PSEN = 0. It remains in effect until power-down or when the condition (RST = 1 and PSEN = EA = 0) is removed. Entering the ROM loader mode forces the processor to start fetching from the 2kB internal ROM for program memory initialization and other loader functions. The read/write accessibility is determined by the state of the lock bits, which can be verified directly by the ROM loader. The flash memory can be programmed (by the built-in ROM loader) using commands that are received over the serial interface from a host PC. Full details of the ROM loader commands are given in the Ultra-High-Speed Flash Microcontroller User’s Guide. Host software to communicate with the ROM loader is available in Windows® format as well as other platforms. Contact our technical support department at micro.support@dalsemi.com for more information. Parallel Programming Mode The microcontroller also supports a programming mode such as that used by commercial device programmers. This mode is of little utility in normal applications and is only used by commercial device programmers. For information on this mode, contact our technical support department at micro.support@dalsemi.com Data Pointer Increment/Decrement and Options The DS89C430 incorporates a hardware feature to assist applications that require data pointer increment/ decrement. Data pointer increment/decrement bits ID0 and ID1 (DPS.6 and DPS.7) define how the INC DPTR instruction functions in relation to the active DPTR (selected by the SEL bit). Setting ID0 = 1 and SEL = 0 enables the decrement operation for DPTR, and execution of the INC DPTR instruction decrements the DPTR contents by 1. Similarly, setting ID1 = 1 and SEL = 1 enables the decrement operation for DPTR1, and execution of the INC DPTR instruction decrements the DPTR1 contents by 1. With this feature, the user can configure the data pointers to operate in four ways for the INC DPTR instruction: ID1 ID0 SEL = 0 SEL = 1 0 0 INC DPTR INC DPTR1 0 1 DEC DPTR INC DPTR1 1 0 INC DPTR DEC DPTR1 1 1 DEC DPTR DEC DPTR1 SEL (DPS.0) bit always selects the active data pointer. The DS89C430 offers a programmable option that allows any instructions related to data pointer to toggle the SEL bit automatically. This option is enabled by setting the toggle-select-enable bit (TSL–DPS.5) to a logic 1. Once enabled, the SEL bit is automatically toggled after the execution of one of the following five DPTR-related instructions: INC DPTR MOV DPTR #data16 MOVC A, @A+DPTR MOVX A, @DPTR MOVX @DPTR, A The DS89C430 also offers a programmable option that automatically increases (or decreases) the contents of the selected data pointer by 1 after the execution of a DPTR-related instruction. The actual function (increment or decrement) is dependent on the setting of the ID1 and ID0 bits. This option is enabled by setting the automatic increment/decrement enable (AID–DPS.4) to a logic 1 and is affected by the following three instructions: MOVC A, @A+DPTR MOVX A, @DPTR MOVX @DPTR, A Windows is a registered trademark of Microsoft Corporation.

memory cycle contains four system clocks for nonpage mode operation. of the number of oscillator clocks. A stretch machine cycle always contains four system clocks. Table 5. Data Memory Cycle Stretch Values the system clock is in divide-by-1 mode (CD1:CD0 = 10b).

configuration of P0 and P2 for the purposes of address output and data I/O during external memory cycles. PSEN are altered to support this mode of operation. register requires a timed access. Table 6. Page Mode Select P2: The upper address byte is multiplexed with the data byte. impedance state for external reads from data memory and driven with data during external writes to data memory. address. The external memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss. address. The external memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit. external address latches. PSEN, RD, and WR strobes accordingly for the appropriate operation on the P0 data bus. There is no ALE assertion for page hits.

Figure 10. Page Mode 1, External Memory Cycle (CD1:CD0 = 10) the appropriate operation takes place.

Table 7. Page Mode 1, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 00) Table 8. Page Mode 1, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 01) Table 9. Page Mode 1, Data Memory Cycle Stretch Values (PAGES1:PAGES0 = 10)

Figure 12. Page Mode 1, External Data Memory Access

Figure 13. Page Mode 1, External Data Memory Access the individual interrupt-enable settings. The power-fail interrupt is controlled by its individual enable only. supports five levels of interrupt priorities instead of the original two.

Table 11. Interrupt Summary is level triggered, the flag follows the state of the pin. Note 2: The flag is cleared automatically by hardware when the service routine is vectored to.

summarizes the timer functions. corresponding T0/T1 pin for 1-to-0 transitions. The timer mode (TMOD) register controls the mode of operation. Each timer consists of a 16-bit register in 2 bytes, which can be found in the SFR map as TL0, TH0, TL1, and TH1. The timer control (TCON) register enables timers 0 and 1. Table 12. Timer Functions *8-bit timer/counter includes autoreload feature. 2x8-bit mode does not. at divide by 2, regardless of the setting of its timer mode bits. TL2 and TH2) is enabled by the T2CON register. Its mode of operation is selected by the T2MOD register.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 38 of 48 during the three machine cycles following the writing of the 55h. Writing to a timed-access-protected bit outside of these three machine cycles has no effect on the bit. The timed-access process is address, data, and time dependent. A processor running out of control and not executing system software statistically is not able to perform this timed sequence of steps, and as such, does not accidentally alter the protected bits. It should be noted that this method should be used in the main body of the system software and never used in an interrupt routine in conjunction with the watchdog reset. Interrupt routines using the timed-access watchdog-reset bit (RWT) can recover a lost system and allow the resetting of the watchdog, but the system returns to a lost condition once the RETI is executed, unless the stack is modified. Also, it is advisable that interrupts be disabled (EA = 0) when executing the timed-access sequence, since an interrupt during the sequence adds time, making the timed-access attempt fail. Power Management and Clock-Divide Control Power-management features are available that monitor the power-supply voltage levels and support low-power operation with three power-saving modes. Such features include a bandgap voltage monitor, watchdog timer, selectable internal ring oscillator, and programmable system clock speed. The SFRs that provide control and application software access are the watchdog control (WDCON, D8h), extended interrupt enable (EIE, E8h), extended interrupt flag (EXIF, 91h) and power control (PCON, 87h) registers. System Clock-Divide Control The programmable clock-divide control bits (CD1 and CD0) provide the processor with the ability to adapt to different crystals and to slow the system clocks, providing lower power operation when required. An on-chip crystal multiplier allows the DS89C430 to operate at two or four times the crystal frequency by setting the 4X/ 2X bit, and is enabled by setting the CTM bit to a logic 1. An additional ci rcuit provides a clock source at divide by 1024. When used with a 7.372MHz crystal, for example, the processor executes the machine cycle in times ranging from 33.9ns (mulitply-by-4 mode) to 138.9/g109s (divide-by-1024 mode) and maintains a highly accurate serial port baud rate, while allowing the use of more cost-effective lower frequency crystals. Although the clock-divide control bits can be written at any time, certain hardware features enhance the use of these clock controls to guarantee proper serial port operation and to allow for a high-speed response to an external interrupt. The 01b setting of CD1 and CD0 is reserved. It has the same effect as the setting of 10b, which forces the system clock into a divide-by-1 mode. The DS89C430 defaults to divide-by-1 clock mode on all forms of reset. When in divide-by-1024 mode, in order to allow a quick response to incoming data on a serial port, the system uses the switchback mode to automatically revert to divide-by-1 mode whenever a start bit is detected. This automatic switchback is only enabled in divide-by-1024 mode when the switchback bit (PMR.5:SWB) is set. All other clock modes are unaffected by interrupts and serial port activity. The oscillator multiply ratios of 4, 2, and 1 are also used to provide standard baud-rate generation for the serial ports through a forced divide-by-12 input clock (TxMH,TxM = 00b, x = 1, 2, or 3) to the timers. Use of the multiply-by-4 or multiply-by-2 options through the clock-divide control bits requires that the crystal multiplier be enabled and the specific system-clock-multiply value be established by the 4X/ 2X bit in the PMR register. The multiplier is enabled through the CTM (PMR.4) bit but cannot be automatically selected until a startup delay has been established through the CKRY bit in the status register. The 4X/ 2X bit can only be altered when the CTM bit is cleared to a logic 0. This prevents the system from changing the multiplier until the system has moved back to the divide-by-1 mode and the multiplier has been disabled by the CTM bit. The CTM bit can only be altered when the CD1 and CD0 bits are set to divide-by-1 mode and the RGMD bit is cleared to 0. Setting the CTM to a logic 1 from a previous logic 0 automatically clears the CKRY bit in the status register and starts the multiplier startup timeout in the multiplier startup counter. During the multiplier startup period, the CKRY bit remains cleared and the CD1 and CD0 clock controls cannot be set to 00b. The CTM bit is cleared to a logic 0 on all resets. Note that the rated maximum speed of operation applies to the speed of the microcontroller core, not the external clock source. When using the clock multiplier feature, the external clock source frequency, multiplied by the clock multiplier (2X or 4X) can never be faster than the maximum rated speed of the device. Thus, if a designer wished to use the 4X clock multiplier on a device rated at 33MHz, the maximum external clock speed would be 8.25MHz. Figure 14 gives a simplified description of the generation of the system clocks. Specifics of hardware restrictions associated with the use of the 4X/2X CTM, CKRY, CD1, and CD0 bits are outlined in the SFR section.

Figure 14. System Clock Sources The power monitor in the DS89C430 monitors the V CC pin in relation to the on-chip bandgap voltage reference. although in a mode that reduces their power consumption.

(CD1:0) and crystal multiplier settings. Table 13. Watchdog Timeout Value (In Number of Oscillator Clocks) interrupt can be programmed to allow a system to wake up periodically to sample the external world. the reset is removed, the RST pin is driven low, and operation begins from address 0000h.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 41 of 48 External/Hardware Reset A hardware reset can be initiated by asserting the RST pin high for at least three external clock cycles while the external clock is running. The reset is asserted immediately. When the RST pin is taken to a logic low, the microcontroller exits the reset state within a delay that depends on the state of the flash memory at the time the reset was asserted. If a flash write or erase operation was in progress, the reset state is a 4ms maximum. If no flash write or erase operations were in progress, there is a delay of 90 external clock cycles. Operation resumes at address 0000h. If taking RST to a logic low causes the device to exit stop mode, an additional delay of 65,536 clock cycles is experienced before operation begins. Reset Output If a reset is caused by a power-fail reset, a watchdog timer reset, or an internal system reset, a logic high output- reset pulse is also generated at the bidirectional RST pin. This reset pulse is asserted as long as an internal reset is asserted. Although the microcontroller generates its own power-on delay for crystal warmup, legacy designs may employ an external RC circuit. Large values of “C” may load the pin enough that the RST output may not achieve a logic high, but the state of the external RST pin does not affect the internal reset condition. Oscillator-Fail Detect and Reset The DS89C430 incorporates an oscillator-fail-detect circuit that, when enabled, causes a reset if the crystal oscillator frequency falls below 20kHz and holds the chip in reset with the ring oscillator operating. Setting the OFDE (PCON.4) bit to logic 1 enables the circuit. The OFDE bit is only cleared from logic 1 to logic 0 by a power- fail reset or by software. A reset caused by an oscillator failure also sets the OFDF (PCON.5) to logic 1. This flag is cleared by software or power-on reset. This circuit does not force a reset when the oscillator is stopped by the software-enabled stop mode. Power-Management Mode The power-management mode offers a software-controllable power-saving scheme by providing a reduced instruction cycle speed, which allows the microcontroller to continue operating while using an internally divided version of the clock source to save power. Power-management mode is invoked by software setting the clock- divide control bits CD1 and CD0 (PMR.7–6) bits to 11b, which sets an operating rate of 1024 oscillator cycles for one machine cycle. On all forms of reset, the clock-divide control bits default to 10b, which selects one oscillator cycle per machine cycle. Since the clock speed choice affects all functional logic, including timers, several hardware switchback features allow the clock speed to automatically return to the divide-by-1 mode from a reduced cycle rate. Setting the SWB (PMR.5) bit to 1 in software enables this switchback function. When CD1 and CD0 are programmed to the divide-by-1024 mode and the SWB bit is also enabled, the system forces the clock-divide control bits to automatically reset to the divide-by-1 mode whenever the system detects an externally enabled (and allowed by nesting priorities) interrupt. The switchback occurs whenever one of the two following conditions occurs. The first switchback condition is initiated by the detection of a low on either INT0, INT1, INT3, or INT5 or a high on INT2 or INT4 when the respective pin has been programmed and allowed (by nesting priorities) to issue an interrupt. The second switchback condition occurs when either serial port is enabled to receive data and is found to have an active-low transition on the respective receive-input pin. Serial port transmit activity also forces a switchback if the SWB is set. Note that the serial port activity, as related to the switchback, is independent of the serial port interrupt relationship. Any attempt to change the clock divider to the divide-by-1024 mode while the serial port is either transmitting or receiving has no effect, leaving the clock control in the divide-by- 1 mode. Note also that the switchback interrupt relationship requires that the respective external interrupt source is allowed to actually generate an interrupt, as defined by the priority of the interrupt and the state of the nested interrupts, before the switchback can actually occur. An interrupt by the serial port is not required, nor is the setting of serial port enable. Disabling external interrupts and serial port receive/transmission mode disables the automatic switchback mode. Clearing the SWB bit also disables the switchback, and all interrupt and serial port controls of the clock divider are disabled. All other clock modes ignore the switchback relationship and are unaffected by interrupts and serial port activity. The basic divide-by-12 mode for the timers (TxMH, TxM = 00b) as well as the divide by 32 and 64 for mode 2 on the serial ports has been maintained when running the processor with the oscillator divide ratio of 0.25, 0.5, and 1.

summarizes the effect of clock mode on timer operation. CD1 and CD0 to verify write was allowed) before proceeding with low-power program functions. Table 14. Effect of Clock Mode on Timer Operation (In Number of Oscillator Clocks) oscillator does not drive it.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 43 of 48 Stop Mode Stop mode disables all circuits within the processor. All on-chip clocks, timers, and serial port communication are stopped, and no processing is possible. Stop mode is invoked by setting the stop bit (PCON.1) to logic 1. The processor enters stop mode on the instruction that sets the bit. The processor can exit stop mode by using any of the six external interrupts that are enabled. An external reset through the RST pin unconditionally exits the processor from stop mode. If the BGS bit is set to logic 1, the bandgap provides a reset while in stop mode if V CC should drop below the V RST level. If BGS is 0, no reset is generated if VCC drops below VRST. When the stop mode is removed, the processor waits for 65,536 clock cycles for the internal flash memory to warm up before starting normal execution. Also, the processor waits for the crystal warmup period if it is not using the ring oscillator. Serial I/O The microcontroller provides a serial port (UART) that is identical to the 80C52. In addition, it includes a second hardware serial port that is a full duplicate of the standard one. This port optionally uses pins P1.2 (RXD1) and P1.3 (TXD1) and has duplicate control functions included in new SFR locations. Both ports can operate simultaneously but can be at different baud rates or modes. The second serial port has similar control registers (SCON1 at C0h, SBUF1 at C1h) to the original. The new serial port can only use timer 1 for timer-generated baud rates. Control for serial port 0 is provided by the SCON0 register, while its I/O buffer is SBUF0. The registers SCON1 and SBUF1 provide the same functions for the second serial port. A full description of the use and operation of both serial ports can be found in the Ultra-High-Speed Flash Microcontroller User’s Guide. Instruction Set All instructions are 100% binary compatible with the industry-standard 8051, and are only different in the number of machine cycles used for the instructions. There are some special conditions and features to be considered when analyzing the DS89C430 instruction set. Full details are available in the Ultra-High-Speed Flash Microcontroller User’s Guide.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 44 of 48 SELECTOR GUIDE PART TEMP RANGE FLASH MEMORY SIZE MAX CLOCK SPEED (MHz) PIN-PACKAGE DS89C430-MNL -40°C to +85°C 16kB x 8 33 40 PDIP DS89C430-MNL+ -40°C to +85°C 16kB x 8 33 40 PDIP DS89C430-QNL -40°C to +85°C 16kB x 8 33 44 PLCC DS89C430-QNL+ -40°C to +85°C 16kB x 8 33 44 PLCC DS89C430-ENL -40°C to +85°C 16kB x 8 33 44 TQFP DS89C430-ENL+ -40°C to +85°C 16kB x 8 33 44 TQFP DS89C430-MNG -40°C to +85°C 16kB x 8 25 40 PDIP DS89C430-MNG+ -40°C to +85°C 16kB x 8 25 40 PDIP DS89C430-QNG -40°C to +85°C 16kB x 8 25 44 PLCC DS89C430-QNG+ -40°C to +85°C 16kB x 8 25 44 PLCC DS89C430-ENG -40°C to +85°C 16kB x 8 25 44 TQFP DS89C430-ENG+ -40°C to +85°C 16kB x 8 25 44 TQFP DS89C440-MNL -40°C to +85°C 32kB x 8 33 40 PDIP DS89C440-MNL+ -40°C to +85°C 32kB x 8 33 40 PDIP DS89C440-QNL -40°C to +85°C 32kB x 8 33 44 PLCC DS89C440-QNL+ -40°C to +85°C 32kB x 8 33 44 PLCC DS89C440-ENL -40°C to +85°C 32kB x 8 33 44 TQFP DS89C440-ENL+ -40°C to +85°C 32kB x 8 33 44 TQFP DS89C440-MNG -40°C to +85°C 32kB x 8 25 40 PDIP DS89C440-MNG+ -40°C to +85°C 32kB x 8 25 40 PDIP DS89C440-QNG -40°C to +85°C 32kB x 8 25 44 PLCC DS89C440-QNG+ -40°C to +85°C 32kB x 8 25 44 PLCC DS89C440-ENG -40°C to +85°C 32kB x 8 25 44 TQFP DS89C440-ENG+ -40°C to +85°C 32kB x 8 25 44 TQFP DS89C450-MNL -40°C to +85°C 64kB x 8 33 40 PDIP DS89C450-MNL+ -40°C to +85°C 64kB x 8 33 40 PDIP DS89C450-QNL -40°C to +85°C 64kB x 8 33 44 PLCC DS89C450-QNL+ -40°C to +85°C 64kB x 8 33 44 PLCC DS89C450-ENL -40°C to +85°C 64kB x 8 33 44 TQFP DS89C450-ENL+ -40°C to +85°C 64kB x 8 33 44 TQFP DS89C450-MNG -40°C to +85°C 64kB x 8 25 40 PDIP DS89C450-MNG+ -40°C to +85°C 64kB x 8 25 40 PDIP DS89C450-QNG -40°C to +85°C 64kB x 8 25 44 PLCC DS89C450-QNG+ -40°C to +85°C 64kB x 8 25 44 PLCC DS89C450-ENG -40°C to +85°C 64kB x 8 25 44 TQFP DS89C450-ENG+ -40°C to +85°C 64kB x 8 25 44 TQFP + Denotes a lead-free/RoHS-compliant device.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 45 of 48 PIN CONFIGURATIONS

REVISION HISTORY

111003 New product release. 032204 changed Units from “/g109A” to “mA.” Note 15: Changed number of external clock cyles per system clock and minimum external clock speeds. Flash Memory Programming Characteristics table: Removed Note 20 (room temperature only) from the Data Retention parameter. 060204 Changed Write/Erase Endurance parameter from 20,000 cycles to 10,000 cycles. Removed original Table 5. Parallel Programming Instruction Set, and replaced it with a paragraph introducing the subject and advising interested parties to contact the factory for more information. Clarified IAP programming sequence. 060805 Added lead-free devices to Ordering Information table. 6 1 40 18 28 7 39 17 29 DS89C430 DS89C440 DS89C450 PLCC 33 23 1 1 34 22 44 12 DS89C430 DS89C440 DS89C450 TQFP TOP VIEW ALE/PROG P1.0/T2 P1.1/T2EX P1.2/RXD1 P1.3/TXD1 P1.4/INT2 P1.5/INT3 P1.6/INT4 P1.7/INT5 RST P3.0/RXD0 P3.1/TXD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS VCC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA/VPP PSEN P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 DS89C430 DS89C440 DS89C450 PDIP

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 46 of 48

PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PKG 40-PIN PDIP DIM MIN MAX A — 0.200 A1 0.015 — A2 0.140 0.160 B 0.014 0.022 C 0.008 0.012 D 1.980 2.085 E 0.600 0.625 E1 0.530 0.555 E 0.090 0.110 L 0.115 0.145 EB 0.600 0.700 56-G5000-000 Note: Dimensions are in inches.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 47 of 48 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) NOTE 1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED. NOTE 2: CONTROLLING DIMENSION ARE IN INCHES.

DS89C430/DS89C440/DS89C450 Ultra-High-Speed Flash Microcontrollers 48 of 48 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Ma xim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specification s without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products /g183 Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)