DS83C530-ENL+

DS87C530_05 DALLAS | Alldatasheet

Document overview

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Technical content

1 of 47 REV: 071107 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.

FEATURES

ƒ 80C52 Compatible

8051 Instruction-Set Compatible

Three 16-Bit Timer/Counters

256 Bytes Scratchpad RAM

ƒ Large On-Chip Memory 16kB EPROM (OTP) 1kB Extra On-Chip SRAM for MOVX ƒ ROMSIZE Features Selects Effective On-Chip ROM Size from 0 to 16kB Allows Access to Entire External Memory Map Dynamically Adjustable by Software Useful as Boot Block for External Flash ƒ Nonvolatile Functions On-Chip Real-Time Clock with Alarm Interrupt Battery Backup Support of 1kB SRAM ƒ High-Speed Architecture

4 Clocks/Machine Cycle (8051 = 12)

Runs DC to 33MHz Clock Rates Single-Cycle Instruction in 121ns Dual Data Pointer Optional Variable Length MOVX to Access Fast/Slow RAM /Peripherals ƒ Power Management Mode Programmable Clock Source Saves Power Runs from (crystal/64) or (crystal/1024) Provides Automatic Hardware and Software Exit ƒ EMI Reduction Mode Disables ALE ƒ Two Full-Duplex Hardware Serial Ports ƒ High Integration Controller Includes: Power-Fail Reset Early-Warning Power-Fail Interrupt Programmable Watchdog Timer ƒ 14 Total Interrupt Sources with Six External PIN CONFIGURATIONS DALLAS DS87C530 DS83C530 7 1 47 21 33 PLCC, WINDOWED CLCC DALLAS DS87C530 DS83C530 39 27 1 13 2640 1452 TQFP TOP VIEW www.maxim-ic.com DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock The High-Speed Microcontroller User’s Guide must be used in conjunction with this data sheet. Download it at: www.maxim-ic.com/microcontrollers.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 2 of 47

ORDERING INFORMATION

(MHz) PIN-PACKAGE DS87C530-QCL 0°C to +70°C 33 52 PLCC DS87C530-QCL+ 0°C to +70°C 33 52 PLCC DS87C530-QNL -40°C to +85°C 33 52 PLCC DS87C530-QNL+ -40°C to +85°C 33 52 PLCC DS87C530-KCL* 0°C to +70°C 33 52 Windowed CLCC DS87C530-ECL 0°C to +70°C 33 52 TQFP DS87C530-ECL+ 0°C to +70°C 33 52 TQFP DS87C530-ENL -40°C to +85°C 33 52 TQFP DS87C530-ENL+ -40°C to +85°C 33 52 TQFP DS83C530-QCL 0°C to +70°C 33 52 PLCC DS83C530-QCL+ 0°C to +70°C 33 52 PLCC DS83C530-QNL -40°C to +85°C 33 52 PLCC DS83C530-QNL+ -40°C to +85°C 33 52 PLCC DS83C530-ECL 0°C to +70°C 33 52 TQFP DS83C530-ECL+ 0°C to +70°C 33 52 TQFP DS83C530-ENL -40°C to +85°C 33 52 TQFP DS83C530-ENL+ -40°C to +85°C 33 52 TQFP + Denotes a Pb-free/RoHS-compliant device. * The windowed ceramic LCC package is intrinsically Pb free.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 3 of 47 DETAILED DESCRIPTION The DS87C530/DS83C530 EPROM/ROM microcontrollers with a real-time clock (RTC) are 8051- compatible microcontrollers based on the Dallas Semic onductor high-speed core. They use 4 clocks per instruction cycle instead of the 12 used by the standard 8051. They also provide a unique mix of peripherals not widely available on other processors . They include an on-chip RTC and battery backup support for an on-chip 1k x 8 SRAM. The new Power Management Mode allows software to select reduced power operation while still processing. A combination of high-performance microcontro ller core, RTC, battery-backed SRAM, and power management makes the DS87C530/DS83C 530 ideal for instruments and porta ble applications. They also provide several periphera ls found on other Dallas high-speed microcontrollers. These include two independent serial ports, two data pointers, on-chip power monito r with brownout detection and a watchdog timer. Power Management Mode (PMM) allows software to select a slower CPU clock. While default operation uses four clocks per machine cycle, the PMM runs the processor at 64 or 1024 clocks per cycle. There is a corresponding drop in power consumption when the processor slows. The EMI reduction feature allows software to select a reduced emission mode. This disables the ALE signal when it is unneeded. The DS83C530 is a factory mask ROM version of the DS87C530 designed fo r high-volume, cost- sensitive applications. It is identical in all respect s to the DS87C530, except that the 16kB of EPROM is replaced by a user-supplied application program. All references to features of the DS87C530 will apply to the DS83C530, with the exception of EPROM-specific features where noted. Please contact your local Dallas Semiconductor sales representative for ordering information. Note: The DS87C530/DS83C530 are monolithic devices. A user must supply an external battery or super cap and a 32.768kHz timekeeping crystal to have permanently powered timekeeping or nonvolatile RAM. The DS87C530/DS83C530 provide all the support and switching circuitry needed to manage these resources.

Figure 1. Block Diagram 29 22 V CC2 +5V RTC Supply. VCC2 is isolated from VCC to isolate the RTC from digital noise. as the device provides this function internally. place of a crystal. XTAL2 is the output of the crystal amplifier.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 5 of 47 PIN DESCRIPTION (continued) PIN PLCC TQFP NAME FUNCTION 38 31 PSEN Program Store-Enable Output. This active-low signal is a chip enable for optional external ROM memory. PSEN provides an active-low pulse and is driven high when external ROM is not being accessed. 39 32 ALE Address Latch-Enable Output. This pin latches the external address LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of an external 373 family transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high when the device is in a Reset condition. ALE can be disabled and forced high by writing ALEOFF = 1 (PMR.2). ALE operates independently of ALEOFF during external memory accesses. 50 43 P0.0 (AD0) 49 42 P0.1 (AD1) 48 41 P0.2 (AD2) 47 40 P0.3 (AD3) 46 39 P0.4 (AD4) 45 38 P0.5 (AD5) 44 37 P0.6 (AD6) 43 36 P0.7 (AD7) Port 0 (AD0–AD7), I/O. Port 0 is an open-drain, 8-bit, bidirectional I/O port. As an alternate function Port 0 can function as the multiplexed address/data bus to access off-chip memory. During the time when ALE is high, the LSB of a memory address is presented. When ALE falls to a logic 0, the port transitions to a bidirectional data bus. This bus is used to read external ROM and read/ write external RAM memory or peripherals. When used as a memory bus, the port provides active high drivers. The reset condition of Port 0 is tri-state. Pullup resistors are required when using Port 0 as an I/O port. 3 48 P1.0 4 49 P1.1 5 50 P1.2 6 51 P1.3 7 52 P1.4 8 1 P1.5 9 2 P1.6 10 3 P1.7 Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for Timer 2 I/O, new External Interrupts, and new Serial Port 1. The reset condition of Port 1 is with all bits at a logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. When software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes the output high (and input) state. The alternate modes of Port 1 are outlined as follows. Port Alternate Function P1.0 T2 External I/O for Timer/Counter 2 P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger P1.2 RXD1 Serial Port 1 Input P1.3 TXD1 Serial Port 1 Output P1.4 INT2 External Interrupt 2 (Positive Edge Detect) P1.5 INT3 External Interrupt 3 (Negative Edge Detect) P1.6 INT4 External Interrupt 4 (Positive Edge Detect) P1.7 INT5 External Interrupt 5 (Negative Edge Detect)

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 6 of 47 PIN DESCRIPTION (continued) PIN PLCC TQFP NAME FUNCTION 30 23 P2.0 (AD8) 31 24 P2.1 (AD9) 32 25 P2.2 (AD10) 33 26 P2.3 (AD11) 34 27 P2.4 (AD12) 35 28 P2.5 (AD13) 36 29 P2.6 (AD14) 37 30 P2.7 (AD15) Port 2 (A8–A15), I/O. Port 2 is a bidirectional I/O port. The reset condition of Port 2 is logic high. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. When software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. As an alternate function Port 2 can function as MSB of the external address bus. This bus can be used to read external ROM and read/write external RAM memory or peripherals. 15 8 P3.0 16 9 P3.1 17 10 P3.2 18 11 P3.3 19 12 P3.4 20 13 P3.5 21 14 P3.6 22 15 P3.7 Port 3, I/O. Port 3 functions as both an 8-bit, bi-directional I/O port and an alternate functional interface for external interrupts, Serial Port 0, Timer 0 and 1 Inputs, and RD and WR strobes. The reset condition of Port 3 is with all bits at a logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. When software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. The alternate modes of Port 3 are outlined below. Port Alternate Function P3.0 RXD0 Serial Port 0 Input P3.1 TXD0 Serial Port 0 Output P3.2 INT0 External Interrupt 0 P3.3 INT1 External Interrupt 1 P3.4 T0 Timer 0 External Input P3.5 T1 Timer 1 External Input P3.6 WR External Data Memory Write Strobe P3.7 RD External Data Memory Read Strobe 42 35 EA External Access Input, Active Low. Connect to ground to use an external ROM. Internal RAM is still accessible as determined by register settings. Connect to VCC to use internal ROM. 51 44 V BAT VBAT Input. Connect to the power source that maintains SRAM and RTC when VCC < VBAT. Can be connected to a 3V lithium battery or a super cap. Connect to GND if battery will not be used with device. 27 20 RTCX2 28 21 RTCX1 Timekeeping Crystals. A 32.768kHz crystal between these pins supplies the time base for the RTC. The devices support both 6pF and 12.5pF load capacitance crystals as selected by an SFR bit (described later). To prevent noise from affecting the RTC, the RTCX2 and RTCX1 pins should be guard-ringed with GND2. 2, 11, 13, 14, 40, 4, 6, 7, 33, 34, N.C. Not Connected. These pins should not be connected. They are reserved for use with future devices in the family.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 7 of 47 COMPATIBILITY The DS87C530/DS83C530 are fully sta tic, CMOS 8051-compatible microc ontrollers designed for high performance. While remaining familiar to 8051 users, th e devices have many new features. In general, software written for existing 8051-based sy stems works without modification on the DS87C530/DS83C530. The exception is critical timing since the high-s peed microcontrollers perform its instructions much faster than the original for any given crystal selecti on. The DS87C530/DS83C530 run the standard 8051 instruction set. They are not pin compatible with other 8051s due to the timekeeping crystal. The DS87C530/DS83C530 provide three 16-bit timer/counters, full-dupl ex serial port (2), 256 bytes of direct RAM plus 1kB of extra MOVX RAM. I/O por ts have the same opera tion as a standard 8051 product. Timers will default to a 12 clock-per-cycle operation to keep their timing compatible with original 8051 systems. However, timers are individually programmable to run at the new 4 clocks per cycle if desired. The PCA is not supported. The DS87C530/DS83C530 provide several new hardware features implemented by new Special Function Registers. A summary of these SFRs is provided below. PERFORMANCE OVERVIEW The DS87C530/DS83C530 featur e a high-speed, 8051-compatible core. Higher speed comes not just from increasing the clock frequency, but also from a newer, more efficient design. This updated core does not have the dummy memory cycles that are present in a standard 8051. A conventional 8051 generates machine cycles using the clock frequency divided by 12. In the DS87C530/DS83C530, the same machine cy cle takes 4 clocks. Thus the fastest instruction, one machine cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions. The majority of instructions on the DS87C530/DS 83C530 will see the full 3-to-1 speed improvement. Some instructions will get between 1.5 and 2.4 to 1 improvement. All instructions are faster than the original 8051. The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of individual programs will depend on the actual instructions used. Speed-sensitive applications would make the most use of instructions that are three times faster. However, the sheer number of 3 to 1 improved opcodes makes dramatic speed impr ovements likely for any code. These architecture improvements produce a peak instruction cycle in 121ns (8.25 MIPs). The Dual Data Pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory. INSTRUCTION SET SUMMARY All instructions perform the same functions as thei r 8051 counterparts. Their ef fect on bits, flags, and other status functions is identical. However, the timing of each instruction is different. This applies both in absolute and relative number of clocks. For absolute timing of real-time events, the timing of software loops can be calculated using a table in the High-Speed Microcontroller User’s Guide . However, counter/timers default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at 4 clocks pe r increment to take advant age of faster processor operation.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 8 of 47 The relative time of two instructions might be different in the new architecture than it was previously. For example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS87C530/DS83C530, the MOVX instruction ta kes as little as two machine cycles or eight oscillator cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have differ ent execution times. This is because the DS87C530/DS83C530 usually use one instruction cycle for each instruction byte. The user concerned with precise program timing should examine the timin g of each instruction for familiarity with the changes. Note that a machine cycle now requires ju st 4 clocks, and provides one ALE pulse per cycle. Many instructions require only one cycle, but some requi re five. In the original architecture, all were one or two cycles except for MUL and DIV. Refer to the High-Speed Microcontroller User’s Guide for details and individual instruction timing. SPECIAL FUNCTION REGISTERS Special Function Registers (SFRs) control most special features of th e DS87C530/DS83C530. This allows the device to incorporate new features but remain instruction-set compatible with the 8051. EQUATE statements can be used to define the new SFR to an assembler or compiler. All SFRs contained in the standard 80C52 are duplicated in this device. Table 1 shows the register addresses and bit locations. The High-Speed Microcontroller User’s Guide describes all SFRs.

Table 1. Special Function Register Locations

• Functions not present in the 80C52 are in bold.

Table 1. Special Function Register Locations (continued)

• Functions not present in the 80C52 are in bold.

functions and controls. The user must supply a backup source and a 32.768kHz timekeeping crystal. write) seconds, minutes, hours, day of the week, and date. Figure 2 shows the clock organization. time of day, including subseconds, in only four regist ers. The calendar stores its data in binary form. number allows a total range of 179 years beginning from 0000.

interrupts with no match will generate an interrupt 256 times per second. Software enables the timekeeper oscillator using the RTC enable bit in the RTC Control register (F9h). unneeded. Values in the RTC Control register are maintained by the backup source through power failure. Figure 2. Real-Time Clock affected by this circuit and are volatile. energy source are needed. The following describes guidelines for choosing these devices.

6pF crystal. This bit will be nonvola tile so these choices will remain while the backup source is present. A guard ring (connected to the RTC ground) should encircle the RTCX1 and RTCX2 pins. requires an external resistor and diode to supply charge. specified in the electrical specifications. The circuit loads the VBAT only when VCC has fallen below VBAT. time without power. A very small lithium cell provides a lifetime of more than 10 years. Figure 3. Internal Backup Circuit DS87C530/DS83C530 against these conditions.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 13 of 47 space SRAM is read/write accessible and is memory mapped. This on-chip SRAM is reached by the MOVX instruction. It is not used for executable memo ry. The scratchpad area is 256 bytes of register mapped RAM and is identical to the RAM found on the 80C52. There is no conflict or overlap among the 256 bytes and the 1kB as they use different addressing modes and separate instructions. OPERATIONAL CONSIDERATION The erasure window of the windowed LCC should be covered without regard to the programmed/unprogrammed state of the EPROM. Othe rwise, the device may not meet the AC and DC parameters listed in the data sheet. PROGRAM MEMORY ACCESS On-chip ROM begins at address 0000h and is c ontiguous through 3FFFh (16kB). Exceeding the maximum address of on -chip ROM will cause the DS87C530/DS 83C530 to access off-chip memory. However, the maximum on-chip decode d address is selectable by software using the ROMSIZE feature. Software can cause the microcontroller to behave like a device with less on-chip memory. This is beneficial when overlapping external memory, such as Flash, is used. The maximum memory size is dynamically variable. Thus a portion of memory can be removed from the memory map to access off-chip memory, then restored to access on-chip memory. In fact, all the on-chip memory can be removed from the memory map allowi ng the full 64kB memory space to be addressed from off-chip memory. ROM addresses that are larger than the selected maximum are automatically fetched from outside the part via Ports 0 and 2. Figure 4 shows a depiction of the ROM memory map. The ROMSIZE register is used to select the maximum on-chip decoded address for ROM. Bits RMS2, RMS1, RMS0 have the following effect: RMS2 RMS1 RMS0 MAXIMUM ON-CHIP ROM ADDRESS 0 0 0 0kB 0 0 1 1kB 0 1 0 2kB 0 1 1 4kB 1 0 0 8kB 1 0 1 16kB (default) 1 1 0 Invalid—reserved 1 1 1 Invalid—reserved The reset default condition is a ma ximum on-chip ROM address of 16kB . Thus no action is required if this feature is not used. When acce ssing external program memory, the first 16kB would be inaccessible. To select a smaller effective ROM size, software must alter bits RMS2–RMS0. Altering these bits requires a timed-access procedure. Care should be taken so that changing the ROMS IZE register does not corrupt program execution. For example, assume that a device is executing instructions from internal program memory near the 12kB boundary (~3000h) and that the ROMSIZE register is currently configured for a 16kB internal program space. If software reconfigures the ROMSIZE regist er to 4kB (0000h–0FFFh) in the current state, the

internal program memory size is modified while executing from external program memory. Off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. when Ports 0 and 2 fetch from external ROM. Figure 4. ROM Memory Map area as though it was located off-chip. The 1kB of SRAM is between address 0000h and 03FFh. addresses for other hardware and still have full compatibility.

reach off-chip devices at the same addresses. Th e control bits are DME1 (PMR.1) and DME0 (PMR.0). Table 2. Data Memory Access Control running if desired. The bits are read-only. peripherals such as LCDs or UARTs that are slow. The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below. change this value depending on the particular memory or peripheral. On reset, the Stretch value will de fault to a 1, resulting in a three-cycle MOVX for any external access. only way to slow program memory (ROM) access is to use a slower crystal.

related timing. Also, setup and hold times are increased by 1 clock when using any Stretch greater than 0. Table 3. Data Memory Cycle Stretch Values DS87C530/DS83C530, the standard data pointer is called DPTR, located at SFR addresses 82h and 83h. register locations are as follows.

feature several enhancements to Stop mode that make it more useful. below). The speeds are (Clock/64) and (Clock/1024). PMM 1 eliminates most of the power consumption while still allowing a reasonable speed of processing. use Idle mode in new designs. Table 4. Machine Cycle Rate Table 5. Typical Operating Current in PMM

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 18 of 47 CRYSTAL-LESS PMM A major component of power consumption in PMM is the crystal amplifier circuit. The DS87C530/DS83C530 allow the user to sw itch CPU operation to an internal ring oscillator and turn off the crystal amplifier. The CPU would then have a clock source of approximately 2MHz to 4MHz, divided by either 4, 64, or 1024. The ring is not accurate, so software cannot perform precision timing. However, this mode allows an additional saving of betw een 0.5mA and 6.0mA, depending on the actual crystal frequency. While this saving is of little use when r unning at 4 clocks per instruction cycle, it makes a major contribution when running in PMM1 or PMM2. PMM OPERATION Software invokes the PMM by setting the appropriate b its in the SFR area. The basic choices are divider speed and clock source. There are three speeds (4, 64, and 1024) and two clock sources (crystal, ring). Both the decisions and the controls are separate. Software will typically select the clock speed first. Then, it will perform the switch to ring operation if desired. Lastly, software can disable the crystal amplifier if desired. There are two ways of exiting PMM. Software can remove the condition by reversing the procedure that invoked PMM or hardware can (opti onally) remove it. To resume ope ration at a divide-by-4 rate under software control, simply select 4 clocks per cycle, and then crysta l-based operation if relevant. When disabling the crystal as the time base in favor of the ring oscillator, there are timing restrictions associated with restarting the crystal operation. Details are described below. There are three registers containing bits that are concerned with PMM functions. They are Power Management Register (PMR; C4h), Status (STATUS; C5h), and External Interrupt Flag (EXIF; 91h) Clock Divider Software can select the instruction cycle rate by selecting bits CD1 (PMR .7) and CD0 (PMR.6) as follows: CD1 CD0 CYCLE RATE 0 0 Reserved 0 1 4 clocks (default) 1 0 64 clocks 1 1 1024 clocks The selection of instruction cycle rate will take effect after a delay of one instruction cycle. Note that the clock divider choice applies to all functions including timers. Since baud rates are altered, it will be difficult to conduct serial communication while in P MM. There are minor restrictions on accessing the clock selection bits. The processor mu st be running in a 4-clock state to select either 64 (PMM1) or 1024 (PMM2) clocks. This means software cannot go directly from PMM1 to PMM2 or visa versa. It must return to a 4-clock rate first.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 19 of 47 Switchback To return to a 4-clock rate from PMM, software can simply select the CD1 and CD0 clock control bits to the 4 clocks per cycle state. Ho wever, the DS87C530/DS83C530 provide several hardware alternatives for automatic Switchback. If Switchback is enabled, then the device will automatically return to a 4-clock per cycle speed when an interrupt occurs from an en abled, valid external interrupt source. A Switchback will also occur when a UART detects th e beginning of a serial start bit if the serial receiver is enabled (REN = 1). Note the beginning of a start bit does not ge nerate an interrupt; this occurs on reception of a complete serial word. The automatic Switchback on detection of a start bit allows hardware to correct baud rates in time for a proper serial reception. A Switchback will also occur when a byte is written to the SBUF0 or SBUF1 for transmission. Switchback is enabled by setting the SWB bit (PMR.5) to a 1 in software. For an external interrupt, Switchback will occur only if the interrupt source could really generate the interrupt. For example, if INT0 is enabled but has a low priority setting, then Switchback will not occur on INT0 if the CPU is servicing a high priority interrupt. Status Information in the Status register assists decisions about switching in to PMM. This register contains information about the level of active interrupts and the activity on the serial ports. The DS87C530/DS83C530 support three leve ls of interrupt priority. Thes e levels are Power-fail, High, and Low. Bits STATUS.7–5 indicate the service status of each level. If PIP (Power-fail Interrupt Priority; STATUS. 7) is 1, then the processor is servicing th is level. If either HIP (High Interrupt Priority; STATUS.6) or LIP (Low Interrupt Priority; STATUS .5) is high, then the corresponding level is in service. Software should not rely on a lower priority level interrupt source to remove PMM (Switchback) when a higher level is in service. Check the current priority service level before entering PMM. If the current service level locks out a desired Switchback source, then it would be advisable to wait until this condition clears before entering PMM. Alternately, software can prevent an undesired exit from PMM by entering a low priority interrupt service level before entering PMM. This will prevent other low priority interrupts from causing a Switchback. Status also contains information a bout the state of the serial ports. Serial Port Zero Receive Activity (SPRA0; STATUS.0) indicates a serial word is being received on Serial Port 0 when this bit is set to a 1. Serial Port 0 Transmit Activity (SPTA0; STATUS.1) indicates that the serial port is still shifting out a serial transmission. STATUS.2 and STATUS.3 provide the same information for Serial Port 1, respectively. These bits should be interrogated before entering PMM1 or PMM2 to ensure that no serial port operations are in progress. Changing the clock di visor rate during a serial transmission or reception will corrupt the operation.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 20 of 47 Crystal/Ring Operation The DS87C530/DS83C530 allow software to choose the clock source as an independent selection from the instruction cycle rate. The us er can select crystal-based or ring oscillator-based operation under software control. Power-on reset default is the crystal (or external clock) source. The ring may save power depending on the actual crystal speed. To save still more power, software can then disable the crystal amplifier. This process requires two steps. Reversing the process also requires two steps. The XT/ RG bit (EXIF.3) selects the crystal or ring as the clock source. Setting XT/ RG = 1 selects the crystal. Setting XT/ RG = 0 selects the ring. The RGMD (EXIF.2) bit serves as a status bit by indicating the active clock source. RGMD = 0 indicates the CPU is running from the crystal. RGMD = 1 indicates it is running from the ring. When operating from th e ring, disable the crystal amplifier by setting the XTOFF bit (PMR.3) to a 1. This can only be done when XT/ RG = 0. When changing the clock source, the selection will take effect after a one-instruction-cycle delay. This applies to changes from crystal to ring and vise versa. However, this assumes that the crystal amplifier is running. In most cases, when the ring is active, software previously disabled the crystal to save power. If ring operation is being used and the system must sw itch to crystal operation, the crystal must first be enabled. Set the XTOFF bit to 0. At this time, the crystal oscillation will begin. The DS87C530/DS83C530 then provi de a warm-up delay to make certa in that the frequency is stable. Hardware will set the XTUP bit (STATUS.4) to 1 when the crystal is ready for use. Then software should write XT/ RG to 1 to begin operating from the crystal. Hardware prevents writing XT/ RG to 1 before XTUP = 1. The delay between XTOFF = 0 and XTUP = 1 will be 65,536 crystal clocks in addition to the crystal cycle startup time. Switchback has no affect on the clock source. If softwa re selects a reduced clock divider and enables the ring, a Switchback will only restore the divider speed. The ring will remain as the time base until altered by software. If there is serial activity, Switchback us ually occurs with enough time to create proper baud rates. This is not true if the cr ystal is off and the CPU is running from the ring. If sending a serial character that wakes the system from crystal-less PMM, then it should be a dummy character of no importance with a subsequent delay for crystal startup. Table 6 is a summary of the bits relating to PMM and its operation. The flow chart below illustrates a typical decision set associated with PMM.

Table 6. PMM Control and Status Bit Summary clock; XT/ RG =0, runs from internal ring oscillator.

Figure 5. Invoking and Clearing PMM

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 23 of 47 IDLE MODE Setting the lsb of the Power Control register (PCON; 87h) invokes the Idle mode. Idle will leave internal clocks, serial ports and timers running. Power consum ption drops because the CPU is not active. Since clocks are running, the Idle power consumption is a function of crystal frequency. It should be approximately one-half the operational power at a given frequency. The CPU can exit the Idle state with any interrupt or a reset. Idle is available for backward software compatibility. The system can now reduce power consumption to below Idle levels by using PMM1 or PMM2 and running NOPs. STOP MODE ENHANCEMENTS Setting bit 1 of the Power Control register (PCON; 87h) invokes the Stop mode. Stop mode is the lowest power state since it turns off all internal clocking. The ICC of a standard Stop mode is approximately 1 /g109A but is specified in the Electrical Specifications. The CPU will exit Stop mode from an external interrupt or a reset condition. Internally generated interrupts (timer, serial port, watchdog) are not useful since they require clocking activity. One exception is that a RTC interrupt can cause the device to exit Stop mode. This provides a very power efficient way of performing infrequent yet periodic tasks. The DS87C530/DS83C530 provide two enhancements to the Stop mode. As documented below, the device provides a bandgap reference to determine Powe r-fail Interrupt and Reset thresholds. The default state is that the bandgap reference is off while in Stop mode. This allows the extremely low-power state mentioned above. A user can optiona lly choose to have the bandgap enabled during Stop mode. With the bandgap reference enabled, PFI and Power-fail Reset are f unctional and are a valid means for leaving Stop mode. This allows software to detect and comp ensate for a brownout or power supply sag, even when in Stop mode. In Stop mode with the bandgap enabled, I CC will be approximately 50 /g109A compared with 1 /g109A with the bandgap off. If a user does not require a Power-fail Reset or Interrupt while in Stop mode, the bandgap can remain disabled. Only the most power sensitive applications should turn off the bandgap, as this results in an uncontrolled power-down condition. The control of the bandgap reference is located in the Extended Interrupt Flag register (EXIF; 91h). Setting BGS (EXIF.0) to a 1 will keep the bandgap re ference enabled during Stop mode. The default or reset condition is with the bit at a logic 0. This results in the bandgap being off during Stop mode. Note that this bit has no control of the reference during full power, PMM, or Idle modes. The second feature allows an additional power saving option while also making Stop easier to use. This is the ability to start instantly when exiting Stop mode. It is the internal ring oscillator that provides this feature. This ring can be a clock source when exitin g Stop mode in response to an interrupt. The benefit of the ring oscillator is as follows. Using Stop mode turns off the crystal oscillator and all internal clocks to save power. This requires that the oscillator be restarted when exiting Stop mode. Actual startup time is crystal-dependent, but is normally at least 4ms. A common recommendation is 10m s. In an application that will wake up, perform a short operation, then return to sleep, the crystal startup can be longer than the real transaction. However, the ring oscillator will start instantly. Running from th e ring, the user can perform a simple operation and return to sleep before the crystal has even started. If a user selects the ring to provide the startup clock and the processor remains running, hardware will automatically switch to the crystal once a power-on reset interval (65,536 clocks) has expired. Hardware uses this value to assure proper crystal start even though power is not being cycled.

is to exit Stop mode without using the ring oscillator. communication or precision timing while this bit is set, since the operating frequency is not precise. Figure 6. Ring Oscillator Exit from Stop Mode NOTE: DIAGRAM ASSUMES THAT THE OPERATION FOLLOWING STOP REQUIRES LESS THAN 18ms TO COMPLETE.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 25 of 47 PERIPHERAL OVERVIEW The DS87C530/DS83C530 provide several of the most commonly needed peripheral functions in microcomputer-based systems. These new functions include a second serial port, power-fail reset, Power- fail interrupt, and a programmable watchdog timer. These are described below, and more details are available in the High-Speed Microcontroller User’s Guide. SERIAL PORTS The DS87C530/DS83C530 provide a serial port (UART) that is identical to the 80C52. In addition it includes a second hardware serial port that is a full duplicate of the standard one. This port optionally uses pins P1.2 (RXD1) and P1.3 (T XD1). It has duplicate control functions included in new SFR locations. Both ports can operate simultaneously but can be at different baud rates or even in different modes. The second serial port has similar control registers (SC ON1; C0h, SBUF1; C1h) to the original. The new serial port can only use Timer 1 for timer-generated baud rates. TIMER RATE CONTROL There is one important difference between the DS87C530/DS83C530 and 8051 regarding timers. The original 8051 used 12 clocks per cycle for timers as well as for machine cycles. The DS87C530/DS83C530 architecture normally uses 4 clocks per machine cycle. However, in the area of timers and serial ports, the DS87C530/DS83C530 will default to 12 clocks per cycle on reset. This allows existing code with real-time dependencies such as baud rates to operate properly. If an application needs higher speed timers or serial baud rates, the user can select individual timers to run at the 4-clock rate. The Clock Control register (CKCON; 8Eh) determines these timer speeds. When the relevant CKCON bit is logic 1, the DS87C530/DS83C 530 use 4 clocks per cycle to generate timer speeds. When the bit is a 0, the DS87C530 uses 12 cl ocks for timer speeds. The reset condition is a 0. Unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls are independent. POWER-FAIL RESET The DS87C530/DS83C530 use a precision bandgap voltage reference to decide if VCC is out of tolerance. While powering up, the internal monitor circuit maintains a reset state until V CC rises above the V RST level. Once above this level, the monitor enables the crystal oscillator and counts 65,536 clocks. It then exits the reset state. This power-on reset (POR) interval allows time for the oscillator to stabilize. A system needs no external components to generate a power-related reset. Anytime V CC drops below VRST, as in power failure or a power drop, the mon itor will generate and hold a reset. It occurs automatically, needing no action from the software. Refer to the Electrical Specifications section for the exact value of VRST. POWER-FAIL INTERRUPT The voltage reference that sets a precise reset threshold also generates an optional early warning power- fail interrupt (PFI). When enabled by software, the processor will vector to program memory address 0033h if V CC drops below VPFW. PFI has the highest priority. The PFI enable is in the Watchdog Control SFR (WDCON–D8h). Setting WDCON.5 to logic 1 will en able the PFI. Application software can also

(BGS) is set, a PFI will bring the device out of Stop mode. can be (re)started by software. Software can select one of four timeout values. Then, it restarts the timer and enables the reset function. by a “Timed Access” circuit. This prevents errant software from accidentally clearing the Watchdog. reference, the time periods at 33MHz also are shown. interrupt flag 512 clocks before setting the reset flag. Software can optionally enable this interrupt source. and WD0, respectively, and they select the Watchdog timeout period as shown in Table 7. Table 7. Watchdog Timeout Values free-running timer and does not require an enable.

to determine the reset source. EWT (WDCON.1) is the enable for the Watchdog Timer reset function. the user can enable the Watchdog Interrupt using EWDI (EIE.4). Table 8. Interrupt Sources and Priorities

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 28 of 47 TIMED-ACCESS PROTECTION It is useful to protect certain SFR bits from an accidental write operation. The Timed-Access procedure stops an errant CPU from accidentally changing these bits. It requires that the following instructions precede a write of a protected bit. MOV 0C7h, #0AAh MOV 0C7h, #55h Writing an AAh and then a 55h to the Timed-Access re gister (location C7h) opens a three-cycle window for write access. The window allows software to modi fy a protected bit(s). If these instructions do not immediately precede the write operation, then the write will not take effect. The protected bits are: EXIF.0 BGS Bandgap Select WDCON.6 POR Power-On Reset flag WDCON.1 EWT Enable Watchdog Reset WDCON.0 RWT Restart Watchdog WDCON.3 WDIF Watchdog Interrupt Flag ROMSIZE.2 RMS2 ROM Size Select 2 ROMSIZE.1 RMS1 ROM Size Select 1 ROMSIZE.0 RMS0 ROM Size Select 0 TRIM.7–0 — All RTC Trim Functions RTCC.2 RTCWE RTC Write Enable RTCC.0 RTCE RTC Oscillator Enable EPROM PROGRAMMING The DS87C530 follows standards for a 16kB EPROM versi on in the 8051 family. It is available in a UV erasable, ceramic windowed package and in plastic packages for one-time user-programmable versions. The part has unique signature information so programmers can support its specific EPROM options. PROGRAMMING PROCEDURE The DS87C530 should run from a clock speed betw een 4MHz and 6MHz when programmed. The programming fixture should apply addr ess information for each byte to the address lines and the data value to the data lines. The control signals must be manipulated as shown in Table 9. The diagram in Figure 5 shows the expected electrical connection for programming. Note that the programmer must apply addresses in demultiplexed fashion to Ports 1 and 2 with data on Port 0. Waveforms and timing are provided in the Electrical Specifications section. Program the DS87C530 as follows: 1) Apply the address value, 2) Apply the data value, 3) Select the programming option from Table 9 using the control signals, 4) Increase the voltage on VPP from 5V to 12.75V if writing to the EPROM, 5) Pulse the PROG signal five times for EPROM array and 25 times for encryption table, lock bits, and other EPROM bits, 6) Repeat as many times as necessary.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 29 of 47 DS87C530 SECURITY OPTIONS The DS87C530 employs a standard three-level lock th at restricts viewing of the EPROM contents. A 64- byte Encryption Array allows the authorized user to verify memory by presenting the data in encrypted form. Lock Bits The security lock consists of 3 lock bits. These bits select a total of 4 levels of security. Higher levels provide increasing security but also limit application flexibility. Table 10 shows the security settings. Note that the programmer cannot directly read the stat e of the security lock. User software has access to this information as described in the Memory section. Encryption Array The Encryption Array allows an authorized user to verify EPROM without allowing the true memory to be dumped. During a verify, each byte is Exclusive NORed (XNOR) with a byte in the Encryption Array. This results in a true representation of the EPRO M while the Encryption is unprogrammed (FFh). Once the Encryption Array is programmed in a non-FFh state, the verify value will be encrypted. For encryption to be effective, the Encryption Array mu st be unknown to the party that is trying to verify memory. The entire EPROM also should be a non-FFh state or the Encryption Array can be discovered. The Encryption Array is programmed as shown in Ta ble 9. Note that the programmer cannot read the array. Also note that the verify operation always uses the Encryption Array. The array has no impact while FFh. Simply programming the array to a non-FFh state will cause the encryption to function. Other EPROM Options The DS87C530 has user-selectable opti ons that must be set before beginning software execution. These options use EPROM bits rather than SFRs. Program the EPROM selectable options as shown in Table 9. The Option Register sets or reads these selections. The bits in the Option Control Register have the following function: Bits 7 to 4 Reserved, program to 1. Bit 3 Watchdog POR default. Set = 1; Wa tchdog reset function is disabled on power-up. Set = 0; Watchdog reset function is enabled automatically. Bits 2 to 0 Reserved. Program to 1. DS87C530 Signature The Signature bytes identify the product and pr ogramming revision to EP ROM programmers. This information is at programming addresses 30h, 31h, and 60h. This information is as follows: ADDRESS VALUE MEANING 30h DAh Manufacturer 31h 30h Model 60h 01h Extension

Table 9. EPROM Programming Modes

• PL indicates pulse to a logic low.

Table 10. EPROM Lock Bits

2 P U U

reset. Allow no further programming of EPROM. external memory from reading SRAM (MOVX) in internal memory. 4 P P P Level 3 plus no external execution.

Figure 7. EPROM Programming Configuration The DS83C530 supports a subset of the EPROM features found on the DS87C530. and its status can only be determined by observing the operation of the device.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 32 of 47 DS83C530 ROM Verification The DS83C530 memory contents can be verified us ing a standard EPROM programmer. The memory address to be verified is placed on the pins shown in Figure 7, and the programming control pins are set to the levels shown in Table 9. The data at that location is then asserted on port 0. DS83C530 Signature The Signature bytes identify the DS83C530 to EP ROM programmers. This information is at programming addresses 30h, 31h, and 60h. Because Mask ROM devices are not programmed in device programmers, most designers will find little use for the feature, and it is included only for compatibility. ADDRESS VALUE MEANING 30h DAh Manufacturer 31h 31h Model 60h 01h Extension

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 33 of 47 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.3V to (V CC + 0.5V) Voltage Range on VCC Relative to Ground ..-0.3V to +6.0V Operating Temperature Range .0°C to +70°C Storage Temperature Range ...-55°C to +125°C (Note 1) Soldering Temperature. See IPD/JEDEC J-STD-020 Specification This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 4.5V to 5.5V, TA = -40°C to +85°C.) (Note 2) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage VCC 4.5 5.0 5.5 V 3 Power-Fail Warning VPFW 4.25 4.38 4.5 V 3 Minimum Operating Voltage VRST 4.0 4.13 4.25 V 3 Backup Battery Voltage VBAT 2.5 3.0 V CC-0.7 V Supply Current Active Mode at 33MHz ICC 30 46 mA 4 Supply Current Idle Mode at 33MHz IIdle 15 25 mA 5 Supply Current Stop Mode, Bandgap Disabled (0°C to +70°C) 1 100 /g109A 6 Supply Current Stop Mode, Bandgap Disabled (-40°C to +85°C) IStop 1 150 /g109A 6 Supply Current Stop Mode, Bandgap Enabled (0°C to +70°C) 50 170 /g109A 6 Supply Current Stop Mode, Bandgap Enabled (-40°C to +85°C) ISPBG 50 195 /g109A 6 Backup Supply Current, Data-Retention Mode (0°C to +70°C) 0 0.5 /g109A 7 Backup Supply Current, Data-Retention Mode (-40°C to +85°C) IBAT 0 1 /g109A 7 Input Low Level V IL -0.3 +0.8 V 3 Input High Level V IH 2.0 V CC+0.3 V 3 Input High Level XTAL1 and RST V IH2 3.5 V CC+0.3 V 3 Output Low Voltage at IOL = 1.6mA V OL1 0.15 0.45 V 3 Output Low Voltage Ports 0, 2, ALE, and PSEN at IOL = 3.2mA VOL2 0.15 0.45 V 3 Output High Voltage Ports 1, 2, 3, ALE, PSEN at IOH = -50/g109A VOH1 2.4 V 3, 8 Output High Voltage Ports 1, 2, 3 at IOH = -1.5mA VOH2 2.4 V 3, 9 Output High Voltage Port 0 in Bus Mode IOH = -8mA VOH3 2.4 V 3, 10 Input Low Current Ports 1, 2, 3 at 0.45V IIL -70 /g109A 11 Transition Current from 1 to 0 Ports 1, 2, 3 at 2V ITL -800 /g109A 12

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 34 of 47 DC ELECTRICAL CHARACTERISTICS (continued) (VCC = 4.5V to 5.5V, TA = -40°C to +85°C.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Port 0, EA, Pins, I/O Mode IL -10 +10 /g109A 13 Input Leakage Port 0, Bus Mode IL -300 +300 /g109A 14 RST Pulldown Resistance RRST 50 200 k/g87 Note 1: Storage temperature is defined as the temperature of the device when VCC = 0V and VBAT = 0V. In this state, the contents of SRAM are not battery backed and are undefined. Note 2: All parameters apply to both commercial and industrial temperature operation unless otherwise noted. Note 3: All voltages are referenced to ground. Note 4: Active current measured with 33MHz clock source on XTAL1, VCC = RST = 5.5V, other pins disconnected. Note 5: Idle mode current measured with 33MHz clock source on XTAL1, VCC = 5.5V, RST at ground, other pins disconnected. Note 6: Stop mode current measured with XTAL1 and RST grounded, VCC = 5.5V, all other pins disconnected. Note 8: RST = V CC. This condition mimics operation of pins in I/O mode. Port 0 is tri-stated in reset and when at a logic high state during I/O mode. Note 9: During a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transitio n mode. Note 10: When addressing external memory. This specification only applies to the first clock cycle following the transition. Note 11: This is the current required from an external circuit to hold a logic low level on an I/O pin while the corresponding port lat ch bit is set to 1. This is only the current required to hold the low level; transitions from 1 to 0 on an I/O pin will also have to overcome the transition current. Note 12: Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at approximately 2V. Note 13: 0.45 < VIN < VCC. RST = VCC. This condition mimics operation of pins in I/O mode. Note 14: 0.45 < V IN < VCC. Not a high-impedance input. This port is a weak address holding latch in Bus Mode. Peak current occurs near the input transition point of the latch, approximately 2V. TYPICAL ICC vs. FREQUENCY

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 35 of 47 AC ELECTRICAL CHARACTERISTICS (Note 1) 33MHz VARIABLE CLOCK PARAMETER SYMBOL MIN MAX MIN MAX UNITS External Oscillator 0 33 0 33 Oscillator Frequency External Crystal 1/tCLCL 1 33 1 33 MHz ALE Pulse Width t LHLL 40 1.5t CLCL-5 ns Port 0 Address Valid to ALE Low t AVLL 10 0.5t CLCL-5 ns Address Hold after ALE Low t LLAX1 (Note 2) (Note 2) ns ALE low to Valid Instruction In t LLIV 43 2.5t CLCL-33 ns ALE Low to PSEN Low tLLPL 4 0.5t CLCL-11 ns PSEN Pulse Width tPLPH 55 2t CLCL-5 ns PSEN Low to Valid Instruction In tPLIV 37 2t CLCL-24 ns Input Instruction Hold after PSEN tPXIX 0 0 ns Input Instruction Float after PSEN tPXIZ 26 t CLCL-5 ns Port 0 Address to Valid Instruction In t AVIV1 59 3t CLCL-32 ns Port 2 Address to Valid Instruction In t AVIV2 68 3.5t CLCL-38 ns PSEN Low to Address Float tPLAZ (Note 2) (Note 2) ns Note 1: All parameters apply to both commercial and industrial temperature range operation unless otherwise noted. Specifications to -40°C are guaranteed by design and are not production tested. AC electrical characteristics are not 100% tested, but are characterized and guaranteed by design. All signals are characterized with load capacitance of 80pF except Port 0, ALE, PSEN, RD and WR with 100pF. Interfacing to memory devices with float times (turn off times) over 25ns may cause contention. This will not damage the parts, but will cause an increase in operating current. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing will change in relation to duty cycle variation. Note 2: Address is driven strongly until ALE falls, and is then held in a weak latch until overdriven externally.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 36 of 47 MOVX CHARACTERISTICS USING STRETCH MEMORY CYCLES VARIABLE CLOCK PARAMETER SYMBOL MIN MAX UNITS STRETCH 1.5tCLCL-5 t MCS=0 Data Access ALE Pulse Width t LHLL2 2tCLCL-5 ns tMCS>0 0.5tCLCL-5 t MCS=0 Port 0 Address Valid to ALE Low t AVLL2 tCLCL-5 ns tMCS>0 0.5tCLCL-10 t MCS=0 Address Hold After ALE Low for MOVX Write tLLAX2 tCLCL-7 ns tMCS>0 2tCLCL-5 t MCS=0 RD Pulse Width tRLRH tMCS-10 ns tMCS>0 2tCLCL-5 t MCS=0 WR Pulse Width tWLWH tMCS-10 ns tMCS>0 2t CLCL-22 t MCS=0 RD Low Valid Data In tRLDV t MCS-24 ns tMCS>0 Data Hold After Read t RHDX 0 ns — t CLCL-5 ns t MCS=0 Data Float After Read t RHDZ 2t CLCL-5 t MCS>0 2.5t CLCL-31 t MCS=0 ALE Low to Valid Data In t LLDV t MCS+tCLCL-26 ns tMCS>0 3t CLCL-29 t MCS=0 Port 0 Address to Valid Data In t AVDV1 t MCS+2CLCL-29 ns tMCS>0 3.5t CLCL-37 t MCS=0 Port 2 Address to Valid Data In t AVDV2 t MCS+2.5LCL-37 ns tMCS>0 0.5tCLCL-10 0.5t CLCL+5 t MCS=0 ALE Low to RD or WR Low tLLWL tCLCL-5 t CLCL+5 ns tMCS>0 tCLCL-9 t MCS=0 Port 0 Address to RD or WR Low tAVWL1 2tCLCL-7 ns tMCS>0 1.5tCLCL-17 t MCS=0 Port 2 Address to RD or WR Low tAVWL2 2.5tCLCL-16 ns tMCS>0 Data Valid to WR Transition tQVWX -6 ns tCLCL-5 t MCS=0 Data Hold After Write t WHQX 2tCLCL-6 ns tMCS>0 RD Low to Address Float tRLAZ (Note 1) ns -4 10 t MCS=0 RD or WR High to ALE High tWHLH tCLCL-5 t CLCL+5 ns tMCS>0 Note 1: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the value of tMCS for each Stretch selection.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 37 of 47 MOVX CHARACTERISTICS USING STRETCH MEMORY CYCLES (continued) M2 M1 M0 MOVX CYCLES t MCS 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles (default) 4 t CLCL 0 1 0 4 machine cycles 8 t CLCL 0 1 1 5 machine cycles 12 t CLCL 1 0 0 6 machine cycles 16 t CLCL 1 0 1 7 machine cycles 20 t CLCL 1 1 0 8 machine cycles 24 t CLCL 1 1 1 9 machine cycles 28 t CLCL EXTERNAL CLOCK CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS Clock High Time t CHCX 10 ns Clock Low Time t CLCX 10 ns Clock Rise Time t CLCL 5 ns Clock Fall Time t CHCL 5 ns SERIAL PORT MODE 0 TIMING CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SM2 = 0, 12 clocks per cycle 12t CLCL Serial Port Clock Cycle Time tXLXL SM2 = 1, 4 clocks per cycle 4t CLCL ns SM2 = 0, 12 clocks per cycle 10t CLCL Output Data Setup to Clock Rising tQVXH SM2 = 1, 4 clocks per cycle 3t CLCL ns SM2 = 0, 12 clocks per cycle 2t CLCL Output Data Hold from Clock Rising tXHQX SM2 = 1, 4 clocks per cycle t CLCL ns SM2 = 0, 12 clocks per cycle t CLCL Input Data Hold after Clock Rising tXHDX SM2 = 1, 4 clocks per cycle t CLCL ns SM2 = 0, 12 clocks per cycle 11t CLCL Clock Rising Edge to Input Data Valid tXHDV SM2 = 1, 4 clocks per cycle 3t CLCL ns

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 38 of 47 EXPLANATION OF AC SYMBOLS In an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such devices, using the same symbols. For completeness, the following is an explanation of the symbols. t Time A Address C Clock D Input data H Logic level high L Logic level low I Instruction P PSEN Q Output data R RD signal V Valid W WR signal X No longer a valid logic level Z Tri-State POWER-CYCLE TIMING CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Cycle Startup Time t CSU 1.8 ms 1 Power-On Reset Delay t POR 65,536 t CLCL 2 Note 1: Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592MHz crystal manufactured by Fox. Note 2: Reset delay is a synchronous counter of crystal oscillations after crystal startup. At 33MHz, this time is 1.99ms. EPROM PROGRAMMING AND VERIFICATION (VCC = 4.5V to 5.5V, TA = +21°C to +27°C.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Programming Voltage V PP 12.5 13.0 V 1 Programming Supply Current I PP 50 mA Oscillator Frequency 1/t CLCL 4 6 MHz Address Setup to PROG Low tAVGL 48tCLCL Address Hold after PROG tGHAX 48tCLCL Data Setup to PROG Low tDVGL 48tCLCL Data Hold after PROG tGHDX 48tCLCL Enable High to VPP tEHSH 48tCLCL VPP Setup to PROG Low tSHGL 10 /g109s VPP Hold after PROG tGHSL 10 /g109s PROG Width tGLGH 90 110 /g109s Address to Data Valid t AVQV 48t CLCL Enable Low to Data Valid t ELQV 48t CLCL Data Float after Enable t EHQZ 0 48t CLCL PROG High to PROG Low tGHGL 10 /g109s Note 1: All voltages are referenced to ground.

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 39 of 47 EXTERNAL PROGRAM MEMORY READ CYCLE EXTERNAL DATA MEMORY READ CYCLE tVALL2

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 40 of 47 DATA MEMORY WRITE CYCLE DATA MEMORY WRITE WITH STRETCH = 1 tAVLL2

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 41 of 47 DATA MEMORY WRITE WITH STRETCH = 2 EXTERNAL CLOCK DRIVE

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 42 of 47 SERIAL PORT MODE 0 TIMING

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 43 of 47 POWER-CYCLE TIMING EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 44 of 47

PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 45 of 47 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 46 of 47 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PKG 52-PIN DIM MIN NOM MAX A — — 1.20 A1 0.05 0.10 0.15 A2 0.95 1.00 1.05 b 0.25 0.32 0.40 c 0.09 — 0.20 D 11.80 12.00 12.20 D1 10.00 BSC E 11.80 12.00 12.20 E1 10.00 BSC e 0.65 BSC L 0.45 0.60 0.75

DS87C530/DS83C530 EPROM/ROM Microcontrollers with Real-Time Clock 47 of 47 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DATA SHEET REVISION SUMMARY REVISION DESCRIPTION 071107 1) Corrected P1.5 pin for TQ FP package from 4 to 1 (page 5). 070505 2) Added Pb-free/RoHS-compliant part numbers to Ordering Information table. 3) Deleted the “A” from the IPC/JEDEC J-STD-020 specification in the Absolute Maximum Ratings. 040104 4) Removed “Preliminary” status. 5) Soldering temperature parameter now references JEDEC specification. 6) Added note to absolute maximums clarifying voltages referenced to ground and storage temperature. 7) Updated I CC, IIDLE, ISTOP, ISPBG, IIL, and ITL to incorporate errata conditions. 8) Added note clarifying DC electrical test conditions. 9) Added note clarifying V OH3 specification applies to first clock cycle following the transition. 10) Updated AC and MOVX electrical charact eristics with final characterization values. 11) Added t AVLL2 specification and corrected MOVX timing diagrams to show tAVLL2 instead of tAVLL. 12) Updated I BAT to incorporate errata conditions. 112299 Contact factory for details. 070798 1) Added DS83C530 to data sheet. 2) Updated PMM operating current estimates. 3) Added note to clarify I IL specification. 4) Added note to prevent accidental corruption of Watchdog Timer count while changing counter length. 5) Changed I BAT specification to 1μA over extended temperature range. 6) Changed minimum oscillator frequency to 1MHz when using external crystal. 7) Changed RST pulldown resistance from 170k Ω to 200kΩ maximum. 8) Corrected “Data memory write with stretch” diag rams to show falling edge of ALE coincident with rising edge of C3 clock. 022097 1) Updated ALE pin description. 2) Added note pertaining to erasure window. 3) Added note pertaining to internal MOVX SRAM. 4) Changed Note 6 from RST=5.5V to RST=V CC. 5) Changed Note 10 from RST=5.5V to RST=V CC. 6) Changed serial port mode 0 timing diagram label from t QVXL to tQVXH. 7) Added information pertaining to 52-pin TQFP package. 060895 Initial release.