DS89C420

DS89C420 DALLAS | Alldatasheet

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Technical content

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS89C420 offers the highest performance available in 8051-compatible microcontrollers. It features a redesigned processor core that executes every 8051 instruction (depending on the instruction type) up to 12 times faster than the original for the same crystal speed. Typical applications see a speed improvement of 10 times using the same code and crystal. The DS89C420 offers a maximum crystal speed of 33MHz, achieving execution rates up to 33 million instructions per second (MIPS).

APPLICATIONS

Appliances (Washers, Microwaves, etc.) Telephones HVAC Building Security and Door Access Control Building Energy Control and Management Uninterruptible Power Supplies Programmable Logic Controllers Industrial Control and Automation

ORDERING INFORMATION

MAX. CLOCK SPEED (MHz) PIN-PACKAGE DS89C420- MCL 0°C to +70°C 33 40 PDIP DS89C420- QCL 0°C to +70°C 33 44 PLCC DS89C420- ECL 0°C to +70°C 33 44 TQFP Ordering information continued at end of data sheet.

FEATURES

/g167 80C52 Compatible /g45 8051 Pin and Instruction-Set Compatible /g45 Four Bidirectional I/O Ports /g45 Three 16-Bit Timer Counters /g45 256 Bytes Scratchpad RAM /g167 On-Chip Memory /g45 16kB Flash Memory /g45 In-System Programmable through Serial Port /g45 1kB SRAM for MOVX /g167 ROMSIZE Feature /g45 Selects Internal Program Memory Size from 0 to 16k /g45 Allows Access to Entire External Memory Map /g45 Dynamically Adjustable By Software See page 2 for a complete list of features. PIN CONFIGURATIONS www.maxim-ic.com DS89C420 Ultra-High-Speed Microcontroller P1.0/T2 P1.1/T2EX P1.2/RXD1 P1.3/TXD1 P1.4/INT2 P1.5/INT3 P1.6/INT4 P1.7/INT5 RST P3.0/RXD0 P3.1/TXD0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS VCC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 DS89C420 DIP TOP VIEW Pin Configurations continued at end of data sheet.

/g167 80C52 compatible /g45 8051 pin and instruction-set compatible /g45 Four bidirectional I/O ports /g45 Three 16-bit timer counters /g45 256 bytes scratchpad RAM /g167 On-chip memory /g45 16kB flash memory /g45 In-system programmable through serial port /g45 1kB SRAM for MOVX /g167 ROMSIZE feature /g45 Selects internal program memory size from 0 to 16k /g45 Allows access to entire external memory map /g45 Dynamically adjustable by software /g167 High-speed architecture /g45 1 clock-per-machine cycle /g45 DC to 33MHz operation /g45 Single-cycle instruction in 30ns /g45 Optional variable length MOVX to access fast/slow peripherals /g45 Dual data pointers with auto increment/decrement and toggle select /g45 Supports four paged modes /g167 Power Management Mode /g45 Programmable clock divider /g45 Automatic hardware and software exit /g167 Two full-duplex serial ports /g167 Programmable watchdog timer /g167 13 interrupt sources (six external) /g167 Five levels of interrupt priority /g167 Power-fail reset /g167 Early warning power-fail interrupt DETAILED DESCRIPTION The DS89C420 is pin compatible with all three p ackages of the standard 8051 and includes standard resources such as three timer/counters, four 8-bit I/O ports, and a serial port. It features 16kB of in-system programmable flash memory, which can be programmed in-system from an I/O port using a built-in program memory loader. It can also be loaded externally using standard commercially available programmers. Besides greater speed, the DS89C420 includes 1kB of data RAM, a second full-hardware serial port, seven additional interrupts, two more levels of interrupt priority, programmable watchdog timer, brown- out monitor, and power-fail reset. The device also provides dual data pointers (DPTRs) to speed up block-data memory moves. This feature is further enhanced with a new selectable automatic increment/decrement and toggle-select operation. The speed of MOVX data memory access can be adjusted by adding stretch values up to 10 machine cycle times for flexibility in selecting external memory and peripherals. A power management mode (PMM) significantly consumes less power by slowing the CPU execution rate from 1 clock period per cycle to 1024 clock peri ods per cycle. A selectable switchback feature can automatically cancel this mode to enable a normal speed response to interrupts. The EMI reduction feature disables the ALE signal when the processor is not accessing external memory.

Figure 1. Block Diagram

Table 1. Pin Description a Schmitt trigger to recognize external active-high reset inputs. output of the crystal amplifier. PSEN remains low for consecutive page hits. PROG ) is used to execute the parallel program function. resistors are required when using Port 0 as an I/O port.

DIP PLCC TQFP NAME FUNCTION 1–8 2–9 40–44 P1.0–P1.7 Port 1, I/O. Port 1 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for timer 2 I/O, new external interrupts, and new serial port 1. The reset condition of port 1 is with all bits at a logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input state, since any external circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any port pin, the DS89C420 activates a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes the output high (and input) state. The alternate functions of Port 1 are outlined below. PORT ALTERNATE FUNCTION P1.0 T2 External I/O for Timer/Counter2 P1.1 T2EX Timer 2 Capture/Reload Trigger P1.2 RXD1 Serial Port 1 Receive P1.3 TXD1 Serial Port 1 Transmit P1.4 INT2 External Interrupt 2 (Positive Edge Detect) P1.5 INT3 External Interrupt 3 (Negative Edge Detect) P1.6 INT4 External Interrupt 4 (Positive Edge Detect) P1.7 INT5 External Interrupt 5 (Negative Edge Detect) P2.0 (A8) P2.1 (A9) P2.2 (A10) P2.3 (A11) P2.4 (A12) P2.5 (A13) P2.6 (A14) P2.7 (A15) Port 2 (A8–15), I/O. Port 2 is an 8-bit, bidirectional I/O port. The reset condition of port 2 is logic high. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any port pin, the DS89C420 activates a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. As an alternate function, port 2 can function as the MSB of the external address bus when reading external program memory and read/write external RAM or peripherals. In page mode 1, port 2 provides both the MSB and LSB of the external address bus; in page mode 2, it provides the MSB and data.

DIP PLCC TQFP NAME FUNCTION 10–17 11, 13– 5, 7–13 P3.0–P3.7 Port 3, I/O. Port 3 functions as both an 8-bit, bidirectional I/O port and an alternate functional interface for external interrupts, serial port 0, timer 0 and 1 inputs, and RD and WR strobes. The reset condition of port 3 is with all bits at a logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port overcomes the weak pullup. When software writes a 0 to any port pin, the DS89C420 activates a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 causes a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. The alternate modes of Port 3 are outlined below. P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 PORT ALTERNATE FUNCTION P3.0 RXD0 Serial Port 0 Receive P3.1 TXD0 Serial Port 0 Transmit P3.2 INT0 External Interrupt 0 P3.3 INT1 External Interrupt 1 P3.4 T0 Timer 0 External Input P3.5 T1 Timer 1 External Input P3.6 WR External Data Memory Write Strobe P3.7 RD External Data Memory Read Strobe 31 35 29 EA External Access. Allows selection of internal or external program memory. Connect to ground to force the DS89C420 to use an external memory-program memory. The internal RAM is still accessible as determined by register settings. Connect to VCC to use internal flash memory.

The DS89C420 is a fully static CMOS 8051-compa tible microcontroller similar to the DS87C520 in functional features, but with much higher perform ance. In most cases the DS89C420 can drop into an existing socket for the 8xC51 family to improve the operation significantly. While remaining familiar to 8051 family users, it has many new features. The DS89C420 runs the standard 8051 family instruction set and is pin compatible with DIP, PLCC, and TQFP packages. In general, software written for existing 8051-based systems works without DS89C420 modification, with th e exception of critical timing routines, since the DS89C420 performs its instructions much faster than the original for any given crystal selection. The DS89C420 provides three 16-bit timer/counters, two full-duplex serial ports, and 256 bytes of direct RAM plus 1kB of extra MOVX RAM. I/O ports can operate as in standard 8051 products. Timers default to a 12 clock-per-cycle operation to keep their timing compatible with original 8051 family systems. However, timers are individually programmable to run at the new 1 clock-per-cycle if desired. The DS89C420 provides several new hardware features implemented by new SFRs. Performance Overview The DS89C420 features a completely redesigned high -speed 8051-compatible core and allows operation at a higher clock frequency, but the updated core does not have the dummy memory cycles that are present in a standard 8051. A conventional 8051 gene rates machine cycles using the clock frequency divided by 12. In the DS89C420, the same machine cy cle takes 1 clock. Thus, the fastest instructions execute 12 times faster for the same crystal frequency (and actually 24 times faster for the INC data pointer instruction). It should be noted that this speed improvement reduces when using external memory access modes that require more than 1 clock per cycle. Improvement of individual programs depends on the actual instructions used. Speed-sensitive applications make the most use of instructions that are 12 times faster. However, the sheer number of 12- to-1 improved op codes makes dram atic speed improvements likely for any code. These architecture improvements produce instruction cycle times as low as 30ns (33MIPs). The dual data pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory. The new page modes allow for increased efficiency in external memory accesses. Instruction Set Summary All instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and other status functions is also identical. However, the timing of each instruction is different in both absolute and relative number of clocks. For absolute timing of real-time events, the timing of so ftware loops can be calculated using information in the “Instruction Set” table of the Ultra-High-Speed Flash Microcontroller User’s Guide. However, counter/timers default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at lower numbers of clocks per increment to take advantage of faster processor operation. The relative time of some instructions might be different in the new architecture than it was previously. For example, in the original architecture, the “MOVX A, @DPTR” instruction and the “MOV direct, direct” instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS89C420, the MOVX instruction takes as little as two machine cycles or two oscillator cycles but the “MOV direct, direct” uses three machine cycles or three oscillator cycles. While both are faster than their original counterparts, they now have different execution times. This is because the DS89C420 usually uses one machine cycle for ea ch instruction byte and requires one cycle for

execution. The user concerned with precise program timing should examine the timing of each instruction to become familiar with the changes. Special Function Registers (SFRs) All peripherals and operations that are not explic it instructions in the DS89C420 are controlled through SFRs. The most common features basic to the architecture are mapped to the SFRs. These include the CPU registers (ACC, B, and PSW), data pointers (DPTRs), stack point er, I/O ports, timer/counters, and serial ports. In many cases, an SFR controls an i ndividual function or reports the function’s status. The SFRs reside in register locations 80h–FFh and are only accessible by direct addressing. SFRs whose addresses end in 0h or 8h are bit-addressable. All standard SFR locations from the 8051 are duplicat ed in the DS89C420 and several SFRs have been added for the unique features of the DS89C420. Most of these features are controlled by bits in SFRs located in unused locations in the 8051 SFR map. This allows for increased functionality while maintaining complete instruction set compatibility. Table 2 summarizes the SFRs and their locations. Table 3 specifies the default reset condition for all SFR bits. Data Pointers The data pointers (DPTR and DPTR1) are used to a ssign a memory address for the MOVX instructions. This address can point to a MOVX RAM location (on- chip or off-chip), or a memory-mapped peripheral. Two pointers are useful when moving data from one me mory area to another, or when using a memory- mapped peripheral for both source and destination addresses. The user selects the active pointer through a dedicated SFR bit (Sel = DPS.0), or activates an automatic toggling feature for altering the pointer selection (TSL = DPS.5). An additional feature, if selected, provides automatic incrementing or decrementing of the current DPTR. Stack Pointer The stack pointer denotes the register location at the top of the stack, which is the last used value. The user can place the stack anywhere in the scratchpa d RAM by setting the stack pointer to the desired location, although the lower bytes are normally used for working registers. I/O Ports The DS89C420 offers four 8-bit I/O ports. Each I/O po rt is represented by an SFR location, and can be written or read. The I/O port has a latch that contains the value written by software. Counter/Timers Three 16-bit timer/counters are available in the DS 89C420. Each timer is contained in two SFR locations that can be read or written by software. The timers are controlled by other SFRs described in the “SFR Bit Description” section of the Ultra-High-Speed Flash Microcontroller User’s Guide. Serial Ports The DS89C420 provides two UARTs th at are controlled and accessed by SFRs. Each UART has an address that is used to read and write the UART. The same address is used for both read and write operations, and the read and write operations ar e distinguished by the instruction. Each UART is controlled by its own SFR control register.

Table 2. Special Function Registers

REGISTER ADDR BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 PSW D0h CY AC F0 RS1 RS0 OV F1 P FCNTL D5h FBUSY FERR —— FC3 FC2 FC1 FC0 WDCON D8h SMOD_1 POR EPFI PFI WDIF WTRF EWT RWT EIE E8h — — — EWDI EX5 EX4 EX3 EX2 EIP1 F1h — — — MPWDI MPX5 MPX4 MPX3 MPX2 EIP0 F8h — — — LPWDI LPX5 LPX4 LPX3 LPX2

Table 3. SFR Reset Value

REGISTER ADDR BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 T L 2 C C h 0000000 0 T H 2 C D h 0000000 0 P S W D 0 h 0000000 0 F C N T L D 5 h 1011000 0 F D A T A D 6 h 0000000 0 WDCON D8h 0 Special 0 Special 0 Special Special 0 A C C E 0 h 0000000 0 E I E E 8 h 1110000 0 B F 0 h 0000000 0 E I P 1 F 1 h 1110000 0 E I P 0 F 8 h 1110000 0

There are three distinct memory areas in the DS89C420: scratchpad re gisters, program memory, and data memory. All registers are located on-chip but the program and data memory spaces can be either on-chip, off-chip, or both. There are 16kB of on-chip program memory implemented in flash memory and 1kB of on-chip data memory space that can be configured as program space using the PRAME bit in the ROMSIZE feature. The DS89C420 uses a memory-add ressing scheme that se parates program memory from data memory. The program and data segments can be overlapped since they are accessed in different ways. If the maximum address of on-chip program or data memory is exceeded, the DS89C420 performs an external memory access using the expanded memory bus. The PSEN signal goes active low to serve as a chip enable or output enable when performing a code fetch from external program memory. MOVX instructions activate the RD or WR signal for external MOVX data memory access. The lower 128 bytes of on-chip flash memory store reset and interrupt vectors. The program memory ROMSIZE feature allows software to dynamically configure the maximum address of on-chip program memory. This allows the DS89C420 to act as a bootloader fo r an external flash or NV SRAM. It also enables the use of the overlapping external program spaces. 256 bytes of on-chip RAM serve as a register area and program stack, which are separated from the data memory. Register Space Registers are located in the 256 byte s of on-chip RAM, which can be divided into two subareas of 128 bytes each as illustrated in Figure 2. Separate classes of instructions are used to access the registers and the program/data memory. The upper 128 bytes are overlapped with the 128 bytes of SFRs in the memory map. The upper 128 bytes of scratchpad RAM are acce ssed by indirect addressing, and the SFR area is accessed by direct addressing. The lower 128 bytes can be accessed by direct or indirect addressing. There are four banks of eight individual working re gisters in the lower 128 bytes of scratchpad RAM. The working registers are general-purpose RAM locations that can be addressed within the selected bank by any instructions that use R0–R7. The register bank selection is controlled through the program status register in the SFR area. The contents of the working registers can be used for indirectly addressing the upper 128 bytes of scratchpad RAM. To support the Boolean operations, there are indivi dually addressable bits in both the RAM and SFR areas. In the scratchpad RAM area, registers 20h–2Fh are bit-addressable by software using Boolean operation instructions. Another use of the scratchpad RAM area is for the stack. The stack pointer in the SFRs is used to select storage locations for program variables and for return addresses of control operations.

Figure 2. Memory Map

128 Bytes

128 Bytes SFR

As illustrated in Figure 2, the DS89C420 incorporates two 8kB flash memories for on-chip program memory and 1kB of SRAM for on-chip data memory or a particular range (400–7FF) of “alternate” program memory space. The DS89C420 uses an addr ess scheme that separa tes program memory from data memory, such that the 16-bit address bus can address each memory area up to 64kB. Program Memory Access On-chip program memory begins at address 0000h a nd is contiguous through 3FFFh (16kB). Exceeding the maximum address of on-chip program memory causes the device to access off-chip memory. However, the maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the DS89C420 to behave like a de vice with less on-chip memory. This is beneficial when overlapping external memory is used. The maximum memory size is dynamically variable. Thus, a portion of memory can be removed from the memory map to access off-chip memory, then be restored to access on-chip memory. In fact, all of the on-chip memory can be removed from the memory map allowing the full 64kB memory space to be addressed from off-chip memory. Program memory addresses that are larger than the selected maximum are automatically fetched from outside the part through ports 0 and 2 (Figure 2). The ROMSIZE register is used to select the maximum on-chip decoded address for program memory. Bits RMS2, RMS1, RMS0 have the following effect: RMS2 RMS1 RMS0 ADDRESS MAXIMUM ON-CHIP PROGRAM MEMORY 00 0 0 k 0 0 1 1k/03FFh 0 1 0 2k/07FFh 0 1 1 4k/0FFFh 1 0 0 8k/1FFFh 1 0 1 16k (default)/3FFFh 1 1 0 Invalid–Reserved 1 1 1 Invalid–Reserved The reset default condition is a maximum on-chip program-memory address of 16kB. When accessing external program memory, the first 16kB would be in accessible. To select a smaller effective program memory size, software must alter bits RMS2–RMS0. Altering these bits requires a timed access procedure as explained later. Care should be taken so that changing the ROMSI ZE register does not corrupt program execution. For example, assume that a DS89C420 is executing instructions from internal program memory near the 12kB boundary (~3000h) and that the ROMSIZE register is currently configured for a 16kB internal program space. If software reconfigures the ROMSIZE register to 4kB (0000h–0FFFh) in the current state, the device immediately jumps to external program execution because program code from 4kB to 16kB (1000h–3FFFh) is no longer located on-chip. This could result in code misalignment and execution of an invalid instruction. The recommended method is to modify the ROMSIZE register from a location in memory that is internal (or external) both before and after the operation. In the above example, the instruction that modifies the ROMSIZE register should be located below the 4kB (1000h) boundary or above the 16kB (3FFFh) boundary so that it is una ffected by the memory modification. The same precaution should be applied if the internal program memory size is modified while executing from external program memory.

For non-page mode operations, off-chip memory is accessed using the multiple xed address/data bus on P0 and the MSB address on P2. While serving as a memory bus, these pins are not I/O ports. This convention follows the standard 8051 method of ex panding on-chip memory. Off-chip program memory access also occurs if the EA pin is a logic 0. EA overrides all bit settings. The PSEN signal goes active (low) to serve as a chip enable or output enable when port 0 and port 2 fetch from external program memory. The RD and WR signals are used to control the external data memory device. Data memory is accessed by MOVX instructions. The MOVX@Ri instruction uses the value in the designated working register to provide the LSB of the address, while port 2 supplies the address MSB. The MOVX@DPTR instruction uses one of the two data pointer s to move data over the entire 64kB external data memory space. Software selects the data pointer to be used by writing to the SEL bit (DPS.0). The DS89C420 also provides a user option for high-speed external memory access by reconfiguring the external memory interface into page mode operation. Note: When using the original 8051 expanded bus structure, the throughput is reduced by 75% compared with that of internal operations. This is due to the CPU being stalled for three out of four clocks waiting for the data fetch, which takes four clocks. Page Mode 1 is the only ex ternal addressing mode where the CPU does not require stalls for external memory access, but page misses result in reduced external access performance. On-Chip Program Memory The full on-chip program memory range can be fetched by the processor automatically. The reset routines and all interrupt vectors are located in the lower 128 bytes of the on-chip program memory area. On-chip program memory is logically divided into two 8kB flash memory banks and is designed to be programmed with the standard 5V VCC supply by using a built-in program memory loader. It can also be programmed in standard flash or EPROM pr ogrammers. The DS89C420 incorporates a memory management unit (MMU) and other hardware to s upport any of the two programming methods. The MMU controls program and data memory access, and provides seque ncing and timing controls for programming the on-chip program memory. There is also a separate security flash block that is used to support a standard three-level lock, a 64-byte encryption array, and other flash options. Security Features The DS89C420 incorporates a 64-byte encryption array, allowing the user to verify program codes while viewing the data in encrypted form. The encryption array is implemented in a security flash memory block that has the same electrical and timing characteristics as the on-chip program memory. Once the encryption array is programmed to non-FFh, the data presented in the verify mode is encrypted. Each byte of data is XNOR’ed with a byte in the encryption array during verification. A three-level lock restricts viewing of the internal program and data memory contents. By programming the three lock bits, the user can select a level of security as specified in Table 4. Once a security level is selected and programmed, the setting of the lock bits remains. Only a mass erase can erase these bits to allow reprogramming the security level to a less restricted protection.

Table 4. Flash Memory Lock Bits further parallel or program memory loader programming. memory from reading internal SRAM. 4 X X 0 Level 3 plus no external execution. The DS89C420 provides user-sel ectable options that must be set before beginning software execution. programmable as a byte-wide register. Bit 3 of this register is defined as the watchdog POR default. executing a verify-option control-register instruction in ROM loader mode. being used for communication and sets up the baud rate generator for communication at that frequency.

configure and load the microcontrollers are available at www.maxim-ic.com/micros/ftpinfo.html. Microcontroller User’s Guide. Figure 3. Interfacing the Bootloader to a PC

The DS89C420 allows parallel programming of its internal flash memory compatible with standard flash or EPROM programmers. In parallel programming mode, a mass-erase command is used to erase all memory locations in the 16kB program memory, the security block, and the memory bank select. Erasing the memory bank select sets it to the default state; the memory bank select cannot be altered otherwise. If lock bit LB2 has not been programmed, the program code can be read back for verification. The state of the lock bits can also be verified directly in the parallel programming mode. One instruction is used to read signature information (at addresses 30, 31, and 60h). Separate instructions are used for the option control register. The following sequence can be used to program the flash memory in the parallel programming mode: The DS89C420 is powered up and running at a clock speed between 4MHz and 6MHz. 2) Set RST = EA = 1 and PSEN = 0. 3) Apply the appropriate logic combination to pins P2.6, P2.7, P3.6, and P3.7 to select one of the flash instructions shown in Table 8. /g45 For program operation, apply the desired address to pins P1.7:0 and P2.5:0. Data is written to port 0. /g45 For verify operation, apply the desired address to pins P1.7:0 and P2.5:0. Data is read at port 0. 4) Pulse ALE/PROG once to perform an erase/program operation. 5) Repeat steps 3 and 4 as necessary.

Table 5. Parallel Programming Instruction Set memory location is returned to FFh. (3) L H H H Program the 16k program memory. Memory ADDR DOUT H (4) L L H H Verify the 16k program memory. Write LB1 Don’t care Don’t care PL (3) HHHH P r o g r a m L B 1 t o l o g i c 0 . Write LB2 Don’t care Don’t care PL (3) H H L L Program LB2 and LB1 to 00b. Program the option control register. watchdog POR default setting. Erase the option control register. dog reset function on power-up. logic value of the watchdog POR. 1) Mass erase requires an active-low PROG pulse width of 828ms. 2) Erase option control register requires an active-low PROG pulse width of 828ms. 3) Byte program requires an active-low PROG pulse width of 100/g109s max. 4) PROG is weakly pulled to a high internally. Note 1: P3.2 is pulled low during programming to indicate Busy. P3.2 is pulled high again when programming is completed to indicate Ready. Note 2: P3.0 is pulled high during programming to indicate an error.

On-chip data memory is provided by the 1kB SR AM and occupies addresses 0000h through 03FFh. The internal data memory is disabled after a power-on reset, and any MOVX instruction directs the data memory access to the external data memory. To enable the internal data memory, software must configure the data memory enable bits DME1 and DME0 (PMR.1-0). See “SFR Bit Descriptions” in the Ultra-High-Speed Flash Microcontroller User’s Guide for data memory configurations. Once enabled, MOVX instructions with addresses inside the 1k range access the on-chip data memory, and addresses exceeding the 1k range automatically access external data memory. An internal data memory cycle spans only one system clock period to support fast internal execution. Data Pointer Increment/Decrement and Options The DS89C420 incorporates a hardwa re feature to assist applica tions that require data pointer increment/decrement. Data pointer increment/decrement bits ID0 and ID1 (DPS.6 and DPS.7) define how the INC DPTR instruction functions in relation to the active DPTR (selected by the SEL bit). Setting ID0 = 1 and SEL = 0 enables the decrement ope ration for DPTR, and execution of the INC DPTR instruction decrements the DPTR contents by 1. Similarly, setting ID1 = 1 and SEL = 1 enables the decrement operation for DPTR1, and execution of th e INC DPTR instruction decrements the DPTR1 contents by 1. With this feature, the user can configure the data pointers to operate in four ways for the INC DPTR instruction: ID1 ID0 SEL = 0 SEL = 1 0 0 Increment DPTR Increment DPTR1 0 1 Decrement DPTR Increment DPTR1 1 0 Increment DPTR Decrement DPTR1 1 1 Decrement DPTR Decrement DPTR1 The active data pointer is always selected by the SEL (DPS.0) bit. The DS89C420 offers a programmable option that allows any instructions related to data pointer to toggle the SEL bit automatically. This option is enabled by setting the toggle-select-enable bit (TSL -DPS.5) to a logic 1. Once enabled, the SEL bit is automatically toggled after the execution of one of the following five DPTR-related instructions: INC DPTR MOV DPTR #data16 MOVC A, @A+DPTR MOVX A, @DPTR MOVX @DPTR, A The DS89C420 also offers a progra mmable option that automatically increases (or decreases) the contents of the selected data pointer by 1 after the execution of a DPTR-related instruction. The actual function (increment or decrement) is dependent upon the setting of the ID1 and ID0 bits. This option is enabled by setting the automatic increment/decrement enable (AID-DPS.4) to a logic 1 and is affected by one of the following three instructions: MOVC A, @A+DPTR MOVX A, @DPTR MOVX @DPTR, A

basic external memory cycle contains four system clocks for non-page mode operation. memory bus cycle. CKCON (8Eh) provides an applic ation-selectable stretch value for this purpose. Software can change the stretch value dynamically by changing the setting of CKCON.2–CKCON.0. cycle always contains four system clocks. Table 6. Data Memory Cycle Stretch Values on external data memory access and a MOVX instruction is completed in two basic memory cycles. (stretch value = 4) when the system clock is in divide by one mode (CD1:CD0 = 10b).

cycles. Additionally, the functions of ALE and PSEN are altered to support this mode of operation. selects another bus structure. Write access to the ACON register requires a timed access. Table 7. Page Mode Select the upper byte and lower byte of the address. the upper byte and lower byte of the address. the upper byte and lower byte of the address.

The first page mode (page mode 1) external bus structure uses P2 as the primary address bus, (multiplexing both the most significant byte (MSB) and least significant byte (LSB) of the address for each external memory cycle) and P0 is used as the primary data bus. During external code fetches, P0 is held in a high-impedance state by the processor. Op codes are driven by the external memory onto P0 and latched at the end of the external fetch cycle at the rising edge of PSEN . During external data read/write operations, P0 functions as the data I/O bus. It is held in a high-impedance state for external reads from data memory, and driven with data during external writes to data memory. /g167 A page miss occurs when the MSB of the subsequent address is different from the last address. The external memory machine cycle can be 2, 4, or 8 system clocks in length for a page miss. /g167 A page hit occurs when the MSB of the subsequent address does not change from the last address. The external memory machine cycle can be 1, 2, or 4 system clocks in length for a page hit. During a page hit, P2 drives Addr0–7 of the 16-bit address while the most significant address byte is held in the external address latches. PSEN , RD , and WR strobe accordingly for the appropriate operation on the P0 data bus. There is no ALE assertion for page hits. During a page miss, P2 drives the Addr [8:15] of the 16-bit address and holds it for the duration of the first half of the memory cycle to allow the external address latches to latch the new most significant address byte. ALE is asserted to strobe the external address latches. During this operation, PSEN , RD , and WR are all held in inactive states and P0 is in a high-impedance state. The second half of the memory cycle is executed as a page-hit cycle and the appropriate operation takes place. A page miss can occur at set intervals or during external operations that require a memory access into a page of memory that has not been accessed during the last external cycle. Generally, the first external memory access causes a page miss. The new page address is stored internally, and is used to detect a page miss for the current external memory cycle. Note that there are a few exceptions for this mode of operation when PAGES1 and PAGES2 are set to 00b: /g167 PSEN is asserted for both page hit and page miss for a full clock cycle. /g167 The execution of external MOVX instruction causes a page miss. /g167 A page miss occurs when fetching the next external instruction following the execution of an external MOVX instruction. Figure 7 shows the external memory cycle for this bus structure. The first case illustrates a back-to-back execution sequence for 1-cycle page mode (PAGES1 = PAGES0 = 0b). PSEN remains active during page hit cycles, and page misses are forced durin g and after MOVX executions, independent of the most significant byte of the subsequent addresses. The second case illustrates a MOVX execution sequence for 2-cycle page mode (PAGES1 = 0 and PAGES0 = 1). PSEN is active for a full clock cycle in code fetches. Note that the page misses in this sequence are caused by changing the MSB of the data address. The third case illustrates a MOVX execution sequenc e for 4-cycle page mode (PAGES1 = 1 and PAGES0 = 0). There is no page miss in this execution cycle because the most significant byte of the data address is assumed to match the last program address.

for the different signals on P0 and P2. Figure 8 illustrates the memory cycle for external code fetches. Figure 7. Page Mode 1, External Memory Cycle (CD1:CD0 = 10)

Figure 8. Page Mode 2, External Code Fetch Cycle (CD1:CD0 = 10) four system clocks, independent of the logic value of the page mode select bits. Table 8. Page Mode 1, Data Memory Cycle Stretch Values

Table 9. Page Mode 1, Data Memory Cycle Stretch Values Table 10. Page Mode 1, Data Memory Cycle Stretch Values

Table 11. Page Mode 2, Data Memory Cycle Stretch Values data hold time. When using very slow RAM and peripherals, a larger stretch value (4–7) can be selected. stretched by one stretch cycle for page miss) and one stretch cycle is used to create additional hold time.

The DS89C420 provides 13 interrupt vector sources. All interrupts, with the exception of the power-fail, are controlled by a series combinati on of individual enable bits and a global enable (EA) in the interrupt enable register (IE.7). Setting EA to a logic 1 allows individual interrupts to be enabled. Setting EA to a logic 0 disables all interrupts regardless of the individual interrupt enab le settings. The power-fail interrupt is controlled by its individual enable only. The interrupt enables and priorities are functionally identical to those of the 80C52, except that the DS89C420 supports five levels of interrupt priorities instead of the original two. Interrupt Priority There are five levels of interrupt priority: level 4 to 0. The highest interrupt priority is level 4, which is reserved for the power-fail interrupt. All other interrupts have individual priority bits in the interrupt priority registers to allow each interrupt to be assigned a priority level from 3 to 0. The power-fail interrupt always has the highest priority if it is enabled. All interrupts also have a natural hierarchy. In this manner, when a set of interr upts has been assigned the same priority, a second hierarchy determines which interrupt is allowed to take precedence. The natural hierarchy is determined by analyzing potential interrupts in a sequential manner with the order listed in Table 12.

Table 12. Interrupt Summary *Cleared automatically by hardware when the service routine is vectored to. the flag follows the state of the pin. must be cleared by software. oscillator cycles. Table 13 summarizes the timer functions.

map as TL0, TH0, TL1, and TH1. Timers 0 and 1 are enabled by the timer control (TCON) register. Table 13. Timer Functions

• 8-bit timer/counter includes auto-reload feature; 2 x 8-bit mode does not.

is selected by the T2MOD register. time base is fixed at divide by 2, regardless of the setting of its timer mode bits.

The timed access function provides c ontrol verification to system functions. The timed access function prevents an errant CPU from making accidental changes to certain SFR bits that are considered vital to proper system operation. This is achieved by using software control when accessing the following SFR control bits: WDCON.0 RWT Reset Watchdog Timer WDCON.1 EWT Watchdog Reset Enable WDCON.3 WDIF Watchdog Interrupt Flag WDCON.6 POR Power-On Reset Flag EXIF.0 BGS Bandgap Select ACON.5 PAGES0 Page Mode Select Bit 0 ACON.6 PAGES1 Page Mode Select Bit 1 ACON.7 PAGEE Page Mode Enable ROMSIZE.0 RMS0 Program Memory Size Select Bit 0 ROMSIZE.1 RMS1 Program Memory Size Select Bit 1 ROMSIZE.2 RMS2 Program Memory Size Select Bit 2 ROMSIZE.3 PRAME Program RAM Enable FCNTL.0 FC0 Flash Command Bit 0 FCNTL.1 FC1 Flash Command Bit 1 FCNTL.2 FC2 Flash Command Bit 2 FCNTL.3 FC3 Flash Command Bit 3 Before these bits can be altered, the processor must execute the timed access sequence. This sequence consists of writing an AAh to the timed access (TA, C7h) register, followed by writing a 55h to the same register within three machine cycles. This timed sequence of steps then allows any of the timed access- protected SFR bits to be altered during the thre e machine cycles, following the writing of the 55h. Writing to a timed access-protected bit outside of these three machine cycles has no effect on the bit. The timed access process is address- , data-, and time-dependent. A pro cessor running out of control and not executing system software cannot statistically perform this timed sequence of steps, and as such, will not accidentally alter the protected bits. It should be noted that this method should be used in the main body of the system software and never used in an interrupt routine in conjunction with the watchdog reset. Interrupt routines using the timed-access watchdog-reset bit (RWT) can recover a lost system and allow the resetting of the watchdog, but the system returns to a lost condition once the RETI is executed, unless the stack is modified. It is advisable that interrupts be disabled (EA = 0) when executing the timed access sequence, since an interrupt during the sequence adds time, making the timed access attempt fail.

Power Management and Clock-Divide Control The DS89C420 incorporates power ma nagement features that monitor the power-supply voltage levels and support low-power opera tion with three power-saving modes. Such features include a bandgap voltage monitor, watchdog timer, selectable internal ring oscillator, and programmable system clock speed. The SFRs that provide control and application software access are the watchdog control (WDCON, D8h), extended interrupt enable (EIE, E8h) , extended interrupt flag (EXIF, 91h), and power control (PCON, 87h) registers. System Clock-Divide Control The programmable clock-divide control bits (CD1 and CD0) provide the processor with the ability to adapt to different crystals and also to slow the system clocks providing lower power operation when required. An on-chip crystal multiplier allows the DS89C420 to operate at two or four times the crystal frequency by setting the 4X/ X2 bit and is enabled by setting the CTM bit to a logic 1. An additional circuit provides a clock source at divide-by-1024. When used with a 7. 372MHz crystal, for example, the processor executes machine cycle in times ranging fr om 33.9ns (divide-by-0.25) to 138.9µs (multiply by 1024), and maintains a highly accurate serial port baud rate while allowing the use of more cost-effective, lower-frequency crystals. Although the clock-divide control bits can be written at any time, certain hardware features have been provided to enhance th e use of these clock controls to guarantee proper serial port operation, and also to allow for a high-speed response to an external interrupt. The 01b setting of CD1 and CD0 is reserved, and has the same effect as the 10b setting, which forces the system clock into a divide by 1 mode. The DS89C420 defaults to divide-by-1 clock mode on all forms of reset. When programmed to the divide-by-1024 mode, and th e switchback bit (PMR.5:SWB) is also set, the system forces the clock-divide control bits to reset automatically to the divide-by-1 mode whenever the system has detected externally enabled interrupts. The oscillator divide ratios of 0.25, 0.5, and 1 are al so used to provide standard baud-rate generation for the serial ports through a forced divide-by-12 input clock (TxMH, TxM = 00b, x = 1, 2, or 3) to the timers. When in divide-by-1024 mode, in order to allow a quick response to incoming data on a serial port, the system uses the switchback mode to automatically revert to divide-by-1 mode whenever a start bit is detected. This automatic switchback is only enab led during divide-by-1024 mo de, and all other clock modes are unaffected by interrupts and serial port activity. See Power Management Mode for more details. Use of the divide-by-0.25 or 0.5 options through the clock-divide control bits requires that the crystal multiplier be enabled and the specific system-clock-multiply value be established by the 4X/ X2 bit in the PMR register. The multiplier is enabled through the CTM (PMR.4) bit but cannot be automatically selected until a startup delay has been established through the CKRY bit in the status register. The 4X/ X2 bit can only be altered when the CTM bit is cleared to a logic 0. This prevents the system from changing the multiplier until the system has moved back to the divide by 1 mode and the multiplier has been disabled through the CTM bit. The CTM bit can only be altered when the CD1 and CD0 bits are set to divide-by-1 mode and the RGMD bit is cleared to 0. Setting the CTM to a logic 1 from a previous logic 0 automatically clears the CKRY bit in the status register and starts the multiplier startup timeout in

power-fail comparator are powered up, although in a reduced fashion, while in stop mode. watchdog interrupt periods. Table 14 summarizes the watchdog bit settings and the timeout values. crystal multiplier settings. Table 14. Watchdog Timeout Value (in Number of Oscillator Clocks) One of the applications of the watchdog timer is for the watchdog to wake up the system from idle mode.

If the RST input is taken to a logic 1, the device is forced into a reset state. An external reset is accomplished by holding the RST pin high for at least 3 clock cycles while the oscillator is running. Once the reset state is invoked, it is maintained as long as RST is pulled to logic 1. When the RST is removed, the processor exits the reset state within 4 clock cycles and begins execution at address 0000h. If a RST is applied while the processor is in stop mode, the RST causes the oscillator to begin running and forces the program counter to 0000h. There is a reset delay of 65,536 clock cycles to allow the oscillator to stabilize. The RST pin is a bidirectional I/O. If a reset is caused by a power-fail reset, a watchdog timer reset, or an internal system reset, an output-reset pulse is also generated at the RST pin. This reset pulse is asserted as long as an internal reset is asserted and may not be able to drive the reset signal out if the RST pin is connected to an RC circuit. Connecting the RST pin to a capacitor does not affect the internal reset condition. Oscillator-Fail Detect The DS89C420 incorporates an oscillator fail-detect circuit that, when enabled, causes a reset if the crystal oscillator frequency falls below 20kHz and holds the chip in reset with the ring oscillator operating. The circuit is enabled by setting the OFDE (PCON.4) bit to a logic 1. The OFDE bit is only cleared from a logic 1 to a logic 0 by a power-fail reset or by software. A reset caused by an oscillator failure also sets the OFDF (PCON.5) to a logic 1. This flag is cleared by software or power-on reset. Note that this circuit does not force a reset when the oscillator is stopped by the software-enabled stop mode. Power Management Mode Power management mode offers a software-contro llable power-saving scheme by providing a reduced instruction cycle speed, which allows the DS89C420 to continue to operate wh ile using an internally divided version of the clock source to save power . Power management mode is invoked by software setting the clock-divide control bits CD1 and CD0 (PMR.7-6) bits to 11b, which sets an operating rate of 1024 oscillator cycles for 1 machine cycle. On all forms of reset, the clock-divide control bits default to 10b, which selects 1 oscillator cycle per machine cycle. Since the clock speed choice affects all functi onal logic including timers, the DS89C420 implements several hardware switchback features that allow the clock speed to automatically return to the divide-by-1 mode from a reduced cycle rate. This switchback function is enabled by setting the SWB (PMR.5) bit to a 1 in software. When CD1 and CD0 are programmed to the divide-by- 1024 mode and the SWB bit is also enabled, the system forces the clock-divide control bits to automatically reset to the divide-by-1 mode whenever the system detects an externally enabled (and allowed through nesting priorities) interrupt. The switchback occurs whenever one of the two conditions occur. The first switchback condition is initiated by the detection of a low on either 0INT , 1INT , 3INT , or 5INT , or a high on INT2 or INT4 when the respective pin has been programmed and allowed (through nesting priorities) to issue an interrupt. The second switchback condition occurs when either serial port is enabled to receive data and is found to have an active-low transition on the respective receive input pin. Serial port transmit activity also forces a

switchback if the SWB is set. Note that the seri al port activity, as related to the switchback, is independent of the serial port inte rrupt relationship. Any attempt to change the clock divider to the divide-by-1024 mode while the serial port is either transmitting or receiving has no effect, leaving the clock control in the divide-by-1 mode. Note also th at the switchback interrupt relationship requires that the respective external interrupt source is allowed to actually generate an interrupt as defined by the priority of the interrupt and the state of the nested interrupts, before the switchback can actually occur. An interrupt by the serial port is not required, nor is the setting of serial port enable. Disabling external interrupts and serial port receive/transmission mode disable the automatic switchback mode. Clearing the SWB bit also disables the switchback, and all interrupt and serial port controls of the clock divider are disabled. All other clock modes ig nore the switchback relationship and are unaffected by interrupts and serial port activity. The basic divide-by-12 mode for the timers (TxMH, TxM = 00b), as well as the divide-by-32 and 64 for mode 2 on the serial ports, are maintained when running the processor with the oscillator divide ratio of 0.25, 0.5, and 1. Serial ports and timers track the oscillator cycles per machine cycle when the higher divide ratio of 1024 is selected, and require the switchback function to automatically return to the divide-by-1 mode for proper operation when a qualif ied event occurs. Table 15 summarizes the effect of clock mode on timer operation. It is possible to enable a receive function on a seri al port when incoming data is not present and then change to the higher divide ratio. An inactive serial port receive/transmit mode requires the receive input pin to remain high and all outgoing transmissions to be completed. During this inactive receive mode it is possible to change the clock-divide control bits from a divide-by-1 to a 1024 divide ratio. In the case when the serial port is being used to receive or transmit data it is very important to validate an attempted change in the clock-divide control bits (read CD1 and CD0 to verify wr ite was allowed) before proceeding with low-power program functions.

Table 15. Effect of Clock Mode on Timer Operation (in Number of Oscillator external clock rate. It is not driven by the ring oscillator.

vector using the RETI instruction, the next address is the one that immediately follows the instruction that invoked the idle mode. Any processor resets also remove the idle mode. Stop Mode The stop mode disables all circuits within the processor. All on-chip clocks, timers, and serial port communication are stopped, and no processing is possible. Stop mode is invoked by setting the STOP bit (PCON.1) to logic 1. The processor enters the stop mode on the instruction that sets the bit. The processor can exit stop mode by using any of the six external interrupts that are enabled. An external reset by the RST pin unconditionally exits the processor from stop mode. If the BGS bit is set to logic 1, the bandgap provides a reset while in stop mode if V CC should drop below the V RST level. If BGS is 0, no reset is generated if VCC drops below VRST. When the stop mode is removed, the processor wa its for 65,536 clock cycles for the internal flash memory to warm up before starting normal execution. Also, the processor waits for the crystal warmup period if not using the ring oscillator. Serial I/O The DS89C420 provides a serial port (UART) that is identical to the 80C52. In addition, it includes a second hardware serial port that is a full duplicate of the standard one. This port optionally uses pins P1.2 (RXD1) and P1.3 (TXD1) and has duplicate control functions included in new SFR locations. Both ports can operate simultaneously but can be at di fferent baud rates or even in different modes. The second serial port has sim ilar control registers (SCON1 at C0h, SB UF1 at C1h) as the original. The new serial port can only use timer 1 for timer-generated baud rates. Control for serial port 0 is provided by the SCON0 register while its I/O buffer is SBUF0. Registers SCON1 and SBUF1 provide the same functions for the second serial port. A full description of the use and operation of both serial ports is in the Ultra-High-Speed Flash Microcontroller User’s Guide. Instruction Set The DS89C420 instructions are 100% binary compatib le with the industry standard 8051, and are only different in the number of machine cycles used for the instructions. Some special conditions and features should be considered when analyzing the DS89C420 instruction set. Full de tails are given in the Ultra- High-Speed Flash Microcontroller User’s Guide.

sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability. Table 16. DC ELECTRICAL CHARACTERISTICS

Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: Active current is measured with a 33MHz clock source driving XTAL1, VCC = RST = 5.5V. All other pins disconnected. Note 4: Idle mode current measured with a 33MHz clock source driving XTAL1, VCC = 5.5V, RST at ground. All other pins disconnected. Note 5: Stop mode measured with XTAL and RST grounded, VCC = 5.5V. All other pins disconnected. Note 6: When addressing external memory. Note 7: RST = 5.5V. This condition mimics the operation of pins in I/O mode. Note 8: During a 0-to-1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects a port pin in transition mode. Note 9: Ports 1, 2, and 3 source transition current when being pulled down externally. The current reaches its maximum at approximately 2V. Note 10: This port is a weak address holding latch in bus mode. Peak current occurs near the input transition point of the holding latc h at approximately 2V. Note 11: RST = 5.5V. Port 0 floating during reset and when in the logic-high state during I/O mode. Note 12: While the specifications for VPFW and VRST overlap, the design of the hardware makes it such that this is not possible. Within the ranges given, there is a guaranteed separation between these two voltages. Note 13: The user should note that this part is tested and guaranteed to operate down to 4.5V (10%) and that VRST (min) is specified below that point. This indicates that there is a range of voltages [V MIN to V RST (min)] where the processor’s operation is not guaranteed, but the reset trip point has not been reached. This should not be an issue in most applications, but should be considered when proper operation must be maintained at all times. For these applications, it may be desirable to use a more accurate external reset. Note 14: Guaranteed by design.

Table 17. AC CHARACTERISTICS

1 CYCLE

2 CYCLE

4 CYCLE

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES PSEN Low to Valid Instruction In tPLIV tCLCL - 18 t CLCL - 18 2t CLCL - 18 t CLCL - 18 2t CLCL - 18 ns Input Instruction Hold After PSEN tPXIX 000 0 0 n s Input Instruction Float After PSEN tPXIZ tCLCL - 5 t CLCL - 5 ns Port 0 Address to Valid Instruction In t AVIV0 1.5tCLCL - 20 3t CLCL - 20 ns Port 2 Address to Valid Instruction In tAVIV2 tCLCL - 18 1.5t CLCL - 18 2.5t CLCL - 18 3t CLCL - 20 3.5t CLCL - 20 ns PSEN Low to Port 0 Address Float tPLAZ 00 n s RD Pulse Width (P3.7) t RLRH tCLCL - 5 + tSTC1 tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 ns 2 WR Pulse Width (P3.6) t WLWH tCLCL - 5 + tSTC1 tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 2tCLCL - 5 + tSTC1 ns 2 RD (P3.7) Low to Valid Data In tRLDV tCLCL - 15 + tSTC1 tCLCL - 15 + tSTC1 2tCLCL - 15 + tSTC1 2tCLCL - 15 + tSTC1 2tCLCL - 15 + tSTC1 ns 2 Data Hold After RD (P3.7) t RHDX 000 0 0 n s Data Float After RD (P3.7) t RHDZ tCLCL - 5 t CLCL - 5 ns MOVX ALE Low to Input Data Valid t LLDV 2.5tCLCL - 20 + tSTC1 2.5tCLCL - 20 + tSTC1 ns 2 Port 0 Address to Valid Data In t AVDV0 3tCLCL - 20 + tSTC1 3tCLCL - 20 + tSTC1 ns 2

MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES Port 2 Address to Valid Data In tAVDV2 tCLCL - 16 + tSTC1 1.5tCLCL - 16 + tSTC1 3.5tCLCL - 16 + tSTC1 3.0tCLCL - 16 + tSTC1 3.5tCLCL - 20 + tSTC1 ns 2 ALE Low to RD or WR Low tLLRL (tLLWL) 0.5tCLCL - 8 + tSTC2 0.5tCLCL + 1 + tSTC2 2tCLCL - 8 + tSTC2 2tCLCL + 8 + tSTC2 4tCLCL - 8 + tSTC2 4tCLCL + 8 + tSTC2 0.5tCLCL - 8 + tSTC2 0.5tCLCL + 4 + tSTC2 0.5tCLCL - 8 + tSTC2 0.5tCLCL + 4 + tSTC2 ns 2 Port 0 Address Valid to RD or WR Low tAVRL0 (tAVWL0) 1.5tCLCL - 5 + tSTC2 tCLCL - 5 + tSTC2 ns 2 Port 2 Address Valid to RD or WR Low tAVRL2 (tAVWL2) 0 + tSTC5 - 5 0.5tCLCL - 5 + tSTC5 1.5tCLCL - 5 + tSTC5 tCLCL - 5 + tSTC5 1.5tCLCL - 5 + tSTC5 ns 2 Data Out Valid to WR Transition tQVWX -5 -5 -5 -5 -5 ns 1 Data Hold After WR tWHQX 20 20 20 20 20 ns 1 RD or WR High to ALE High tRHLH (tWHLH) tSTC2 - 2 t STC2 + 6 t STC2 - 2 t STC2 + 6 t STC2 - 2 t STC2 + 6 t STC2 - 2 t STC2 + 6 t STC2 - 2 t STC2 + 6 ns 1 *Specifications to -40°C are guaranteed by design and not production tested.

Note 1: The system clock frequency is dependent on the oscillator frequency and the setting of the clock-divide control bits (CD1 and C D0) and the crystal multiplier control bits (4X/ X2 and CTM) in the PMR register. The term “1 / t CLCL” used in the variable timing table is calculated through the use of the table given below. 4X/ X2 CD1 CD0 NUMBER OF OSCILLATOR CYCLES PER SYSTEM CLOCK (1 / tCLCL) 1 0 0 4 Oscillator Cycles 0 0 0 2 Oscillator Cycles X 0 1 Reserved X 1 0 1 Oscillator Cycle X 1 1 1 / 1024 Oscillator Cycle Note 2: External MOVX instruction times are dependent on the setting of the MD2, MD1, and MD0 bits in the clock control register. The t erms “tSTC1, tSTC2, tSTC3” used in the variable timing table are calculated through the use of the table given below. MD2 MD1 MD0 MOVX INSTRUCTION TIME (MACHINE CYCLES) tSTC1 (tCLCL) tSTC2 (tCLCL) tSTC3 (tCLCL) tSTC4 (tCLCL) tSTC5 (tCLCL) 0 0 0 2 0 0000 0 0 1 3 2 1001 0 1 0 4 6 1001 0 1 1 5 1 01001 1 0 0 9 1 45411 1 0 1 10 18 5 4 1 1 1 1 0 1 1 2 25411 1 1 1 1 2 2 65411 Note 3: Maximum load capacitance (to meet the above timing) for Port 0, ALE, PSEN , WR , and RD is limited to 60pF. Port 1, 2, 3, and 4 (except for P3.6, WR and P3.7, RD ) are tested with a capacitance of 50pF. XTAL1 and XTAL2 load capacitance is dependent on the frequency of the selected crystal.

Figure 12. Non-Page Mode Timing

EXTERNAL CLOCK CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = -40°C to +85°C)* PARAMETER SYMBOL MIN MAX UNITS Clock High Time t CHCX 10 ns Clock Low Time t CLCX 10 ns Clock Rise Time t CLCH 5 ns Clock Fall Time t CHCL 5 ns *Specifications to -40°C are guaranteed by design and not production tested. SERIAL PORT MODE 0 TIMING CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = -40°C to +85°C)* 33MHz VARIABLE PARAMETER SYMBOL MIN MAX MIN MAX MAX Clock Cycle Time SM2 = 0 360 12tCLCL SM2 = 1 tXLXL 120 4t CLCL ns Output Data Setup to Clock Rising SM2 = 0 200 10tCLCL - 100 ns SM2 = 1 tQVXH 40 3t CLCL - 10 Output Data Hold to Clock Rising SM2 = 0 2tCLCL - 10 SM2 = 1 tXHQX 20 t CLCL - 100 ns Input Data Hold after Clock Rising SM2 = 0 SM2 = 1 tXHDX 0 0 ns Clock Rising Edge to Input Data Valid SM2 = 0 200 10tCLCL - 100 SM2 = 1 tXHDV 40 3t CLCL - 50 ns *Specifications to -40°C are guaranteed by design and not production tested. Note: SM2 is the serial port 0, mode bit 2. When serial port 0 is operating in mode 0 (SM0 = SM1 = 0), SM2 determines the number of c rystal clocks in a serial-port clock cycle.

Figure 15. Serial Port Timing

POWER CYCLE TIMING CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = -40°C to +85°C) (Note 1) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Crystal Startup Time t CSU 8m s 2 Power-On Reset Delay t POR 65,536 t CLCL 3 Note 1: Specifications to -40°C are guaranteed by design and not production tested. Note 2: Startup time for a crystal varies with load capacitance and manufacturer. Time shown is for a 11.0592MHz crystal manufactured by Fox Electronics. Note 3: Reset delay is a synchronous counter of crystal oscillations after crystal startup. Counting begins when the level on the XTAL1 pin meets the VIH2 criteria. At 33MHz, this time is 1.99ms. FLASH MEMORY PROGRAMMING CHARACTERISTICS (VCC = 4.5V to 5.5V; TA = +21°C to +27°C) PARAMETER SYMBOL MIN TYP MAX UNITS Oscillator Frequency 1 / tCLCL 46 M H z Address Setup to PROG Low tAVGL 48tCLCL Address Hold After PROG tGHAX 48tCLCL Data Setup to PROG Low tDVGL 48tCLCL Data Hold After PROG tGHDX 48tCLCL PROG Pulse Width tGLGH 85 100 /g109s Address to Data Valid tAVQV 48tCLCL Enable Low to Data Valid tELQV 48tCLCL Data Float After Enable tEHQZ 0 48t CLCL PROG High to PROG Low tGHGL 10 /g109s

40-PIN PDIP (600MIL) PKG 40-PIN DIM MIN MAX A — 0.200 A1 0.015 — A2 0.140 0.160 b 0.014 0.022 c 0.008 0.012 D 1.980 2.085 E 0.600 0.625 E1 0.530 0.555 e 0.090 0.110 L 0.115 0.145 eB 0.600 0.700 56–G5000–000 Dimensions are in inches (in).

Note 1: Pin 1 identifier to be located in zone indicated. Note 2: Controlling dimensions are in inches (in).

PART TEMP RANGE MAX. CLOCK SPEED (MHz) PIN-PACKAGE DS89C420-MCL 0°C to +70°C 33 40 PDIP DS89C420-QCL 0°C to +70°C 33 44 PLCC DS89C420-ECL 0°C to +70°C 33 44 TQFP DS89C420-MNL -40°C to +85°C 33 40 PDIP DS89C420-QNL -40°C to +85°C 33 44 PLCC DS89C420-ENL -40°C to +85°C 33 44 TQFP 61 4 0 18 28 73 9 17 29 DS89C420 TOP VIEW PLCC 33 23 11 1 34 22 44 12 DS89C420 TOP VIEW TQFP

REVISION HISTORY

1) Original issue, 092200. 2) Added errata, 122601. (See www.maxim-ic.com/errata for more details.) 3) Official product introduction release, 042702. 4) Inserted Table 17, 051302. 5) Removed (Min Operating Voltage) from DC Electrical Characteristics; inserted diagram of ROM loader interface circuit, 103102.