DS8007-ENG

DS8007 DALLAS | Alldatasheet

Document overview

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Technical content

Features

♦ Complete Interface/Control for Two Separate Smart Card Devices ♦ 8kV (min) ESD Protection on Card Interfaces ♦ Internal IC Card Supply Voltage Generation 5.0V ±5%, 65mA (max) 3.0V ±8%, 50mA (max) 1.8V ±10%, 30mA (max) ♦ Automatic Card Activation, Deactivation, and Data Communication Controlled by Dedicated Internal Sequencer ♦ Host Interface Through an 8-Bit Parallel Bus (User- Selectable Multiplexed or Nonmultiplexed Modes) ♦ Chip Select and Tri-State Bus Allow Multiple Devices (Card Readers and Memories) on Bus ♦ 8-Character Receive FIFO with Optional Programmable Depth/Threshold ♦ I/O Interface Pin to External ISO 7816 UART ♦ Separate Card Clock Generation (Up to 10MHz) with 2x Frequency Doubling ♦ Selectable Card Clock STOP HIGH, STOP LOW, or Internally Generated 1.25MHz (for Card Power- Down) ♦ EMV-Certified Reference Design and Evaluation Kit Available (DS8007-KIT) DS8007 Multiprotocol Dual Smart Card Interface RD V DD CPA2 AGND RSTOUT I/OAUX I/OA C8A PRESA C4A GNDA CLKA V CCA RSTA I/OB C8B PRESB C4B GNDB CLKB VCCB RSTB GND VUP CPA1 CPB1 VDDA CPB2 DELAY XTAL1 XTAL2 AD0 AD1 AD2 AD3 INTAUX INT ALE CS WR LQFP DS8007 Pin Configuration Rev 1; 10/07 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. EVALUATION KIT AVAILABLE

Ordering Information

Typical Operating Circuit appears at end of data sheet. PART TEMP RANGE SMART CARDS SUPPORTED PIN- PACKAGE DS8007-ENG -40°C to +85°C 2 + auxiliary 48 LQFP DS8007-ENG+ -40°C to +85°C 2 + auxiliary 48 LQFP + Denotes a lead-free/RoHS-compliant device. EMV is a trademark owned by EMVCo LLC. MAXQ is a registered trademark of Maxim Integrated Products, Inc. Note: Some revisions of this device may incorporate devia- tions from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.

Multiprotocol Dual Smart Card Interface ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD = +3.3V, VDDA = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on Any Pin Relative to Ground J-STD-020 Specification PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Digital Supply Voltage V DD 2.7 6.0 V Step-Up Converter Supply Voltage VDDA VDD 6.0 V Cards Inactive f XTAL = 0MHz 0.9Power-Down VDD Current Cards Active IPD fXTAL = 0MHz, fCLK = 0MHz, VCCx = 5V 2.2 mA Sleep Mode VDD Current (Cards Active) ISTOP fCLK = 0MHz, VCC = 5V 24 mA Active VDD Current 5V Cards IDD 3x VDD step-up: ICCA + ICCB = 80mA, VDD = 2.7V, fXTAL = 20MHz, fCLK = 10MHz 325 mA 2x VDD step-up: ICC1 + ICC2 = 80mA, fXTAL = 20MHz, fCLK = 10MHz, VDD = 2.7V 225 Active VDD Current 3V Cards IDD No step-up: ICC1 + ICC2 = 80mA, fXTAL = 20MHz, fCLK = 10MHz, VDD = 5V 120 mA VRST Threshold voltage (falling) 2.1 2.5 VPower-Fail Reset Voltage VHYS Hysteresis 50 170 mV Reset Threshold VDRST 1.25 Output Voltage V DO VDD + 0.3 V VDELAY = 0V -2 µAOutput Current I DO VDELAY = VDD +2 mA Delay Pin Output Capacitance CDO 1n F RSTOUT PIN Output High Voltage V OHRSTO IOH = -1mA 0.8 x VDD VDD + 0.3 V Output Low Voltage V OLRSTO IOL = 2mA -0.3 +0.4 V Leakage Current I L VOL = 0V, VOH = 5V -10 +10 µA

Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, VDDA = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Alarm Pulse Width t W CDELAY = 22nF 10 ms External crystal 4 20External Clock Frequency f XTAL External oscillator 0 20 MHz Internal Oscillator f INT 1.6 2.5 3.7 MHz 3x step-up 5.7Voltage on VUP Pin V UP 2x step-up 4.1 V Voltage Detection of VDDA for 2x, 3x Step-Up VDET 3.35 3.50 3.60 V Shutdown Temperature T SD +150 °C Output Low Voltage VOLRST IOLRST = 1mA 0 0.3 VCard Inactive Mode Output Current I OLRST VOLRST = 0V 0 -1 mA Output Low Voltage VOLRSTL IOLRST = +200µA 0 0.3 Output High Voltage VOHRSTH IOHRST = -200µA VCC –

0.5 VCC

V Rise Time t RRST CL = 30pF 0.1 Fall Time t FRST CL = 30pF 0.1 µs Shutdown Current IRST(SD) -25 RSTx Pins Card Active Mode Current Limitation IRST(LIMIT) -25 +25 mA Output Low Voltage VOLCLK IOLCLK = 1mA 0 0.3 VCard Inactive Mode Output Current I OLCLK VOLCLK = 0V 0 -1 mA Output Low Voltage VOLCLK IOLCLK = +200µA 0 0.3 Output High Voltage VOHCLK IOHCLK = -200µA VCC – V Rise Time t RCLK CL = 30pF (Note 2) 8 Fall Time t FCLK CL = 30pF (Note 2) 8 ns Card Active Mode Current Limitation ICLK(LIMIT) -70 +70 mA Idle configuration (1MHz) 1 1.85 CLKx Pins Clock Frequency f CLK Operational 0 10 MHz Duty Factor δ CL = 30pF 45 55 %

Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, VDDA = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Low Voltage VCC ICC = 1mA 0 0.3 VCard Inactive Mode Output Current I CC VCC = 0V 0 -1 mA ICC(5V) < 65mA 4.75 5.00 5.25 ICC(3V) < 50mA 2.78 3.00 3.22 ICC(1.8V) < 30mA 1.65 1.80 1.95 5V card, current pulses of 40nC with I < 200mA, t < 400ns, f < 20MHz 4.6 5.4 3V card, current pulses of 24nC with I < 200mA, t < 400ns, f < 20MHz 2.75 3.25 Output Low Voltage VCC 1.8V card, current pulses of 12nC with I < 200mA, t < 400ns, f < 20MHz 1.62 1.98 V VCC(5V) = 0 to 5V -65 VCC(3V) = 0 to 3V -50Output Current I CC VCC(1.8V) = 0 to 1.8V -30 Total Current (Two Cards) ICC(A+B) -80 Shutdown Current ICC(SD) -100 mA VCCx Pins Card Active Mode Slew Rate V CCSR Up/down, C < 300nF (Note 3) 0.05 0.16 0.05 V/µs Output Low Voltage VOLIO IOLIO = 1mA 0 0.3 V Output Current I OLIO VOLIO = 0V 0 -1 mA Card Inactive Mode Internal Pullup Resistor RPULLUP To VCCx 91 4 1 9 k Ω Output Low Voltage VOLIO IOLIO = 1mA 0 0.3 IOHIO ≤ -20µA 0.8 x V CC VCCOutput High Voltage VOHIO IOHIO ≤ -40µA (3V/5V) 0.75 x V CC VCC V Output Rise/Fall Time tOT CL = 30pF 0.1 µs Input Low Voltage VILIO -0.3 +0.8 Input High Voltage VIHIO 1.5 V CC V Input Low Current IILIO VILIO = 0V 700 Input High Current IIHIO VIHIO = VCC 20 µA Input Rise/Fall Time tIT CL = 30pF 1.2 µs I/Ox Pins Card Active Mode Current Limitation IIO(LIMIT) -25 +25 mA

Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, VDDA = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Low Voltage VOLC48 IOLC48 = 1mA 0 0.3 V Output Current I OLC48 VOLC48 = 0V 0 -1 mA Card Inactive Mode Internal Pullup Resistor RPULLUP Between C4 or C8 and VCCx 61 0 1 4 k Ω Output Low Voltage VOLC48 IOLC48 = 1mA 0 0.3 IOHC48 ≤ -20µA 0.8 x V CC VCCOutput High Voltage VOHC48 IOHC48 ≤ -40µA (3V/5V) 0.75 x V CC VCC V Output Rise/Fall Time tOT CL = 30pF 0.1 µs Input Low Voltage VILC48 -0.3 +0.8 Input High Voltage VIHC48 1.5 V CC V Input Low Current IILC48 VILIO = 0V 850 Input High Current IIHC48 VIHIO = VCC 20 µA Input Rise/Fall Time tIT CL = 30pF 1.2 µs Pullup Pulse Width tWPU Active pullup 200 ns C4x, C8x Pins Card Active Mode Operating Frequency fMAX On card contact pins 1 MHz TIMING Activation Sequence Duration t ACT See Figure 9 130 µs Deactivation Sequence Duration t DE See Figure 9 150 µs PRESA/PRESB PINS Input Low Voltage V ILPRES 0.25 x VDD V Input High Voltage V IHPRES 0.7 x VDD V Input Low Current I ILPRES VILPRES = 0V 40 µA Input High Current I IHPRES VIHPRES = VDD 40 µA I/OAUX PIN Internal Pullup Resistor R PULLUP Between I/OAUX and VDD 91 4 1 9 k Ω Output Low Voltage V OLAUX IOLAUX = 1mA 0.3 V Output High Voltage V OHAUX IOHAUX = 40µA (3V/5V) 0.75 x V DD VDD V Output Rise/Fall Time t OT CL = 30pF 0.1 µs

Multiprotocol Dual Smart Card Interface ELECTRICAL CHARACTERISTICS (continued) (VDD = +3.3V, VDDA = +3.3V, TA = +25°C, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Low Voltage V ILAUX -0.3 0.3 x VDD V Input High Voltage V IHAUX 0.7 x VDD VDD V Input Low Current I ILAUX VILAUX = 0V 700 µA Input High Current I IHAUX VIHIO = VDD -20 +20 µA Input Rise/Fall Time t IT CL = 30pF 1.2 µs INTERRUPT PIN Output Low Voltage V OLINT IOH = 2mA 0.3 V Input High Leakage Current I LIHINT 10 µA D7 TO D0, ALL OTHER LOGIC PINS Output Low Voltage V OLD IOLD = +5mA 0.2 x VDD V Output High Voltage V OD IOHD = -5mA 0.8 x VDD VDD V Output Rise/Fall Time t OT CL = 50pF 25 ns Input Low Voltage V ILD 0.3 x VDD V Input High Voltage V IHD 0.7 x VDD V Input Low Current I ILD -20 +20 µA Input High Current I IHD -20 +20 µA Load Capacitance C LD 10 pF Note 1: Operation guaranteed at -40°C and +85°C but not tested. Note 2: Parameters are guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the maxi- mum rise and fall time is 10ns. Note 3: Parameter is guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the minimum slew rate is 0.05V/µs and the maximum slew rate is 0.5V/µs.

Figure 1. Multiplexed Parallel Bus Timing

Figure 2. Nonmultiplexed Parallel Bus Timing (Read and Write)

Figure 3. Timing Between Two Read Operations in Register URR of CS/WR instead of the falling edge. Note 5: PSC is the programmed prescaler value (31 or 32).

Multiprotocol Dual Smart Card Interface Pin Description PIN NAME FUNCTION

1 RSTOUT

Reset Output. This active-high output is provided for resetting external devices. The RSTOUT pin is driven high until the DELAY pin reaches VDRST. Once the DELAY pin reaches VDRST, the RSTOUT pin is tri-stated so it can externally be pulled down. The SUPL bit is set for each RSTOUT pulse. 2 I/OAUX Auxiliary I/O. This I/O pin allows connection to an auxiliary smart card interface. 3 I/OA Smart Card A I/O Data Line. This is the I/O data line associated with smart card A. This is also referred to as the ISO C7 contact. 4 C8A Smart Card A Auxiliary I/O. This is an auxiliary I/O associated with smart card A. This is also referred to as the ISO C8 contact. This can be associated with synchronous cards. 5 PRESA Smart Card A Presence Contact. This is the active-high presence contact associated with smart card A. 6 C4A Smart Card A Auxiliary I/O. This is an auxiliary I/O associated with smart card A. This is also referred to as the ISO C4 contact. This can be associated with synchronous cards. 7 GNDA Smart Card A Ground. This must be connected to GND. 8 CLKA Smart Card A Clock Output. This is the clock output associated with smart card A. This is also referred to as the ISO C3 contact. 9V CCA Smart Card A Supply Voltage. This is the supply voltage output associated with smart card A. This is also referred to as the ISO C1 contact. 10 RSTA Smart Card A Reset. This is the reset output associated with smart card A. This is also referred to as the ISO C2 contact. 11 I/OB Smart Card B I/O Data Line. This is the I/O data line associated with smart card B. This is also referred to as the ISO C7 contact. 12 C8B Smart Card B Auxiliary I/O. This is an auxiliary I/O associated with smart card B. This is also referred to as the ISO C8 contact. This can be associated with synchronous cards. 13 PRESB Smart Card B Presence Contact. This is the active-high presence contact associated with smart card B. 14 C4B Smart Card B Auxiliary I/O. This is an auxiliary I/O associated with smart card B. This is also referred to as the ISO C4 contact. This can be associated with synchronous cards. 15 GNDB Smart Card B Ground. This must be connected to GND. 16 CLKB Smart Card B Clock Output. This is the clock output associated with smart card B. This is also referred to as the ISO C3 contact.

17 V CCB

Smart Card B Supply Voltage. This is the supply voltage output associated with smart card B. This is also referred to as the ISO C1 contact. 18 RSTB Smart Card B Reset. This is the reset output associated with smart card B. This is also referred to as the ISO C2 contact.

19 GND Ground

20 V UP Step-Up Converter Connection. Connect a low-ESR capacitor of 220nF between this pin and ground.

Multiprotocol Dual Smart Card Interface Pin Description (continued) PIN NAME FUNCTION 21 CPA1 Step-Up Converter Contact 1. Connect a low-ESR capacitor of 220nF between CPA1 and CPA2. 22 CPB1 Step-Up Converter Contact 3. Connect a low-ESR capacitor of 220nF between CPB1 and CPB2.

23 V DDA

Analog Supply Voltage. Positive analog-supply voltage for the step-up converter; can be higher but not lower than VDD. This pin should be decoupled to AGND with a good quality capacitor. 24 CPB2 Step-Up Converter Contact 4. Connect a low-ESR capacitor of 220nF between CPB1 and CPB2.

25 AGND Analog Ground

26 CPA2 Step-Up Converter Contact 2. Connect a low-ESR capacitor of 220nF between CPA1 and CPA2. 27 V DD Digital Supply Voltage. This pin should be decoupled to GND with a good quality capacitor. 28–35 D0–D7 8-Bit Digital I/O. This port functions as the data or address/data communication lines between the host controller and the DS8007 for the nonmultiplexed and multiplexed operating modes, respectively. 36 RD Active-Low Parallel Bus Read Strobe Input. In multiplexed mode, this input indicates when the host processor is reading information from the DS8007. In nonmultiplexed mode, this pin signals the current operation is a read (RD = 1) or a write (RD = 0) when CS and WR are low. 37 WR Active-Low Parallel Bus Write Strobe Input. In multiplexed mode, this input indicates when the host processor is writing information to the DS8007. In nonmultiplexed mode, a low on this pin signals the bus is engaged in a read or write operation. 38 CS Active-Low Chip-Select Input. This input indicates when the DS8007 is active on the parallel bus. 39 ALE Address Latch Enable Input. This signal monitors the ALE signal when the host processor bus is operating in multiplexed mode. Connect this signal to VDD when operating in nonmultiplexed mode. 40 INT Active-Low Interrupt. This output indicates an interrupt is active. 41 INTAUX Auxiliary Interrupt Input. This pin serves as an auxiliary interrupt. 42–45 AD3–AD0 Register Selection Address Inputs. These pins function as the address input lines for the nonmultiplexed configuration and should be connected to ground or VDD in the multiplexed configuration. 46, 47 XTAL2, XTAL1 Crystal Oscillators. Place a crystal with appropriate load capacitors between these pins if that is the desired clock source. XTAL1 also acts as an input if there is an external clock source in place of a crystal. 48 DELAY External Delay Capacitor Connection. Connect a capacitor from this pin to ground to set the power-on reset delay.

have a basic understanding of ISO 7816 terminology. address is latched irrespective of the state of CS. Figure 6. Block Diagram

parallel bus mode found earlier in this data sheet. Figure 7. Parallel Bus Interface

• u = unchanged, x = always reflects state of external device pin, even when RIU = 0.

Note: Writes to unimplemented bits have no effect. Reads of unimplemented bits return 0. Table 1. Special Function Register Map

00 CSR R/W CSR7 CSR6 CSR5 CSR4 RIU SC3 SC2 SC1 0011 0000 0011 0uuu

01 CCR R/W — — SHL CST SC AC2 AC1 AC0 0000 0000 00uu uuuu

02 PDR R/W PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0000 0000 uuuu uuuu

03 UCR2 R/W — DISTBE/

06 UCR1 R/W FTE0 FIP — PROT T/R LCT SS CONV 0000 0000 0uuu 00uu

07 PCR R/W — — C8 C4 1V8 RSTIN 3V/5V START 0011 0000 0011 uuuu

08 TOC R/W TOC7 TOC6 TOC5 TOC4 TOC3 TOC2 TOC1 TOC0 0000 0000 0000 0000

09 TOR1 W TOL7 TOL6 TOL5 TOL4 TOL3 TOL2 TOL1 TOL0 0000 0000 uuuu uuuu

card interface A and card interface B. of the UART Control Register 1 (UCR1) at address 06h. requires no extra configuration by the software.

Multiprotocol Dual Smart Card Interface Card Select Register (CSR) R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00110uuub on RIU = 0. 76543210 Address 00h CSR7 CSR6 CSR5 CSR4 RIU SC3 SC2 SC1 R-0 R-0 R-1 R-1 RW-0 RW-0 RW-0 RW-0 Clock Configuration Register (CCR) R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00uuuuuub on RIU = 0. 76543210 Address 01h — — SHL CST SC AC2 AC1 AC0 R-0 R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Bits 7 to 4: Identification Bits (CSR7 to CSR4). These bits provide a method for software to identify the device as follows: 0011 = DS8007 revision Ax Bit 3: Reset ISO UART ( RIU). When this bit is cleared (0), most of the ISO UART registers are reset to their initial values. This bit must be cleared for at least 10ns prior to initiating an activation sequence. This bit must be set (1) by software before any action on the UART can take place. Bits 2 to 0: Select Card Bits (SC3 to SC1). These bits determine which IC card interface is active as shown below. Only one bit should be active at any time, and no card is selected after reset (i.e., SC3–SC1 = 000b). Other combinations are invalid. 000 = No card is selected. 001 = Card A is selected. 010 = Card B is selected. 100 = AUX card interface is selected. Bits 7 and 6: Reserved. Bit 5: Stop High or Low (SHL). This bit determines if the card clock stops in the low or high state when the CST bit is active. It forces the clock to stop in a low state when SHL = 0 or in a high state when SHL = 1. Bit 4: Clock Stop (CST). For an asynchronous card, this bit allows the clock to the selected card to be stopped. When this bit is set (1), the card clock is stopped in the state determined by the SHL bit. When this bit is cleared (0), the card clock operation is defined by CCR bits AC2–AC0. Bit 3: Synchronous Clock (SC). For a synchronous card, the card clock is controlled by software manipu- lation of this SC, and the contact CLK is the copy of the value in this bit. In synchronous transmit mode, a write to the UTR results in the least significant bit (LSb) of the data written to the UTR being driven out on the I/Ox pin. In synchronous receive mode, the state of the I/Ox pin can be read from the LSb of the URR. Bits 2 to 0: Alternating Clock Select (AC2 to AC0). These bits select the frequency of the clock provided to the active card interface and to the UART for the ele- mentary time unit (ETU) generation as shown below. All frequency changes are synchronous so that there are no spikes or unwanted pulse widths during transitions. f INT is the frequency of the internal oscillator. AC2–AC0 000 = f XTAL 001 = fXTAL / 2 010 = fXTAL / 4 011 = fXTAL / 8 1xx = fINT / 2

Bits 7 to 0: Programmable ETU Divider Register Bits 7 to 0 (PD7 to PD0). These bits, in conjunction with the defined UART input clock (based upon CKU, AC2–AC0) and the prescaler selection (PSC bit), are used to define the ETU for the UART when interfaced to the associated card interface. The output of the prescaler block is further divided according to the PD7–PD0 bits as follows:

• ETU = Prescaler output / (PD7–PD0), when PD7–PD0 = 02h–FFh
• ETU = Prescaler output / 1, when PD7–PD0 = 00h–01h
• Prescaler output / 256 is not supported Programmable Divider Register (PDR) R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0. 76543210 Address 02h PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 UART Control Register 2 (UCR2) R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0. 76 5 432 1 0 Address 03h — DISTBE/RBF DISAUX PDWN SAN AUTOC CKU PSC R-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Bit 7: Reserved. Bit 6: Disable TBE/RBF Interrupt (DISTBE/RBF). This bit controls whether the TBE/RBF flag can generate an interrupt on the INT pin. When this bit is cleared to 0, an interrupt is signaled on the INT pin in response to the TBE/RBF flag getting set. When DISTBE/RBF is set to 1, interrupts are not generated in response to the TBE/RBF flag. Disabling the TBE/RBF interrupt can allow faster communication speed with the card, but requires that a copy of TBE/RBF in register MSR be polled to not lose priority interrupts that can occur in register USR. Bit 5: Disable Auxiliary Interrupt (DISAUX). This bit controls whether the external INTAUX pin can generate an interrupt on the INT output pin. When this bit is cleared to 0, a change on the INTAUX input pin results in assertion of the INT output pin. When DISAUX is set to 1, a change on INTAUX does not result in assertion of the INT output pin. The INTAUXL bit is set by a change on the INTAUX pin independent of the DISAUX bit state. Since the INTAUX bit is set independent of the DISAUX bit, it is advisable to read HSR (thus clearing INTAUX) prior to clearing DISAUX to avoid an interrupt on the INT pin. To avoid an interrupt when selecting a different card, the DISAUX bit should be set to 1 in all UCR2 registers. Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface Bit 4: Power-Down Mode Enable (PDWN). This bit controls entry into the power-down mode. Power-down mode can only be entered if the SUPL bit has been cleared. When PDWN is set to 1, the XTAL1 and XTAL2 crystal oscillator is stopped, and basic functions such as the sequencers are supported by the internal ring oscillator. The UART is put in a suspended state, and the clocks to the UART, the ETU unit, and the timeout counter are gated off. During the power-down mode, it is not possible to select a card other than the one cur- rently selected (advisory to the programmer, selecting another card during power-down mode is not recom- mended). There are five ways of exiting the power- down mode:

• Insertion of card A or card B (detected by PRLA or PRLB).
• Withdrawal of card A or card B (detected by PRLA or PRLB).
• Reassertion of the CS pin to select the DS8007 ( CS must be deasserted after setting PDWN = 1 for this event to exit from power-down).
• INTAUXL bit is set due to change in INTAUX (INTAUXL bit must be cleared first).
• Clearing of PDWN bit by software (if CS pin is always tied to 0). Except in the case of a read operation of register HSR, the INT pin remains asserted in the active-low state. The host device can read the status registers after the oscillator warmup time, and the INT signal returns to the high state. Bit 3: Synchronous/Asynchronous Card Select (SAN). This bit selects whether a synchronous or asyn- chronous card interface is enabled. When this bit is cleared to 0, an asynchronous card interface is expect- ed. When this bit is set to 1, a synchronous interface is expected. In synchronous mode, the UART is bypassed; the SC bit controls the CLK, and I/O is trans- acted in the LSb of UTR/URR. Card interface AUX can- not operate in the true synchronous mode since it does not have a CLK signal to accompany I/OAUX. However, the SAN bit invokes the same control of I/OAUX through UTR/URR as is given for card interfaces A and B. Bit 2: Auto Convention Disable (AUTOC). This active- low bit controls whether the decoding convention should automatically be detected during the first received character in answer-to-reset (ATR). If AUTOC = 0, the character decoding convention is automatically detected (while SS = 1) and the UCR1.CONV bit is writ- ten accordingly by hardware. If AUTOC = 1, the UCR1.CONV bit must be set by software to assign the character decoding convention. The AUTOC bit must not be changed during a card session. Bit 1: Clock UART Doubler Enable (CKU). This bit enables the effective ETU defined for the UART to last half the number of clock cycles defined by the AC2–AC0 and PD7–PD0 configuration (except in the case when AC2–AC0 = 000b, where f CLK = f XTAL). When CKU is cleared to 0, the AC2–AC0 defined f CLK is used for ETU timing generation. When CKU is set to 1, a clock frequency of 2 x f CLK is used for ETU gener- ation. Bit 0: Prescaler Select (PSC). When PSC = 0, the prescaler value is 31. When PSC = 1, the prescaler value is 32. Guard Time Register (GTR) R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU = 0. 76543210 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 Bits 7 to 0: Guard Time Register Bits 7 to 0 (GTR.7 to GTR.0). These bits are used for storing the number of guard time units (ETU) requested during ATR. When transmitting, the DS8007 UART delays these numbers of extra guard time ETU before transmitting a character written to UTR.

Multiprotocol Dual Smart Card Interface UART Control Register 1 (UCR1) R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 0uuu00uub on RIU = 0. 76 5 432 1 0 Address 06h FTE0 FIP — PROT T/R LCT SS CONV R-0 RW-0 R-0 RW-0 RW-0 RW-0 RW-0 RW-0 Bit 7: FIFO Threshold Enable 0 (FTE0). When this bit and the FTE1 (FCR.3) bit are set, the programmable FIFO threshold feature is enabled. This bit always reads 0 for compatibility. Bit 6: Force Inverse Parity (FIP). When this bit is con- figured to 0, the correct parity is transmitted with each character, and receive characters are checked for the correct parity. When FIP = 1, an inverse parity bit is transmitted with each character and correctly received characters are NAK’d. Bit 5: Reserved. This bit must be left 0. Setting this bit to 1 causes improper device operation. Bit 4: Protocol Select (PROT). This bit is set to 1 by software to select the asynchronous T = 1 protocol and is cleared to 0 to select the T = 0 protocol. Bit 3: Transmit/Receive (T/R). This bit should be set by software to operate the UART in transmit mode. When this bit is changed from 0 to 1 (UART changed from receive to transmit mode), hardware sets the USR.RBF/TBE bit, indicating an empty transmit buffer. The T/R bit is automatically cleared to 0 following suc- cessful transmission if UCR1.LCT is configured to 1 prior to the transmission. This bit cannot be written to when RIU = 0 (holding in reset). Bit 2: Last Character to Transmit (LCT). This bit is optionally set by software prior to writing the last char- acter to be transmitted to the UART transmit register (UTR). If LCT is set to 1 prior to writing to UTR, hard- ware resets the LCT, T/R, and TBE/RBF bits following a successful transmission. Setting this bit to 1 allows automatic change to the reception mode after the last character is sent. This bit can be set during and before the transmission. This bit cannot be written to when RIU = 0 (holding in reset). Bit 1: Software Convention Setting (SS). This bit should be set by software prior to ATR to allow automat- ic convention detection. Hardware automatically resets the SS bit at 10.5 ETU after the detection of the start bit of the first character of the ATR. Bit 0: Convention (CONV). This bit defines the charac- ter decoding convention of the ISO UART. If CONV = 1, the convention is direct. If CONV = 0, the convention is inverted. If automatic convention detection is enabled (AUTOC = 0), hardware detects the character conven- tion and configures the CONV bit appropriately at 10.5 ETU. Otherwise (AUTOC = 1), software must configure the CONV bit.

Multiprotocol Dual Smart Card Interface Bits 7 to 0: Timeout Counter Configuration Register Bits (TOC7 to TOC0). These register bits determine the counting configuration for the three timeout counter registers. The available configurations are detailed in the Timeout Counter Operation section. These registers can be written when RIU = 1 before activation and can- not be written to when RIU = 0. Bits 7 and 6: Reserved. Bit 5: Contact 8 (C8). Writes to this register bit are out- put on the C8 pin of the card interface. Reads of this register bit reflect the value on the C8 pin. Bit 4: Contact 4 (C4). Writes to this register bit are out- put on the C4 pin of the card interface. Reads of this register bit reflect the value on the C4 pin. Bit 3: 1.8V Card Select (1V8). If this bit is set to 1, the V CCx supplied to the card interface is 1.8V. This bit overrides the 3V/5V bit. Bit 2: Reset Bit (RSTIN). When a card interface is acti- vated, the RSTx pin is driven according to the value contained in this register bit. Bit 1: 3V/5V Card Select (3V/5V). This bit determines the V CCx level for the card interface. When this bit is set to 1, V CCx is defined as 3V. When this bit is cleared to 0, VCCx is defined as 5V. When the 1V8 and 3V/5V bits are set to 1, priority is given to 1V8. Bit 0: Start (START). This bit controls software activa- tion/deactivation of the card interface. When this bit is written to 1, the activation sequence for the selected card is performed. When this bit is written to 0, the deactivation sequence for the selected card is per- formed. Hardware automatically resets the START bit for the associated card interface when emergency deactivation occurs. This bit can be written regardless of the state of the RIU bit. Power Control Register (PCR) R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 0011uuuub on RIU = 0. Note: The AUX card interface does not have register PCR. C4 and C8 are external ports that are internally pulled up (10kΩ to VCCx), writing a 1 to C4, C8 configures the weak pullup. Reads are made of the pin state to a different physical bit. Writing a 0 to C4, C8 configures the pulldown. C4 and C8 bits can be written irrespective of the state of the T/R bit. 765 43210 Address 07h — — C8 C4 1V8 RSTIN 3V/5V START R-0 R-0 RW-1 RW-1 RW-0 RW-0 RW-0 RW-0 Timeout Configuration Register (TOC) R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00000000b on RIU = 0. 76543210 Address 08h TOC7 TOC6 TOC5 TOC4 TOC3 TOC2 TOC1 TOC0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0

Bits 7 to 0: Timeout Counter Register 2 Bits (TOL15 to TOL8). This register can be configured to operate as the lower 8 bits of a 16-bit counter or as the middle 8 bits of a 24-bit counter. See the Timeout Counter Operation section for details on configurable modes. Timeout Counter Register 2 (TOR2) R = unrestricted read, W = unrestricted write, -n = value after reset. This register is unchanged on RIU = 0. 76543210 Address 0Ah TOL15 TOL14 TOL13 TOL12 TOL11 TOL10 TOL9 TOL8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 Timeout Counter Register 3 (TOR3) R = unrestricted read, W = unrestricted write, -n = value after reset. This register is unchanged on RIU = 0. 76543210 Address 0Bh TOL23 TOL22 TOL21 TOL20 TOL19 TOL18 TOL17 TOL16 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 Bits 7 to 0: Timeout Counter Register 3 Bits (TOL23 to TOL16). This register can be configured to operate as the high 8 bits of a 16-bit counter or as the high 8 bits of a 24-bit counter. See the Timeout Counter Operation section for details on configurable modes. Timeout Counter Register 1 (TOR1) R = unrestricted read, W = unrestricted write, -n = value after reset. This register is unchanged on RIU = 0. 765432 10 Address 09h TOL7 TOL6 TOL5 TOL4 TOL3 TOL2 TOL1 TOL0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 Bits 7 to 0: Timeout Counter Register 1 Bits (TOL7 to TOL0). This register can be configured to operate as an 8-bit counter or as the lowest 8 bits of a 24-bit counter. TOR1, TOR2, and TOR3 are concatenated to form a 24- bit ETU counter or a pair of independent 16- and 8-bit counters. These counters are only used when a card is supplied an active clock. See the Timeout Counter Operation section for details on configurable modes. Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface Mixed Status Register (MSR) R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to u1u1uuu0b on RIU = 0. 76543210 Address 0Ch CLKSW FE BGT CRED PRB PRA INTAUX TBE/RBF R-0 R-1 R-0 R-1 R-0 R-0 R-0 R-0 Bit 7: Clock Switch (CLKSW). This status bit indicates the clock (f XTAL / n or f INT / 2) being sourced by the selected card interface and thus may be used to deter- mine when a requested clock switch has occurred properly. When CLKSW is set 1, the clock has switched from f XTAL / n to f INT / 2; when CLKSW is cleared to 0, the clock has switched from fINT / 2 to fXTAL / n. Bit 6: FIFO Empty Status Bit (FE). This bit is set to 1 when the receive FIFO is empty. This bit is cleared to 0 when at least one character remains in the receive FIFO. Bit 5: Block Guard Time Status Bit (BGT). This status bit is linked to an ETU counter for the currently selected card interface, and is intended for use in verifying that the block guard time is always being met. The counter restarts on every start bit and stops only if the terminal count is reached. The terminal count is dependent upon the selected protocol (16 ETU for T = 0 and 22 ETU for T = 1). This bit is cleared to 0 on every start bit. Bit 4: Control Ready (CRED). This bit signals the host device that the DS8007 is ready to handle the next write operation to UTR or TOC or the next read opera- tion of URR. When CRED = 0, the DS8007 is still work- ing on the previous operation and cannot correctly process the new read/write request. When CRED = 1, the DS8007 is ready for the next read/write request. This “busy” bit allows the DS8007 to meet the timing constraints of high-speed host devices. The CRED bit remains low:

• 3 clock cycles after the rising edge of RD before reading URR.
• 3 clock cycles after the rising edge of WR (or CS) before writing to UTR.
• 1/PSC (min) ETU and 2/PSC (max) ETU after the rising edge of WR (or CS) before writing to TOC The CRED bit timing applies to asynchronous mode only; this bit is forced to 1 in synchronous mode. Bit 3: Presence Card B (PRB). This bit is set to 1 when card B presence is detected and is cleared to 0 when card B is not present. Bit 2: Presence Card A (PRA). This bit is set to 1 when card A presence is detected and is cleared to 0 when card A is not present. Bit 1: INTAUX Bit (INTAUX). This bit reflects the state of the INTAUX pin. This bit is set when the INTAUX pin is high and is cleared when the INTAUX pin is low. Bit 0: Transmit Buffer Empty/Receive Buffer Full (TBE/RBF). This bit signals special conditions relating to the ISO UART and associated hardware. This bit is not set when the last character is transmitted by the UART when LCT = 1. This bit is set to 1 when:
• UCR1.T/R is changed from 0 (receive mode) to 1 (transmit mode).
• A character is transmitted by the UART.
• The receive FIFO becomes full. This bit is cleared to 0 when:
• The ISO UART is reset by RIU = 0.
• A character is written to the UART transmit register (UTR) in transmit mode.
• A character is read from the receive FIFO in receive mode.
• UCR1.T/R is changed from 1 (transmit mode) to 0 (receive mode).

UART Receive Register (URR)/UART Transmit Register (UTR) R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00000000b on RIU = 0. 76543210 Address 0Dh UR7/UT7 UR6/UT6 UR5/UT5 UR4/UT4 UR3/UT3 UR2/UT2 UR1/UT1 UR0/UT0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 FIFO Control Register (FCR) R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 0uuu0uuub on RIU = 0. 76543210 Address 0Ch — PEC2 PEC1 PEC0 FTE1 FL2 FL1 FL0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 Bits 7 to 0: UART Receive Register (Read Operations)/UART Transmit Register (Write Operations) (UR7/UT7 to UR0/UT0). This register is used both as the UART transmit and receive buffer by the host microcontroller. Received characters are always read by the host microcontroller in direct convention, meaning that if the CONV bit is 0, then characters received using inverse convention are automatically translated by the hardware. When the receive FIFO is enabled, reads of URR always access the oldest avail- able received data. For the synchronous mode of opera- tion, the LSb (URR.0) reflects the state of the selected card I/Ox line. Writes by the host microcontroller to this register trans- mit characters to the selected card. The host microcon- troller should write data to UTR in direct convention (inverse convention encoding is handled by the hard- ware). The UTR register cannot be loaded during trans- mission. The transmission:

• Starts at the end of the write operation (rising edge of WR) if the previous character has been transmit- ted and the extra guard time has been satisfied.
• Starts at the end of the extra guard time if that guard time has not been satisfied.
• Does not start if the transmission of the previous character is not completed (e.g., during retransmis- sion attempts or if a transmit parity error occurs). For the synchronous mode of operation, only the LSb (UTR.0) of the loaded data is transferred to the I/Ox pin for the selected card. Bit 7: Reserved. Bits 6 to 4: Parity Error Count (PEC2 to PEC0). These bits are used only for the T = 0 protocol to determine the number of retransmission attempts that can occur in transmit mode and the number of parity errors that can occur before the PE bit is set to 1 to indicate that the par- ity error limit has been reached. In transmit mode, the DS8007 attempts to retransmit a character up to (PEC2–PEC0) times (when NAK’d by the card) before the PE bit is set. Retransmission attempts are automati- cally made at 15 ETU from the previous start bit. If PEC2–PEC0 = 000b, no retransmission attempt is made, however, the host device can manually rewrite the char- acter to UTR (in which case, it is re-sent as early as 13.5 ETU from the previous start bit of the error character. In receive mode, if (PEC2–PEC0 + 1) parity errors have been detected, the USR.PE bit is set to 1. For example, if PEC2–PEC0 = 000b, only one parity error needs to be detected for the PE bit to be set; if PEC2–PEC0 = 111b, 8 parity errors must be detected, etc. If a character is correctly received before the allowed parity error count is reached, the parity counter is reset. For the T = 1 protocol, the parity counter is not used. The PE bit is set whenever a parity error is detected for a received character. Bit 3: FIFO Threshold Enable 1 (FTE1). When this bit and the FTE0 (UCR1.7) bit are set, the programmable FIFO threshold feature is enabled. This bit always reads 0 for compatibility. Bits 2 to 0: FIFO Length (FL2 to FL0). These bits determine the depth of the receive FIFO. The receive FIFO has depth equal to (FL2–FL0) + 1 (e.g., FIFO depth = 2 if FL2–FL0 = 001b). Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface Bits 7 to 5: Timeout Counter 3/2/1 Status (TO3 to TO1). These bits are set to 1 whenever their respective timeout counter reaches its terminal count. Any of these bits causes the INT pin to be asserted. Bit 4: Early Answer Detected (EA). This bit is set to 1 if a start bit is detected on the I/O line during the ATR between clock cycles 200–368 when the RSTx pin is low, and during the first 368 clock cycles after the RSTx pin is high. When the EA bit becomes set, INT is assert- ed. If the EA bit is set for a card during ATR, this bit is cleared when switched to another card. During the early answer detection period, a 46-clock-cycles sam- pling period should be used to detect the start bit; there is an undetected period of 32 clock cycles at the end for both cases (between clock cycles 200–368 when the RSTx pin is low, and the first 368 clock cycles after the RSTx pin is high). Bit 3: Parity Error (PE). This status bit indicates when the transmit or receive parity error count has been exceeded. For protocol T = 0, the PEC2–PEC0 bits define the allowable number of transmit or receive pari- ty errors. For protocol T = 1, any parity error results in the setting of the PE bit. When the PE bit is set, INT is asserted. For protocol T = 0, characters received with the incorrect parity are not stored in the receive FIFO. For protocol T = 1, received characters with parity errors are stored to the receive FIFO regardless of the parity bit. The PE bit is set at 10.5 ETU in reception mode and at 11.5 ETU in transmit mode for T = 0 and T = 1 (PE bit is not applicable for transmit for T = 1). Bit 2: Overrun FIFO (OVR). This status bit is set to 1 if the UART receives a new character when the receive FIFO is full. When a FIFO overrun condition occurs, the new character received is lost and the previous FIFO content remains undisturbed. When the OVR status bit is set, INT is asserted. The OVR bit is set at 10.5 ETU in receive mode for T = 0 and T = 1. Bit 1: Framing Error (FER). This status bit is set to 1 if the I/O line is not in the high state at time = 10.25 ETU after the start bit. The FER bit is set to 10.5 ETU in receive mode for T = 0 and T = 1. Bit 0: Transmit Buffer Empty/Receive Buffer Full (TBE/RBF). This is a duplicate of the same status bit contained in the Mixed Status Register (MSR). UART Status Register (USR) R = unrestricted read, W = unrestricted write, -n = value after reset. All register bits are reset to 00000000b on RIU = 0. Note: If any of the bits TO3, TO2, TO1, EA, PE, OVR, or FER are set, then a USR read operation clears the bit, causing an interrupt less than 2µs after the rising edge of the RD strobe. PE and FER can be set by the same reception. 76543210 Address 0Eh TO3 TO2 TO1 EA PE OVR FER TBE/RBF R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0

DS8007Hardware Status Register (HSR) R = unrestricted read, W = unrestricted write, -n = value after reset, x = always reflects state of external device pin. This register is reset to 0uuuxxxub on RIU = 0. Note: A minimum of 2µs is needed between successive reads of the HSR to allow for hardware updates. In addition, a minimum of 2µs is needed between reads of the HSR and activation of card A, card B, or the AUX card. 765 43210 Address 0Fh — PRTLB PRTLA SUPL PRLB PRLA INTAUXL PTL R-0 R-0 R-0 R-1 R-0 R-0 R-0 R-0 Bit 7: Reserved. Bit 6: Protection Card Interface B Status Bit (PRTLB). This bit is set to 1 when a fault has been detected on card reader interface B. A fault is defined as detection of a short-circuit condition on either the RSTB or V CCB pin as given by DC specs I RST(SD) and ICC(SD). The INT signal is asserted at logic 0 (active) while this bit is set. This bit returns to 0 after any HSR read, unless the condition persists. Bit 5: Protection Card Interface A Status Bit (PRTLA). This bit is set to a 1 when a fault has been detected on card reader interface 1. A fault is defined as detection of a short-circuit condition on either the RSTA or V CCA pin as given by DC specs I RST(SD) and ICC(SD). The INT signal is asserted at logic 0 (active) while this bit is set. This bit returns to 0 after any HSR read, unless the condition persists. Bit 4: Supervisor Latch (SUPL). This bit is set to 1 when V DD < VRST or when a reset is caused by exter- nally driving the DELAY pin < 1.25V. At this time the INT signal is asserted at logic 0 (active). This bit returns to 0 only after an HSR read outside the alarm pulse. Bit 3: Presence Latch B (PRLB). This bit is set to 1 when a level change has been detected on the PRESB pin of card interface B. The INT signal is asserted at logic 0 (active) while this bit is set. This bit returns to 0 after any HSR read. Bit 2: Presence Latch A (PRLA). This bit is set to 1 when a level change has been detected on the PRESA pin of card interface A. The INT signal is asserted at logic 0 (active) while this bit is set. This bit returns to 0 after any HSR read. Bit 1: INTAUX Latch (INTAUXL). This bit is set to 1 when a 0 → 1 or a 1 → 0 level change has been detect- ed on the INTAUX pin. This bit remains set, regardless of further level changes on the INTAUX pin until cleared to 0 by any HSR read. Bit 0: Protection Thermal Latch (PTL). This bit is set to 1 when excessive heating (approximately +150°C or greater) is detected. The INT signal is asserted at logic 0 (active) while this bit is set. This bit returns to 0 after any HSR read, unless the condition persists. Multiprotocol Dual Smart Card Interface

The VDD and VDDA pins supply power to the DS8007. bit may only be cleared by a read of the HSR register. bit in the HSR is set and an interrupt is generated. I/Ox, C4x, and C8x does not cause deactivation. Table 2. Step-Up Converter Operation

Figure 8. Voltage Supervisor

1. PCRx.START BIT IS SET BY SOFTWARE.
2. STEP-UP CONVERTER ACTIVATED (MAY ALREADY BE ON IF ANOTHER CARD WAS ACTIVE).

CCx ENABLED TO 1.8V, 3V, OR 5V AS SELECTED BY PCRx.1V8 AND PCR.3V/5V BITS. VCCx RISES FROM 0V TO 1.8V, 3V, OR 5V WITH A CONTROLLED RISE TIME OF 0.17V/μs TYPICAL.

1. I/Ox IS PULLED HIGH. C4x, C8x ARE ALSO PULLED HIGH IF PCRx.C4 = 1, PCRx.C8 = 1
2. CLKx OUTPUT IS ENABLED AND RST OUTPUT IS ENABLED.
3. PCRx.RSTIN WRITTEN TO "1" BY SOFTWARE AFTER USING TOC TO TIME SUFFICIENT

DURATION OF RSTx PIN ASSERTION.

1. PCRx.START BIT IS CLEARED BY SOFTWARE.
2. THE ACTIVE-LOW RSTx SIGNAL IS ASSERTED BY SOFTWARE.
3. THE CLKx SIGNAL IS STOPPED.
4. I/Ox, C4x, AND C8x FALL TO 0V.

CCx IS DISABLED AND FALLS TO 0V WITH A TYPICAL RATE OF 0.17V/μs.

1. STEP-UP CONVERTER IS DEACTIVATED IF NOT IN USE BY ANOTHER CARD AND

CCx BECOME LOW IMPEDANCE TO GROUND. Figure 9. Card Activation, Deactivation Sequences ascertained through the HSR, MSR, and CSR bits. 130µs. The activation sequence is detailed in Figure 9.

CCx decrease to less than 0.4V) is less than 150µs. emergency deactivation varies according to the source.

• A fault has been detected on card interfaces (A or B). DD has dropped below the acceptable level.
• A reset is caused by externally driving the DELAY pin to less than 1.25V.
• Excessive heating is detected (i.e., PTL = 1).
• A level change has been detected on pin PRESx or INTAUX for the card interfaces (A, B, or AUX).
• The parity and/or frame error is detected.
• The early answer (EA) bit is set during ATR.
• The timeout counter(s) reach their terminal count(s).
• The FIFO full status is reached.
• The FIFO overrun occurs.
• The transmit buffer is empty. HSR.PRTLA HSR.PRTLB HSR.PRLA HSR.PRLB HSR.PTL HSR.SUPL USR.TO3 USR.TO1 USR.TO2 USR.EA USR.OVR USR.FER USR.PE HSR.INTAUXL INTERRUPT GENERATION INT OUTPUT PINSCA, SCB, SCAUX UCR2A.DISAUX UCR2B.DISAUX UCR2AUX.DISAUX UCR2A.DISTBE/RBF USR.TBE/RBF UCR2B.DISTBE/RBF UCR2AUX.DISTBE/RBF SCA, SCB, SCAUX

Figure 10. Interrupt Sources

ered and have an active clock. ported for all counter widths (8 bit, 16 bit, and 24 bit). new value into the associated TORx counter registers. flag(s) is set, and an interrupt is generated. data is used on the next START bit detection. Table 3. Timeout Counter Configurations 00h Stopped All counters are stopped. bit/autoreload mode for both transmission and reception. Counters 3 and 2 form a 16-bit counter operating in software mode. counters are stopped by setting TOC = 00h. cannot be changed without stopping the counter first.

DS8007Table 3. Timeout Counter Configurations (continued) TOC VALUE TOR3 TOR2 TOR1 DESCRIPTION 71h Start Bit Stopped Counter 1 is stopped. Counters 3 and 2 form a 16-bit counter operating in start bit mode for both transmission and reception. TOR3 and TOR2 registers can be changed during the count, the current count is not affected, and the values are taken into account at the next START bit detected on the I/Ox pin. Setting TOC = 00h stops the counters. 75h Start Bit Start Bit/Autoreload Counter 1 is an 8-bit counter in start-bit/autoreload mode for both transmission and reception; counters 3 and 2 form a 16-bit counter operating in start-bit mode for both transmission and reception. The TOR1 register is not allowed to change during the count. TOR3, TOR2 registers can be changed during the count, the current count is not affected, and the values are taken into account at the next START bit detected on the I/Ox pin. Setting TOC = 00h stops the counters. 7Ch Start Bit Counters 1/2/3 form a 24-bit counter operating in start-bit mode in both transmission and reception. TOR3, TOR2 and TOR1 registers can be changed during the count, the current count is not affected, and the value is taken into account at the next START bit detected on the I/Ox pin. Setting TOC = 00h stops the counter. 85h Stopped Start Bit/Autostop (RCV); Start Bit/Autoreload (XMT) Counters 3 and 2 are stopped. Counter 1 is operated in start- bit/autostop mode in reception and is stopped at the end of the 12th ETU following the first received START bit detected on the I/Ox pin unless the terminal count is reached first. Counter 1 operates in start- bit/autoreload mode in transmission. E5h Software Start Bit/Autostop (RCV); Start Bit/Autoreload (XMT) Counters 3 and 2 form a 16-bit counter operating in software mode. The counters are stopped by setting TOC = 05h before reloading new values in TOR3 and TOR2 registers. Counter 1 is operated in autostop mode in reception and is stopped at the end of the 12th ETU following the first received START bit detected on the I/Ox pin unless the terminal count is reached first. Counter 1 is operated in start-bit/autoreload mode in transmission. F1h Start Bit/Autostop (RCV); Start Bit (XMT) Stopped Counter 1 is stopped. Counters 3 and 2 form a 16-bit counter. The 16-bit counter is operated in start-bit/auto-stop mode in reception and is stopped at the end of the 12th ETU following the first received START bit detected on the I/Ox pin unless the terminal count is reached first; and the 16-bit counter is operated in start-bit mode in transmission. F5h Start Bit/Autostop (RCV); Start Bit (XMT) Start Bit/Autostop (RCV); Start Bit/Autoreload (XMT) Counter 1 is an 8-bit counter operating in start-bit/autostop mode in reception and is stopped at the end of the 12th ETU following the first received START bit detected on the I/Ox pin unless the terminal count is reached first; and the 8-bit counter is operated in start- bit/autoreload mode in transmission. Counters 3 and 2 form a 16-bit counter operating in start-bit mode for transmission but operate in start-bit/autostop mode in reception. Counters 3 and 2 are stopped at the end of the 12th ETU following the first received START bit detected on the I/Ox pin unless the terminal count is reached first; the counters are stopped by setting TOC = 00h. Multiprotocol Dual Smart Card Interface

Multiprotocol Dual Smart Card Interface ISO UART Implementation Reset Operation The HSR.RIU control bit resets the ISO UART. The HSR.RIU must be reset prior to any activation. HSR.RIU must be returned to 1 by software before any UART action can take place. Synchronous Mode The synchronous mode of operation is invoked by set- ting the synchronous/asynchronous card select bit (for a given card interface) to logic 1. In the synchronous mode of operation, the associated I/Ox card interface data is transferred by the LSb of the UART transmit/receive registers (UTR and URR). In this mode, the host device using the CCRx.SC register bit manual- ly controls the CLKx pin for the selected card interface. Switching to the synchronous mode or vice versa is allowed at any time when the card is active. However, it is the responsibility of the host software/firmware to ensure that the current transmission is concluded before switching. If software configures an active card for synchronous mode, and then activates another card, the I/O pin on the previously active card goes to a high-impedance state with a weak pullup (high). The newly selected interface (if configured to synchronous mode) takes on UTR.0. The AUX card interface does not have an associated CLK signal, so the CCRAUX.SC bit does not control an output signal when the synchronous mode of operation is in effect. The handshake between the host and the auxiliary smart card interface is accomplished through the auxiliary interrupt input (INTAUX) and the INT pins. The MSR.INTAUX bit reflects the state of the INTAUX pin. If the UCR2.DISAUX bit is cleared to 0, a change on the INTAUX input pin results in the assertion of INT output pin. The host software/firmware establishes the commu- nication protocol and controls when to transmit/receive data in response to the interrupt. If the UCR2.DISAUX bit is set to 1, the INT pin is not asserted, and the host soft- ware/firmware must examine the INTAUX bit in the MSR register and responds accordingly. Asynchronous Mode The asynchronous mode of operation is the reset default mode for all card interfaces and is selected when the synchronous/asynchronous card select bit (for a given card interface) is configured to logic 0. The I/Ox card interface signal is used for asynchronous half-duplex data communication between the host-con- trolled ISO UART and the external smart card. The host device can optionally stop the CLKx signal in the high or low state while the card is active using the CCRx.CST and CCRx.SHL register bits. ETU Generation and Timing The basic unit of time for asynchronous mode commu- nication on the I/Ox signal is the elementary time unit (ETU). The ETU is defined within the ISO UART as a function of the f CLK frequency that is configured for the card interface (i.e., the same f CLK that can be sourced to the CLKx pin of an associated card interface A or B). In addition to receiving f CLK from the clock generation block, the ISO UART additionally receives a 2 x f CLK frequency if CCRx.AC2–AC0 ≠ 000b. The host device can select whether f CLK or 2 x f CLK is used for ETU generation by using the clock UART (CKU) select bit. When CKU = 0, f CLK is used, while 2 x f CLK is used when CKU = 1. One exception exists when CCRx.AC2–AC0 = 000b, in which case, only f CLK is sourced to the UART and the CKU bit setting has no effect on the duration of an ETU. The basic clock that is selected for ETU generation by the CKU bit is further prescaled by a factor or 31 or 32. The prescaler select control (PSC) bit makes this prescaler selection. When PSC is configured to logic 0, the prescale setting is 31. When PSC is configured to logic 1, the prescale setting is 32. The output of the clock prescaler drives an 8-bit autoreload down counter. The autoreload value for the downcounter is configured by the host device through the Programmable Divider Register (PDR). The interval pro- vided by this downcounter defines the ETU duration for the selected card. Figure 11 shows a diagram of ETU generation. All the asynchronous character transmit/receive operations are defined in terms of ETU

ed initially and after negotiation. should be in the range Fd-Fi and Dd-Di, respectively.

10.5 ETU

10.25 ETU

Figure 11. ETU Generation

Table 4. Fi, Di Parameter Possibilities

0111 RFU — — 0111 RFU

1000 RFU — — 1000 RFU

1110 RFU RFU — 1110 RFU

1111 RFU RFU — 1111 RFU

RFU = Reserved for future use. Table 5. PSC, PDR Settings to Support F,D Parameters

consecutive start bits sent in the opposite direction. BGT status bit is cleared to 0. set to 1 to indicate that the transmit buffer is empty. another character can be loaded into the UTR register. Figure 14. Block Guard Time ETU Counter Operation

not set at the end of the transmission. when reading from register URR at high frequencies. UCR1.FIP is configured to 1, inverse parity is expected. retransmits requested characters. Figure 15. Last Character to Transmit

to a character received with incorrect parity. lish any nonzero PEC2–PEC0 setting. FIFO contents remain undisturbed. AND DECREMENT PARITY COUNTER. Figure 16. Receive Mode—Error Signal Generation

FIFO since the DS8007 is checking for inverse parity. determines the threshold value. and MSR) are set and the interrupt pin is asserted. overwrites the previously received character. clock cycles after the rising edge of the RSTx signal. chased directly from Maxim/Dallas Semiconductor. Table 6. Early Answer Detection

Multiprotocol Dual Smart Card Interface Typical Operating Circuit VBAT V50 VCCOVCCO DVDDC2 10μF 0.1μF 0.1μF C12 0.1μF 10kΩ 10kΩ 10kΩ C14 0.1μF C11 0.1μF 0.22μF 0.22μF 0.22μF 10μF 0.1μF AVDD VDD VDD RST SDI CARD SOCKET SAM SOCKET INT40 ALE39 AD045 AD144 AD243 AD342 RD36 WR37 D028 D129 D230 D331 D533 D634 D735 CS38 I/OAUX2 INTAUX41 XTAL147 XTAL246 VDDA 23 CPA1 21 CPA2 26 CPB1 22 CPB2 24 VUP 20 C4A 6 C8A 4 CLKA 8 RSTA 10 VCCA 9 I/0A 3 PRESA 5 GNDA 7 C4B 14 C8B 12 CLKB 16 RSTB 18 VCCB 17 I/OB 11 PRESB 13 GNDB 15 AGND 25 VDD27 GND19 RSTOUT1 D432 DELAY48 CY62148BLL-70SXC A17 1 A16 2 A14 3 A12 4 A7 5 A6 6A5 7A4 8A3 9A2 10 A1 11A0 12D013 D114 D215 GND D317 D418 D519 D620 D721 A10 23 CE 22 OE 24 A11 25 A9 26A8 27 A13 28 WE 29 A18 30 A15 31 VCC SW1 DELAY 1 2 3 4 C10 22pF P0.4 1 CE2/A162 PE23 A94 P0.3 5 A86 P0.2 7 A138 P0.1 9 R/W10 P0.0 11 1213 MSEL 14 P1.0 15 A1416 P1.1 17 A1218 P1.2 19 A720 P1.3 21 PE322 PE423 A624 P1.4 25 A526 P1.5 27 A428 P1.6 29 A330 P1.7 31 A233 RST 34 A135 P3.0/RXD 36 A037 P3.1/TXD 38 P3.2/INT0 39 P3.3/INT1 40 P3.4/T0 41 VRST 42 PF 43 P3.5/TI 44 P3.6 45 P3.7 46 XTAL2 XTAL148 P2.0 49 P2.1 50 P2.2 51 GND SDI 53 VBAT VCC VCC0 D055 P2.3 56 D157 P2.4 58 D259 P2.5 60 D361 CE462 CE3/A1563 P2.6 64 D465 P2.7 66 D567 NC68 68 D669 ALE 70 D771 CE1N72 NC73 73 CE174 P0.7 75 A1076 P0.6 77 PE178 P0.5 79 A1180 14.7456MHz C15 22pF C13 22pF

14.7456 MHz

Multiprotocol Dual Smart Card Interface Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 41 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation.

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