DS75LXUTR DALLAS | Alldatasheet
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Digital Thermometer and Thermostat with Extended Addressing www.maxim-ic.com GENERAL DESCRIPTION This low-voltage (1.7V to 3.7V) digital thermometer and thermostat provides 9, 10, 11, or 12-bit digital temperature readings over a -55°C to +125°C range with ±2°C accuracy over a -25°C to +100°C range. At power-up, the DS75LX defaults to 9-bit resolution for software compatibility with the LM75. Communication with the DS75LX is achieved through a simple 2-wire serial interface. Three tri-state address pins allow up to 27 DS75LX devices to operate on the same 2-wire bus, which greatly simplifie s distributed temperature- sensing applications. The DS75LX thermostat has a dedicated open-drain output (O.S.) and programmable fault tolerance, which allow the user to define the number of consecutive error conditions that must occur before O.S. is activated. Ther e are two thermostatic operating modes that cont rol thermostat operation based on user-defined trip-points (T OS and THYST).
APPLICATIONS
Any Thermally Sensitive System Cellular Base Stations Telecom Switches and Routers Servers PIN CONFIGURATIONS
FEATURES
1.7V to 3.7V Operating Range Tri-State Address Pins Allow Up to 27 Unique Bus Addresses Temperature Measurements Require No External Components Measures Temperatures from -55°C to +125°C (-67°F to +257°F) ±2°C Accuracy from -25°C to +100°C Thermometer Resolution Is User- Configurable from 9 (Default) to 12 Bits (0.5°C to 0.0625°C Resolution) 9-Bit Conversion Time is 25ms (max) Thermostatic Settings are User-Definable Data is Read/Written Through 2-Wire Serial Interface (SDA and SCL Pins) Data Lines Filtered Internally for Noise Immunity (50ns Deglitch) Bus Timeout Feature Prevents Lockup Problems on 2-Wire Interface Multidrop Capability Simplifies Distributed Temperature-Sensing Applications Pin/Software Compatible with the LM75 Available in 8-Pin μSOP (μMAX®) and SO Packages
ORDERING INFORMATION
DS75LXS+ -55°C to +125°C 8 SO (150 mils) DS75LXS+T&R -55°C to +125°C 8 SO (150 mils),
2500 Piece
DS75LXU+ -55°C to +125°C 8 µSOP (µMAX) DS75LXU+T&R -55°C to +125°C 8 µSOP (µMAX),
3000 Piece
+ Denotes lead-free package. T&R denotes tape-and-reel. Note: A “+” symbol will also be marked on the package near the pin 1 indicator. µMAX is a registered trademark of Maxim Integrated Products, Inc. SO (150 mils) SCL VDD A2GND O.S. SDA DS75 LX μSOP/μMAX SCL VDD A2GND O.S. SDA DS75 LX
Voltage Range on VDD, Relative to Ground -0.3V to +4.0V Voltage Range on Any Other Pin, Relative to Ground -0.3V to +6.0V Operating Temperature Range -55°C to +125°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDEC J-STD-020 These are stress ratings only and functional operation of the devic e at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. The Dallas Semiconductor DS75LX is built to the high est quality standards and manufactured for long-term reliability. All Dallas Semiconductor devices are made using the same quality materials and manufacturing methods. However, the DS75LX is not exposed to environmental stresses, such as burn-in, that some industrial applications require. For specific reliability information on this product, contact the factory in Dallas at (972) 371- 4448. DC ELECTRICAL CHARACTERISTICS (1.7V ≤ VDD ≤ 3.7V, TA = -55°C to +125°C.) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Supply Voltage VDD (Note 1) 1.7 3.7 V -25°C to +100°C ±2.0 Thermometer Error (Note 2) TERR -55°C to +125°C ±3.0 °C Input Logic-High SDA, SCL VIH (Note 3) 0.7 x VDD VDD + 0.3 V Input Logic-Low SDA, SCL VIL VSS - 0.3 0.3 x VDD V VOL1 3mA sink current 0 0.4 SDA Output Logic-Low Voltage (Note 3) VOL2 6mA sink current 0 0.6 V O.S. Saturation Voltage VOL 4mA sink current (Notes 2, 3) 0.8 V Input Current SDA, SCL 0.4 < VI/O < 0.9VDD -10 +10 µA I/O Capacitance CI/O 10 pF Address Input Sink Current ILAH A0, A1, or A2 tied to VDD (Notes 4, 5) 0.2 3.5 µA Address Input Source Current ILAL A0, A1, or A2 tied to GND (Notes 4, 5) 0.2 3.5 µA Address Voltage High VAH (Note 6) VDD - .04 V Address Voltage Low VAL (Note 6) VSS + .04 V Standby Current IDD1 (Notes 4, 5) 13 µA Active temp conversions 1000 Active Current (Notes 1, 4, 5) IDD Communication only 100 µA AC ELECTRICAL CHARACTERISTICS (1.7V ≤ VDD ≤ 3.7V, TA = -55°C to +125°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Resolution 9 12 Bits 9-bit conversions 25 10-bit conversions 50 11-bit conversions 100 Temperature Conversion Time tCONVT 12-bit conversions 200 ms
DS75LX: Digital Thermometer and Thermostat with Extended Addressing 3 of 13 SCL Frequency fSCL 400 kHz AC ELECTRICAL CHARACTERISTICS (continued) (1.7V ≤ VDD ≤ 3.7V, TA = -55°C to +125°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Bus Free Time Between a STOP and START Condition tBUF (Note 7) 1.3 µs START and Repeated START Hold Time from Falling SCL tHD:STA (Notes 7, 8) 600 ns Low Period of SCL tLOW (Note 7) 1.3 µs High Period of SCL tHIGH (Note 7) 0.6 µs Repeated START Condition Setup Time to Rising SCL tSU:STA (Note 7) 600 ns Data-Out Hold Time from Falling SCL tHD:DAT (Notes 7, 9) 0 0.9 µs Data-In Setup Time to Rising SCL tSU:DAT (Note 7) 100 ns Rise Time of SDA and SCL (Receive) tR (Notes 7, 10) 20 + 0.1CB B 300 ns Fall Time of SDA and SCL (Receive) tF (Notes 7, 10) 20 + 0.1CB B 300 ns Spike Suppression Filter Time (Deglitch Filter) tSS 0 50 ns STOP Setup Time to Rising SCL tSU:STO (Note 7) 600 ns Capacitive Load for Each Bus Line CB B 400 pF Input Capacitance CI 5 pF Serial Interface Reset Time tTIMEOUT SDA time low (Notes 11, 12) 75 325 ms Note 1: VDD must be decoupled with a high-quality 0.1µF bypass capacitor. X5R or X7R ceramic surface-mount capacitors are recommended. rated current. Note 3: All voltages are referenced to ground. Note 4: IDD specified with O.S. pin open and A0–A2 pins grounded. Note 5: IDD and address leakage specified with VDD at 3.0V and SDA, SCL = 3.0V at 0°C to +70°C. Note 6: Address pins A0, A1, A2 are directly connected to VDD, VSS, or floating with less than 50pF capacitive load. Note 7: See the timing diagram (Figure 1). All timing is referenced to 0.9 x VDD and 0.1 x VDD. Note 8: After this period, the first clock pulse is generated. Note 9: The DS75LX provides an internal hold time of at least 75ns on the SDA signal to bridge the undefined region of SCL's falling edge. Note 10: For example, if CB = 300pF, then tR[min] = tF[min] = 50ns. Note 11: This timeout applies only when the DS75LX is holding SDA low. Other devices can hold SDA low indefinitely and the DS75LX will not reset. Note 12: The DS75LX is available with timeout feature disabled upon special order. Contact Factory. PIN DESCRIPTION PIN NAME FUNCTION
1 SDA Data Input/Output for 2-Wire Serial Communication Port (Open Drain)
2 SCL Clock Input for 2-Wire Serial Communication Port
3 O.S. Thermostat Output Open Drain
4 GND Ground
5 A2 Address Input
6 A1 Address Input
7 A0 Address Input
8 VDD
Supply Voltage. +1.7V to +3.7V supply pin. V DD must have an external bypass capacitor to GND. 0.1µF X5R or X7R ceramic SMT caps recommended.
Figure 1. Timing Diagram
calibrated and requires no external components to measure temperature. Register section of this data sheet. Note that the conversion time doubles for each additional bit of resolution. resolution, the 11 MSbs (bits 15 through 5) of the temper ature register contain data, and bit 4 reads out as 0. output data and the corresponding temperatures. Figure 2. Temperature, TH, and TL Register Format Table 1. 12-Bit Resolution Temperature/Data Relationship
DS75LX: Digital Thermometer and Thermostat with Extended Addressing 6 of 13 Shutdown Mode For power-sensitive applications, the DS75LX offers a low-power shutdown mo de. The SD bit in the configuration register controls shutdown mode. When SD is changed to 1, the conversion in progress is completed and the result is stored in the temperature register after which the DS75LX goes into a low-power standby state. The O.S. output is cleared if the thermostat is operating in interrupt mode, and O.S remains unchanged in comparator mode. The 2- wire interface remains operational in shutdown mode, and wr iting a 0 to the SD bit returns the DS75LX to normal operation. OPERATION—THERMOSTAT The DS75LX thermostat has two operating modes, co mparator mode and interrupt mode, which activate and deactivate the open-drain thermo stat output (O.S.) based on us er-programmable trip-points (T OS and T HYST). The DS75LX powers up with the thermost at in comparator mode with active-low O.S. polarity and with the overtemperature trip-point (TOS) register set to +80°C and the hysteresis trip-point (T HYST) register set to +75°C. If these power-up settings are compatible with the application, the DS75LX can be used as a stand-alone thermostat THYST values are desired, they must be programmed after power-up, so stand-alone operation is not possible. In both operating modes, the user can program the thermost at fault tolerance, which sets how many consecutive temperature readings (1, 2, 4, or 6) must fall outside of the thermostat limits befor e the thermostat output is triggered. The fault tolerance is set by the F1 and F0 bi ts in the configuration regist er and at power-up the fault tolerance is 1. The data format of the T OS and THYST registers is identical to that of the te mperature register (see Figure 2), i.e., a 2-byte two’s complement representation of the trip-point temperature in de grees celcius with bits 3 through 0 hardwired to 0. After every temperature conversion, the measured temperature is compared to the values in the TOS and THYST registers, and then O.S. is up dated based on the result of the co mparison and the operating mode. The number of TOS and THYST bits used during the thermostat comparison is equal to the conversion resolution set by the R1 and R0 bits in the configurat ion register. For example, if the resolution is 9 bits, only the 9 MSbs of T OS and THYST will be used by the thermostat comparator. The active state of the O.S. output can be changed by the POL bit in the configuration register. The power-up default is active low. If the user does not wish to use the thermostat capabilities of the DS75LX, the O.S. output should be left floating. Note that if the thermostat is not used, the TOS and THYST registers can be used for general storage of system data. Comparator Mode When the thermostat is in comparat or mode, O.S. can be programmed to ope rate with any amount of hysteresis. The O.S. output becomes active when the measured temperature exceeds the T OS value a consecutive number of times as defined by the F1 and F0 fault tolerance (FT) bits in the configuration register. O.S. then stays active until the first time the temperature falls below the value stored in THYST. Putting the device into shutdown mode does not clear O.S. in comparator mode. Thermostat comparator mode operation with FT = 2 is illustrated in Figure 3. Interrupt Mode In interrupt mode, the O.S. output first becomes active when the measured temperature exceeds the T OS value a consecutive number of times equal to the FT value in the co nfiguration register. Once activated, O.S. can only be cleared by either putting the DS75LX into shutdown mode or by reading from any register (temperature, configuration, TOS, or T HYST ) on the device. Once O.S. has been deactivated, it will only be reactivated when the measured temperature falls below the THYST value a consecutive number of times equal to the FT value. Again, O.S can only be cleared by putting the device into shutdown mode or reading any register. Thus, this interrupt/clear process is cyclical between T OS and T HYST events (i.e, T OS, clear, T HYST, clear, T OS, clear, T HYST, clear, etc.). Thermostat interrupt mode operation with FT = 2 is illustrated in Figure 3.
Figure 3. O.S. Output Operation Example entire register is volatile, and thus powers up in its default state. Figure 4. Configuration Register
0 R1 R0 F1 F0 POL TM SD
have a fault tolerance of 2.
Table 2. Configuration Register Bit Descriptions The master can write to this bit, but it always reads out as a 0. Sets conversion resolution (see Table 3). Sets conversion resolution (see Table 3). Sets the thermostat fault tolerance (see Table 4). Sets the thermostat fault tolerance (see Table 4). POL = 0 — O.S. is active low. POL = 1 — O.S. is active high. SD = 0 — Active conversion and thermostat operation. See the Shutdown Mode section for a detailed description of this mode. Table 3. Resolution Configuration Table 4. Fault Tolerance Configuration reading from or writing to the DS75LX, the user must “point ” the DS75LX to the register that is to be accessed. When reading from the DS75LX, once the pointer is set it re mains pointed at the same register until it is changed. refreshed each time a write is performed, even if the same register is being written to twice in a row. immediately without resetting the pointer. Changes to the pointer setting are accomplished as described in the 2-Wire Serial Data Bus.
Table 5. Pointer Definition drain SDA I/O pin. All communication is MSb first. generates the SCL signal and START and STOP conditions. Slave: All devices on the bus other than the master. The DS75LX always functions as a slave. (if the SCL output is open drain). Transmitter: A device (master or slave) that is sending data on the bus. Receiver: A device (master or slave) that is receiving data from the bus. will perform another operation. STOP is issued, the master releases the bus to its idle state. receiving data. The master indicates a NACK by leaving the SDA line high during the ACK clock cycle. device. The DS75LX’s 7-bit bus address depends on the state of the external address pins A0–A2. See Table 6. high or low, connect the address line directly to VDD or GND. Do not use series resistors on these pins. the master is going to write data to the slave device then R/W¯¯ = 0. to the desired register as shown in Table 6.
Table 6. Address Configuration
0 FLOAT 0 0101000
0 FLOAT 1 0101001
0 FLOAT FLOAT 0110101
1 FLOAT 0 0101010
1 FLOAT 1 0101011
1 FLOAT FLOAT 0110110
DS75LX: Digital Thermometer and Thermostat with Extended Addressing 12 of 13 Writing to the DS75LX To write to the DS75LX, the master must generate a ST ART followed by an address byte containing the DS75LX bus address. The value of the R/W¯¯ bit must be a 0, which indicates that a write is about to take place. The DS75LX responds with an ACK after receiving the address byte. Th is must be followed by a pointer byte from the master, which tells the DS75LX which register is being written to. The DS75LX again responds with an ACK after receiving the pointer byte. Following this ACK the master devic e must immediately begin transmitting data to the DS75LX. When writing to the configuration register, the master must send one byte of data (see Figure 8a), and when writing to the T OS or T HYST registers the master must send two bytes of dat a (see Figure 8b). After receiving each data byte, the DS75LX responds with an ACK, and the transaction is finished with a STOP from the master. Software POR The soft POR command is hex 54. Issue a write command to the DS75LX. It responds with an ACK. If the next byte is a 0x54, the DS75LX will reset as if power had been cycled. No ACK is sent by the IC after the POR command is received. Reading from the DS75LX When reading from the DS75LX, if the pointer was already pointed to the desired register during a previous transaction, the read can be performed i mmediately without changing the pointer setting. In this case the master sends a START followed by an address byte containing the DS75LX bus address. The R/W¯¯ bit must be a 1, which tells the DS75LX that a read is being performed. After the DS75LX sends an ACK in response to the address byte, the DS75LX begins transmitting the requested data on the ne xt clock cycle. When readi ng from the configuration register, the DS75LX transmits one byte of data, after which the master must respond with a NACK followed by a STOP (see Figure 8c). For 2-byte reads (i.e., from the temperature, T OS, or THYST register), the DS75LX transmits two bytes of data, and the master must respond to the firs t data byte with an ACK and to the second byte with a NACK followed by a STOP (see Figure 8d). If only the most significant byte of data is needed, the master can issue a NACK followed by a STOP after reading the first data byte , in which case the transacti on will be the same as for a read from the configuration register. If the pointer is not already pointing to the desired register, the pointer must first be updated as shown in Figure 8e, which shows a pointer update followed by a single-byte read. The value of the R/W¯¯ bit in the initial address byte is a 0 (“write”) since the master is going to write a pointer byte to the DS75LX. After the DS75LX responds to the address byte with an ACK, the master sends a pointer byte that corresponds to the desired register. The master must then perform a repeated START followed by a standard 1- or 2-byte read sequence (with R/W ¯¯ = 1) as described in the previous paragraph.
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specificat ions. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PACKAGE DOCUMENT NO. 8-Pin SO 56-G2008-001 8-Pin µSOP/µMAX 21-0036
Figure 8. 2-Wire Interface Timing An address byte value of 1110010 corresponds to A0 connected to VDD, A1 connected to GND, and A2 floating.