DS5002FP DALLAS | Alldatasheet
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Technical content
1 of 25 REV: 030503 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS5002FP secure microprocessor chip is a secure version of the DS5001FP 128k soft microprocessor chip. In addition to the memory and I/O enhancements of the DS5001FP, the secure microprocessor chip incorporates the most sophisticated security features available in any processor. The security features of the DS5002FP include an array of mechanisms that are designed to resist all levels of threat, including observation, analysis, and physical attack. As a result, a massive effort is required to obtain any information about memory contents. Furthermore, the soft nature of the DS5002FP allows frequent modification of the secure information, thereby minimizing the value of any secure information obtained by such a massive effort. PIN CONFIGURATION
FEATURES
/g167/g328051-Compatible Microprocessor for Secure/Sensitive Applications Access 32kB, 64kB, or 128kB of NV SRAM for Program and/or Data Storage In-System Programming Through On-Chip Serial Port Can Modify Its Own Program or Data Memory in the End System /g167/g32Firmware Security Features Memory Stored in Encrypted Form Encryption Using On-Chip 64-Bit Key Automatic True Random Key Generator Self Destruct Input (SDI) Optional Top Coating Prevents Microprobe (DS5002FPM) Improved Security Over Previous Generations Protects Memory Contents from Piracy /g167/g32Crash-Proof Operation Maintains All Nonvolatile Resources for Over 10 Years in the Absence of Power Power-Fail Reset Early Warning Power-Fail Interrupt Watchdog Timer
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS5002FP-16 0°C to +70°C 80 QFP DS5002FPM-16 0°C to +70°C 80 QFP DS5002FP-16N -40°C to +85°C 80 QFP DS5002FMN-16 -40°C to +85°C 80 QFP Selector Guide appears at end of data sheet. DS5002FP Secure Microprocessor Chip www.maxim-ic.com P0.4AD4 CE2 PE2 BA9 P0.3/AD3 BA8 P0.2/AD2 BA13 P0.1/AD1 R/W P0.0/AD0 VCC0 VCC MSEL P1.0 BA14 P1.1 BA12 P1.2 BA7 P1.3 PE3 PE4 BA6 P2.6/A14 CE3 CE4 BD3 P2.5/A13 BD2 P2.4/A12 BD1 P2.3/A11 BD0 VLI SDI GND P2.2/A10 P2.1/A9 P2.0/A8 XTAL1 XTAL2 P3.7/RD P3.6/WR P3.5/TI PF VRST P3.4/T0 Dallas Semiconductor DS5002FP P1.4 BA5 P1.5 BA4 P1.6 BA3 P1.7 PROG BA2 RST BA1 P3.0/RXD BA0 P3.1/TXD P3.2/INT0 P3.3/INT1 BA11 P0.5/AD5 PE1 P0.6/AD6 BA10 P0.7/AD7 CE1 N.C. CE1N BD7 ALE BD6 N.C. BD5 P2.7/A15 BD4 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 QFP TOP VIEW
DS5002FP Secure Microprocessor Chip 2 of 25 ELECTRICAL SPECIFICATIONS The DS5002FP adheres to all AC and DC electrical specifications published for the DS5001FP. The absolute maximum ratings and unique specifications for the DS5002FP are listed below. ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.3V to (V CC + 0.5V) Voltage Range on VCC Relative to Ground -0.3V to +6.0V Operating Temperature Range -40 /g176C to +85/g176C Storage Temperature* -55 /g176C to +125/g176C Soldering Temperature See IPC/JEDEC J-STD-020A This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability. *Storage temperature is defined as the temperature of the device when V CC = 0V and V LI = 0V. In this state the contents of SRAM are not battery-backed and are undefined. DC CHARACTERISTICS (VCC = 5V ±10%, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Low Voltage V IL (Note 1) -0.3 +0.8 V Input High Voltage V IH1 (Note 1) 2.0 VCC + 0.3 V Input High Voltage (RST, XTAL1, PROG) VIH2 (Note 1) 3.5 VCC + 0.3 V Output Low Voltage at IOL = 1.6mA (Ports 1, 2, 3, PF) VOL1 (Notes 1, 13) 0.15 0.45 V Output Low Voltage at IOL = 3.2mA (Ports 0, ALE, BA150, BD70, R/W, CE1N, CE 14, PE 14, VRST) VOL2 (Note 1) 0.15 0.45 V Output High Voltage at IOH = -80µA (Ports 1, 2, 3) VOH1 (Note 1) 2.4 4.8 V Output High Voltage at IOH = -400µA (Ports 0, ALE, BA150, BD70, R/W, CE1N, CE 14, PE 14, VRST) VOH2 (Note 1) 2.4 4.8 V Input Low Current VIN = 0.45V (Ports 1, 2, 3) IIL -50 µA 0°C to +70°C -500 Transition Current; 1 to 0 VIN = 2.0V (Ports 1, 2, 3) ITL ITL -40°C to +85°C (Note 12) -600 µA µA SDI Input Low Voltage V ILS (Note 1) 0.4 V SDI Input High Voltage V IHS (Notes 1, 11) 2.0 V CCO V SDI Pulldown Resistor R SDI 25 60 k Ω
DS5002FP Secure Microprocessor Chip 3 of 25 DC CHARACTERISTICS (continued) (VCC = 5V ±10%, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage Current (Port 0, MSEL) IIL 0.45 < V IN < VCC +10 µA 0°C to +70°C 40 150 RST Pulldown Resistor R RE -40°C to +85°C (Note 12) 30 180 kΩ VRST Pullup Resistor RVR 4.7 k Ω PROG Pullup Resistor RPR 40 k Ω Lithium Supply Voltage V LI (Note 1) 2.5 4.0 V Operating Current at 16MHz I CC (Note 2) 36 mA 0°C to +70°C (Note 3) 7.0 Idle Mode Current at 12MHz I IDLE -40°C to +85°C (Notes 3, 12) 8.0 mA Stop Mode Current I STOP (Note 4) 80 µA Pin Capacitance C IN (Note 5) 10 pF Output Supply Voltage (VCCO) V CCO1 (Notes 1, 2) VCC -0.45 V 0°C to +70°C (Notes 1, 8) VLI -0.65 Output Supply Battery-Backed Mode (VCCO, CE14, PE 12) VCCO2 -40°C to +85°C (Notes 1, 8, 12) VLI -0.9 V Output Supply Current (Note 6) I CCO1 V CCO = VCC - 0.45V 75 mA 0°C to +70°C 5 75 Lithium-Backed Quiescent Current (Note 7) ILI -40°C to +85°C 75 500 nA BAT = 3.0V (0°C to +70°C) (Note 1) 4.0 4.25 BAT = 3.0V (-40°C to +85°C) (Notes 1, 12) 3.85 4.25 Reset Trip Point in Stop Mode BAT = 3.3V (0°C to +70°C) (Note 1) 4.4 4.65 AC CHARACTERISTICS (VCC = 0V to 5V, TA = 0°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.5V < VCC < 5.5V 2 SDI Pulse Reject (Note 10) t SPR VCC = 0V, VBAT = 2.9V 4 µs 4.5V < VCC < 5.5V 10 SDI Pulse Accept (Note 10) t SPA VCC = 0V, VBAT = 2.9V 50 µs
2 ALE Pulse Width t ALPW 2t CLK - 40 ns
3 Address Valid to ALE Low t AVALL t CLK - 40 ns
4 Address Hold After ALE Low t AVAAV t CLK - 35 ns
14 RD Pulse Width tRDPW 6t CLK - 100 ns
15 WR Pulse Width tWRPW 6t CLK - 100 ns
17 Data Hold after RD High tRDHDV 0 ns
18 Data Float after RD High tRDHDZ 2t CLK - 70 ns
21 ALE Low to RD or WR Low tALLRDL 3t CLK - 50 3t CLK + 50 ns
22 Address Valid to RD or WR
23 Data Valid to WR Going Low tDVWRL t CLK - 60 ns
25 Data Valid after WR High tWRHDV t CLK-50 ns
26 RD Low to Address Float tRDLAZ 0 ns
27 RD or WR High to ALE High tRDHALH t CLK - 40 t CLK + 50 ns
Figure 1. Expanded Data Memory Read Cycle
32 Slew Rate from V CCMIN to VLI t F 130 µs
33 Crystal Startup Time t CSU (Note 9)
34 Power-on Reset Delay t POR 21504 t CLK
Figure 4. Power Cycle Timing
35 Serial Port Clock Cycle Time t SPCLK 12t CLK µs
36 Output Data Setup to Rising Clock Edge t DOCH 10t CLK - 133 ns
37 Output Data Hold after Rising Clock Edge t CHDO 2t CLK - 117 ns
38 Clock Rising Edge to Input Data Valid t CHDV 10t CLK - 133 ns
39 Input Data Hold after Rising Clock Edge t CHDIV 0 ns
Figure 5. Serial Port Timing, Mode 0
40 Delay to Byte-Wide Address Valid from CE1,
41 Pulse Width of CE14, PE14, or CE1N tCEPW 4t CLK - 35 ns
42 Byte-Wide Address Hold After CE1, CE2, or
43 Byte-Wide Data Setup to CE1, CE2, or CE1N
44 Byte-Wide Data Hold After CE1, CE2, or CE1N
45 Byte-Wide Address Hold After CE14, PE14, or
46 Delay from Byte-Wide Address Valid CE14,
47 Byte-Wide Data Setup to CE14, PE14, or
48 Byte-Wide Data Hold After CE14, PE14, or
49 Byte-Wide Address Valid to R/W Active During
50 Delay from R/W Low to Valid Data Out During
51 Valid Data Out Hold Time from CE14, PE14, or
52 Valid Data Out Hold Time from R/W High tRWHDV 0 ns
53 Write Pulse Width (R/W Low Time) tRWLPW 6t CLK - 20 ns
Figure 6. Byte-Wide Bus Timing
DS5002FP Secure Microprocessor Chip 9 of 25 RPC AC CHARACTERISTICS, DBB READ (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 7) # PARAMETER SYMBOL MIN MAX UNITS
54 CS, A0 Setup to RD tAR 0 ns
55 CS, A0 Hold After RD tRA 0 ns
56 RD Pulse Width tRR 160 ns
57 CS, A0 to Data Out Delay tAD 130 ns
58 RD to Data Out Delay tRD 0 130 ns
59 RD to Data Float Delay tRDZ 85 ns
RPC AC CHARACTERISTICS, DBB WRITE (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 7) # PARAMETER SYMBOL MIN MAX UNITS
60 CS, A0 Setup to WR tAW 0 ns
61A CS, Hold After WR tWA 0 ns 61B A0, Hold After WR tWA 20 ns
62 WR Pulse Width tWW 160 ns
63 Data Setup to WR tDW 130 ns
64 Data Hold After WR tWD 20 ns
AC CHARACTERISTICS, DMA (VCC = 5V ±10%, TA = 0°C to +70°C.) # PARAMETER SYMBOL MIN MAX UNITS
65 DACK to WR or RD tACC 0 ns
66 RD or WR to DACK tCAC 0 ns
67 DACK to Data Valid tACD 0 130 ns
68 RD or WR to DRQ Cleared tCRQ 110 ns
AC CHARACTERISTICS, PROG (VCC = 5V ±10%, TA = 0°C to +70°C.) # PARAMETER SYMBOL MIN MAX UNITS
69 PROG Low to Active tPRA 48 CLKS
70 PROG High to Inactive tPRI 48 CLKS
Figure 7. RPC Timing Mode All parameters apply to both commercial and industrial temperature operation unless otherwise noted. Note 1: All voltages are referenced to ground. disconnected; RST = PORT0 = VCC, MSEL = VSS. PORT0 = VCC, RST = MSEL = VSS. Note 4: Stop mode ISTOP is measured with all output pins disconnected; PORT0 = VCC; XTAL2 not connected; RST = MSEL = XTAL1 = VSS. Note 5: Pin capacitance is measured with a test frequency: 1MHz, TA = +25°C. Note 6: ICCO1 is the maximum average operating current that can be drawn from VCCO in normal operation. VSDI should be /g163 VILS for IBAT max. Note 8: VCCO2 is measured with VCC < VLI, and a maximum load of 10 µA on VCCO. case specification on this time. guaranteed unless it is longer than tSPA. Note 11: VIHS minimum is 2.0V or VCCO, whichever is lower. Note 12: This parameter applies to industrial temperature operation. Note 13: PF pin operation is specified with VBAT /g179 3.0V.
DS5002FP Secure Microprocessor Chip 11 of 25 PIN DESCRIPTION PIN NAME FUNCTION 11, 9, 7, 5, 1, 79, 77, P0.0P0.7 General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in this mode, it does not require pullups. 15, 17, 19, 21, 25, 27, 29, 31 P1.0P1.7 General-Purpose I/O Port 1 49, 50, 51, 56, 58, 60, 64, 66 P2.0P2.7 General-Purpose I/O Port 2. Also serves as the MSB of the expanded address bus. 36 P3.0 RXD General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on-board UART. This pin should not be connected directly to a PC COM port. 38 P3.1 TXD General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on-board UART. This pin should not be connected directly to a PC COM port. 39 P3.2 INT0 General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt 0. 40 P3.3 INT1 General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt 1. 41 P3.4 T0 General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input. 44 P3.5 T1 General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input. 45 P3.6 WR General-Purpose I/O Port Pin. Also serves as the write strobe for Expanded bus operation. 46 P3.7 RD General-Purpose I/O Port Pin. Also serves as the read strobe for Expanded bus operation.
34 RST
Active-High Reset Input. A logic 1 applied to this pin activates a reset state. This pin is pulled down internally so this pin can be left unconnected if not used. An RC power-on reset circuit is not needed and is not recommended. 70 ALE Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus on port 0. This pin is normally connected to the clock input on a 373 type transparent latch. 47, 48 XTAL2, XTAL1 XTAL1, XTAL 2. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output.
52 GND Logic Ground
13 V CC V CC - +5V
12 V CCO
VCCO - VCC Output. This is switched between VCC and VLI by internal circuits based on the level of VCC. When power is above the lithium input, power is drawn from VCC. The lithium cell remains isolated from a load. When VCC is below VLI, the VCCO switches to the VLI source. VCCO should be connected to the VCC pin of an SRAM. 54 VLI Lithium Voltage Input. Connect to a lithium cell greater than VLIMIN and no greater than VLIMAX as shown in the electrical specifications. Nominal value is +3V. 16, 8, 18, 80, 76, 4, 6, 20, 24, 26, 28, 30, 33, 35, 37 BA140 Byte-Wide Address Bus Bits 140. This bus is combined with the nonmultiplexed data bus (BD70) to access NV SRAM. Decoding is performed using CE1 through CE4 . Therefore, BA15 is not actually needed. Read/write access is controlled by R/ W . BA140 connect directly to an 8k, 32k, or 128k SRAM. If an 8k RAM is used, BA13 and BA14 are unconnected. If a 128k SRAM is used, the micro converts CE2 and CE3 to serve as A16 and A15, respectively. 71, 69, 67, 65, 61, 59, 57, BD70 Byte-Wide Data Bus Bits 70. This 8-bit bidirectional bus is combined with the nonmultiplexed address bus (BA140) to access NV SRAM. Decoding is performed on CE1 and CE2. Read/write access is controlled by R/W. D70 connect directly to an SRAM, and optionally to a real-time clock or other peripheral.
10 R/W
Read/Write. This signal provides the write enable to the SRAMs on the byte-wide bus. It is controlled by the memory map and partition. The blocks selected as program (ROM) are write-protected.
74 CE1
Chip Enable 1. This is the primary decoded chip enable for memory access on the byte-wide bus. It connects to the chip-enable input of one SRAM. CE1 is lithium-backed. It remains in a logic-high inactive state when VCC falls below VLI.
2 CE2
Chip Enable 2. This chip enable is provided to access a second 32k block of memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, the micro converts CE2 into A16 for a 128k x 8 SRAM. CE2 is lithium-backed and remains at a logic high when VCC falls below VLI. 63 CE3 Chip Enable 3. This chip enable is provided to access a third 32k block of memory. It connects to the chip enable input of one SRAM. When MSEL = 0, the micro converts CE3
DS5002FP Secure Microprocessor Chip 12 of 25 PIN NAME FUNCTION into A15 for a 128k x 8 SRAM. CE3 is lithium-backed and remains at a logic high when VCC falls below VLI.
62 CE4
Chip Enable 4. This chip enable is provided to access a fourth 32k block of memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is unused. CE4 is lithium-backed and remains at a logic high when VCC falls below VLI.
78 PE1
Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-time clock such as the DS1283. PE1 is lithium-backed and will remain at a logic high when VCC falls below VLI. Connect PE1 to battery-backed functions only.
3 PE2
Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when the PES bit is set to a logic 1. PE2 is lithium-backed and will remain at a logic high when VCC falls below VLI. Connect PE2 to battery-backed functions only.
22 PE3
Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when the PES bit is set to a logic 1. PE3 is not lithium-backed and can be connected to any type of peripheral function. If connected to a battery-backed chip, it will need additional circuitry to maintain the chip enable in an inactive state when V CC < VLI.
23 PE4
Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when the PES bit is set to a logic 1. PE4 is not lithium-backed and can be connected to any type of peripheral function. If connected to a battery-backed chip, it will need additional circuitry to maintain the chip enable in an inactive state when VCC < VLI.
32 PROG
Invokes the bootstrap loader on a falling edge. This signal should be debounced so that only one edge is detected. If connected to ground, the micro enters bootstrap loading on power- up. This signal is pulled up internally.
42 VRST
This I/O pin (open drain with internal pullup) indicates that the power supply (VCC) has fallen below the VCCMIN level and the micro is in a reset state. When this occurs, the DS5002FP drives this pin to a logic 0. Because the micro is lithium-backed, this signal is guaranteed even when VCC = 0V. Because it is an I/O pin, it also forces a reset if pulled low externally. This allows multiple parts to synchronize their power-down resets. 43 PF This output goes to a logic 0 to indicate that the micro has switched to lithium backup. This corresponds to VCC < VLI. Because the micro is lithium-backed, this signal is guaranteed even when VCC = 0V. The normal application of this signal is to control lithium powered current to isolate battery-backed functions from non-battery-backed functions.
14 MSEL
Memory Select. This signal controls the memory size selection. When MSEL = +5V, the DS5002FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the DS5002FP expects to use a 128k x 8 SRAM. MSEL must be connected regardless of partition, mode, etc.
53 SDI
Self-Destruct Input. An active high on this pin causes an unlock procedure. This results in the destruction of Vector RAM, Encryption Keys, and the loss of power from VCCO. This pin should be grounded if not used. 72 CE1N This is a non-battery-backed version of CE1. It is not generally useful since the DS5002FP cannot be used with EPROM due to its encryption. 73 N.C. No Connect
DS5002FP Secure Microprocessor Chip 13 of 25 DETAILED DESCRIPTION The DS5002FP implements a security system that is an improved version of its predecessor, the DS5000FP. Like the DS5000FP, the DS5002FP loads and executes application software in encrypted form. Up to 128kB of standard SRAM can be accessed by its byte-wide bus. This RAM is converted by the DS5002FP into lithium- backed nonvolatile storage for program and data. Data is maintained for over 10 years at room temperature with a very small lithium cell. As a result, the contents of the RAM and the execution of the software appear unintelligible to the outside observer. The encryption algorithm uses an internally stored and protected key. Any attempt to discover the key value results in its erasure, rendering the encrypted contents of the RAM useless. The secure microprocessor chip offers a number of major enhancements to the software security implemented in the previous generation DS5000FP. First, the DS5002FP provides a stronger software encryption algorithm that incorporates elements of DES encryption. Second, the encryption is based on a 64-bit key word, as compared to the DS5000FPs 40-bit key. Third, the key can only be loaded from an on-chip true random-number generator. As a result, the true key value is never known by the user. Fourth, a self-destruct input (SDI) pin is provided to interface to external tamper-detection circuitry. With or without the presence of V CC, activation of the SDI pin has the same effect as resetting the security lock: immediate erasure of the key word and the 48-byte Vector RAM area. Fifth, an optional top-coating of the die prevents access of information using microprobing techniques. Finally, customer- specific versions of the DS5002FP are available that incorporate a one-of-a-kind encryption algorithm. When implemented as a part of a secure system design, a system based on the DS5002FP can typically provide a level of security that requires more time and resources to defeat than it is worth to unauthorized individuals who have reason to try. For a user who wants a preconstructed module using the DS5002FP, RAM, lithium cell, and a real-time clock, the DS2252T is available and described in a separate data sheet. BLOCK DIAGRAM Figure 8 is a block diagram illustrating the internal architecture of the DS5002FP. The DS5002FP is a secure implementation of the DS5001FP 128k soft microprocessor chip. As a result, it operates in an identical fashion to the DS5001FP, except where indicated. See the DS5001FP data sheet for operating details.
Figure 8. Block Diagram
DS5002FP Secure Microprocessor Chip 15 of 25 SECURE OPERATION OVERVIEW The DS5002FP incorporates encryption of the activity on its byte-wide address/data bus to prevent unauthorized access to the program and data information contained in the NV RAM. Loading an application program in this manner is performed by the bootstrap loader using the general sequence described below: 1) Clear security lock. 2) Set memory map configuration as for DS5001FP 3) Load application software 4) Set security lock 5) Exit loader Loading of application software into the program/data RAM is performed while the DS5002FP is in its bootstrap load mode. Loading is only possible when the security lock is clear. If the security lock has previously set, then it must be cleared by issuing the Z command from the bootstrap loader. Resetting the security lock instantly clears the previous key word and the contents of the Vector RAM. In addition, the bootstrap ROM writes 0s into the first 32k of external RAM. The users application software is loaded into external CMOS SRAM by the L command in scrambled form through on-chip encryptor circuits. Each external RAM address is an encrypted representation of an on-chip logical address. Thus, the sequential instructions of an ordinary program or data table are stored nonsequentially in RAM memory. The contents of the program/data RAM are also encrypted. Each byte in RAM is encrypted by a key- and address-dependent encryptor circuit such that identical bytes are stored as different values in different memory locations. The encryption of the program/data RAM is dependent on an on-chip 64-bit key word. The key is loaded by the ROM firmware just prior to the time that the application software is loaded, and is retained as nonvolatile information in the absence of V CC by the lithium backup circuits. After loading is complete, the key is protected by setting the on-chip security lock, which is also retained as nonvolatile information in the absence of V CC. Any attempt to tamper with the key word and thereby gain access to the true program/data RAM contents results in the erasure of the key word as well as the RAM contents. During execution of the application software, logical addresses on the DS5002FP that are generated from the program counter or data pointer registers are encrypted before they are presented on the byte-wide address bus. Op codes and data are read back and decrypted before they are operated on by the CPU. Similarly, data values written to the external nonvolatile RAM storage during program execution are encrypted before they are presented on the byte-wide data bus during the write operation. This encryption/decryption process is performed in real time such that no execution time is lost as compared to the non-encrypted DS5001FP or 8051 running at the same clock rate. As a result, operation of the encryptor circuitry is transparent to the application software. Unlike the DS5000FP, the DS5002FP chips security feature is always enabled. SECURITY CIRCUITRY The on-chip functions associated with the DS5002FPs software security feature are depicted in Figure 9 . Encryption logic consists of an address encryptor and a data encryptor. Although each encryptor uses its own algorithm for encrypting data, both depend on the 64-bit key word which is contained in the Encryption Key registers. Both the encryptors operate during loading of the application software and also during its execution.
Figure 9. Security Circuitry entire memory range, which is configured during bootstrap loading for access on the byte-wide bus. course of program execution. In a similar fashion, data is manipulated by the CPU in its true representation.
DS5002FP Secure Microprocessor Chip 17 of 25 protection measure, the address encryptor also generates dummy read access cycles whenever time is available during program execution. DUMMY READ CYCLES Like the DS5000FP, the DS5002FP generates a dummy read access cycle to non-sequential addresses in external RAM memory whenever time is available during program execution. This action has the affect of further complicating the task of determining the normal flow of program execution. During these pseudorandom dummy cycles, the RAM is read to all appearances, but the data is not used internally. Through the use of a repeatable exchange of dummy and true read cycles, it is impossible to distinguish a dummy cycle from a real one. ENCRYPTION ALGORITHM The DS5002FP incorporates a proprietary algorithm implemented in hardware, which performs the scrambling of address and data on the byte-wide bus to the SRAM. This algorithm has been greatly strengthened with respect to its DS5000FP predecessor. Improvements include: 1) 64-bit encryption key 2) Incorporation of DES-like operations to provide a greater degree of nonlinearity 3) Customizable encryption The encryption circuitry uses a 64-bit key value (compared to the DS5000FPs 40-bit key), which is stored on the DS5002FP die and protected by the Security Lock function described below. In addition, the algorithm has been strengthened to incorporate certain operations used in DES encryption, so that the encryption of both the addresses and data is highly nonlinear. Unlike the DS5000FP, the encryption circuitry in the DS5002FP is always enabled. Dallas Semiconductor can customize the encryption circuitry by laser programming the die to insure that a unique encryption algorithm is delivered to the customer. In addition, the customer-specific version can be branded as specified by the customer. Please contact Dallas Semiconductor for ordering information of customer-specific versions. ENCRYPTION KEY As described above, the on-chip 64-bit encryption key is the basis of both the address and data encryptor circuits. The DS5002FP provides a key management system, which is greatly improved over the DS5000FP. The DS5002FP does not give the user the ability to select a key. Instead, when the loader is given certain commands, the key is set based on the value read from an on-chip hardware random number generator. This action is performed just prior to actually loading the code into the external RAM. This scheme prevents characterization of the encryption algorithm by continuously loading new, known keys. It also frees the user from the burden of protecting the key selection process. The random number generator circuit uses the asynchronous frequency differences of two internal ring oscillator and the processor master clock (determined by XTAL1 and XTAL2). As a result, a true random number is produced. VECTOR RAM A 48-byte vector RAM area is incorporated on-chip, and is used to contain the reset and interrupt vector code in the DS5002FP. It is included in the architecture to help insure the security of the application program. If reset and interrupt vector locations were accessed from the external nonvolatile program/data RAM during the execution of the program, then it would be possible to determine the encrypted value of known addresses. This could be done by forcing an interrupt or reset condition and observing the resulting addresses on the byte-wide address/data bus. For example, it is known that when a hardware reset is applied the logical program address is forced to location 0000H and code is executed starting from this location. It would then be possible to determine the encrypted value (or physical address) of the logical address value 0000H by observing the address presented to the external RAM following a hardware reset. Interrupt vector address relationships could be determined in a similar fashion. By using the on-chip vector RAM to contain the interrupt and reset vectors, it is impossible to
DS5002FP Secure Microprocessor Chip 18 of 25 observe such relationships. Although it is very unlikely that an application program could be deciphered by observing vector address relationships, the vector RAM eliminates this possibility. Note that the dummy accesses mentioned above are conducted while fetching from vector RAM. The vector RAM is automatically loaded with the users reset and interrupt vectors during bootstrap loading. SECURITY LOCK Once the application program has been loaded into the DS5002FPs NV RAM, the security lock can be enabled by issuing the Z command in the bootstrap loader. While the security lock is set, no further access to program/data information is possible by the on-chip ROM. Access is prevented by both the bootstrap loader firmware and the DS5002FP encryptor circuits. Access to the NV RAM can only be regained by clearing the security lock by the U command in the bootstrap loader. This action triggers several events, which defeat tampering. First, the encryption key is instantaneously erased. Without the encryption key, the DS5002FP is no longer able to decrypt the contents of the RAM. Therefore, the application software can no longer be correctly executed, nor can it be read back in its true form by the bootstrap loader. Second, the vector RAM area is also instantaneously erased, so that the reset and vector information is lost. Third, the bootstrap loader firmware sequentially erases the encrypted RAM area. Lastly, the loader creates and loads a new random key. The Security Lock bit itself is constructed using a multiple-bit latch which is interlaced for self-destruct in the event of tampering. The lock is designed to set-up a domino-effect such that erasure of the bit will result in an unstoppable sequence of events that clears critical data including Encryption Key and Vector RAM. In addition, this bit is protected from probing by the top-coating feature mentioned below. SELF-DESTRUCT INPUT The self-destruct input (SDI) pin is an active-high input that is used to reset the security lock in response to an external event. The SDI input is intended to be used with external tamper-detection circuitry. It can be activated with or without operating power applied to the V CC pin. Activation of the SDI pin instantly resets the security lock and causes the same sequence of events described above for this action. In addition, power is momentarily removed from the byte-wide bus interface including the V CCO pin, resulting in the loss of data in external RAM. TOP LAYER COATING The DS5002FPM is provided with a special top-layer coating that is designed to prevent a probe attack. This coating is implemented with second-layer metal added through special processing of the microcontroller die. This additional layer is not a simple sheet of metal, but rather a complex layout that is interwoven with power and ground, which are in turn connected to logic for the encryption key and the security lock. As a result, any attempt to remove the layer or probe through it results in the erasure of the security lock and/or the loss of encryption key bits. BOOTSTRAP LOADING Initial loading of application software into the DS5002FP is performed by firmware within the on-chip bootstrap loader communicating with a PC by the on-chip serial port in a manner that is almost identical to that for the DS5001FP. The user should consult the DS5001FP data sheet as a basis of operational characteristics of this firmware. Certain differences in loading procedure exist in order to support the security feature. These differences are documented below. Table 1 summarizes the commands accepted by the bootstrap loader. When the bootstrap loader is invoked, portions of the 128-byte scratchpad RAM area are automatically overwritten with 0s, and then used for variable storage for the bootstrap firmware. Also, a set of 8 bytes are generated using the random number generator circuitry and are saved as a potential word for the 64-bit encryption key. Any read or write operation to the DS5002FPs external program/data SRAM can only take place if the security lock bit is in a cleared state. Therefore, the first step in loading a program should be the clearing of the security lock bit through the U command.
Table 1. Serial Bootstrap Loader Commands using any bootstrap command or by any other means. are provided in the Secure Microcontroller Users Guide. between 32k and 128k of SRAM, a lithium cell, and a real-time clock. This is packaged in a 40-pin SIMM module. portion of memory that is actually mapped to the byte-wide bus by selecting the program range and data range.
Secure Microcontroller Users Guide. Figure 10. Memory Map in Nonpartitionable Mode (PM = 1)
Figure 14. Connection to 64k x 8 SRAM in the electrical specifications.
DS5002FP Secure Microprocessor Chip 24 of 25 SELECTOR GUIDE PART TEMP RANGE MAX CLOCK SPEED (MHz) PIN- PACKAGE DS5002FP-16 0°C to +70°C 16 80 QFP DS5002FPM-16 0°C to +70°C 16 80 QFP DS5002FP-16N -40°C to +85°C 16 80 QFP DS5002FMN-16 -40°C to +85°C 16 80 QFP **Internal Microprobe Shield
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline info rmation, go to www.maxim-ic.com/DallasPackInfo.) MM DIM MIN MAX A 3.40 A1 0.25 A2 2.55 2.87 B 0.30 0.50 C 0.13 0.23 D 23.70 24.10 D1 19.90 20.10 E 17.70 18.10 E1 13.90 14.10 e 0.80 BSC L 0.65 0.95 56-G4005-001
DS5002FP Secure Microprocessor Chip 25 of 25
REVISION HISTORY
112795 Original release. 073096 Change VCC02 specification from VLI - 0.5 to VLI - 0.65 (PCN F62501). Update mechanical specifications. 111996 Change V CC01 from VCC - 0.3 to VCC - 0.35. 061297 PF signal moved from VOL2 test specification to VOL1. PCN No. (D72502). AC characteristics for battery-backed SDI pulse specification added. 051499 Reduced absolute maximum voltage to VCC + 0.5V. Added note clarifying storage temperature specification is for nonbattery-backed state. Deleted IBAT specification (Duplicate of ILI specification). Changed RRE min (industrial temp range) from 40kΩ to 30kΩ. Changed VPFW max (industrial temp range) from 4.5V to 4.6V. Added industrial specification for ILI. Reduced tCE1HOV and tCEHDV from 10ns to 0ns. 052599 Minor revisions and approval. 062102 Update V CCO and ICCO1 specifications to reflect 0.45V internal voltage drop instead of 0.35V. 030403 Reset Trip Point in Stop Mode (DC Characteristics) with BAT = 3.0V was changed to 3.3V (original issue was 3.3V).