DS5000

DS5000_1 DALLAS | Alldatasheet

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DS5000(T) Soft Microcontroller Module DS5000(T) 021998 1/19

FEATURES

• 8–bit 8051 compatible Microcontroller adapts to task– at–hand: – 8 or 32K bytes of nonvolatile RAM for program and/or data memory storage – Initial downloading of software in end system via on–chip serial port – Capable of modifying its own program and/or data memory in end use
• Crashproof operation: – Maintains all nonvolatile resources for 10 years in the absence of VCC – Power–fail reset – Early warning power–fail interrupt – Watchdog timer
• Software Security Feature: – Executes encrypted software to prevent unau- thorized disclosure
• On–chip, full–duplex serial I/O ports
• Two on–chip timer/event counters
• 32 parallel I/O lines
• Compatible with industry standard 8051 instruction set and pinout
• Optional Permanently Powered Real–Time Clock (DS5000T) PIN ASSIGNMENT 20 21 40–PIN ENCAPSULATED PACKAGE 40P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD P3.0 TXD P3.1 INT0 P3.2 INT1 P3.3 T0 P3.4 T1 P3.5 WR P3.6 RD P3.7 XTAL2 XTAL1 GND V CC P0.0 AD0 P0.1 AD1 P0.2 AD2 P0.3 AD3 P0.4 AD4 P0.5 AD5 P0.6 AD6 P0.7 AD7 EA ALE PSEN P2.7 A15 P2.6 A14 P2.5 A13 P2.4 A12 P2.3 A11 P2.2 A10 P2.1 A9 P2.0 A8

DESCRIPTION

The DS5000(T) Soft Microcontroller Module is a fully 8051 compatible 8–bit CMOS microcontroller that offers “softness” in all aspects of its application. This is ac- complished through the comprehensive use of nonvola- tile technology to preserve all information in the ab- sence of system VCC . The internal program/data memory space is implemented using either 8K or 32K bytes of nonvolatile CMOS SRAM. Furthermore, internal data registers and key configuration registers are also nonvolatile. An optional real time clock gives permanently powered timekeeping. The clock keeps time to a hundredth of a second using an on–board crystal.

DS5000(T) 021998 2/19

ORDERING INFORMATION

PART NUMBER RAM SIZE MAX CRYSTAL SPEED TIMEKEEPING? DS5000–8–16 8K bytes 16 MHz No DS5000–32–16 32K bytes 16 MHz No DS5000–8–16 8K bytes 16 MHz Yes DS5000T–32–16 32K bytes 16 MHz Yes Operating information is contained in the User’s Guide section of the Secure Microcontroller Data Book. This data sheet provides ordering information, pinout, and electrical specification. DS5000(T) BLOCK DIAGRAM Figure 1 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ P0.0–0.7 P1.0–1.7 P2.0–2.7 P3.0–3.7 RST ALE PSEN EA XTAL1 XTAL2 GND VCC DS5000FP ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ VCCO CE1 R/W CE2 BYTE–WIDE DATA BUS BYTE–WIDE ADDRESS BUS +3V 8K OR 32K SRAM (DS5000T) REAL TIME CLOCK DS5000(T)

DS5000(T) 021998 3/19 PIN DESCRIPTION PIN NUMBER DESCRIPTION 9 RST – Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally so this pin can be left unconnected if not used. 10 P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on board UART. This pin should not be connected directly to a PC COM port. 11 P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on board UART. This pin should not be connected directly to a PC COM port. 12 P3.2 INT0. General purpose I/O port pin 3.2. Also serves as the active low External Interrupt 0. 13 P3.3 INT1. General purpose I/O port pin 3.3. Also serves as the active low External Interrupt 1. 16 P3.6 WR. General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation. 17 P3.7 RD. General purpose I/O port pin. Also serves as the read strobe for Expanded bus operation. 18, 19 XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output. 20 GND. Logic ground. 21–28 P2.0–P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address bus. 29 PSEN – Program Store Enable. This active low signal is used to enable an external program memory when using the Expanded bus. It is normally an output and should be unconnected if not used. PSEN also is used to invoke the Bootstrap Loader. At this time, PSEN will be pulled down externally. This should only be done once the DS5000(T) is already in a reset state. The device that pulls down should be open drain since it must not interfere with PSEN under normal operation. 30 ALE – Address Latch Enable. Used to de–multiplex the multiplexed Expanded Address/Data bus on Port 0. This pin is normally connected to the clock input on a ’373 type transparent latch. When using a parallel programmer, this pin also assumes the PROG function for pro- gramming pulses. 31 EA – External Access. This pin forces the DS5000(T) to behave like an 8031. No internal memory (or clock) will be available when this pin is at a logic low. Since this pin is pulled down internally, it should be connected to +5V to use NV RAM. In a parallel programmer, this pin also serves as V PP for super voltage pulses.

DS5000(T) 021998 4/19 PIN NUMBER DESCRIPTION 32–39 P0.7–P0.0. General purpose I/O Port 0. This port is open–drain and can not drive a logic 1. It requires external pull–ups. Port 0 is also the multiplexed Expanded Address/Data bus. When used in this mode, it does not require pull–ups. 40 VCC – +5 volts. INSTRUCTION SET The DS5000(T) executes an instruction set which is ob- ject code compatible with the industry standard 8051 microcontroller. As a result, software development packages which have been written for the 8051 are compatible with the DS5000(T), including cross–as- semblers, high–level language compilers, and debug- ging tools. A complete description for the DS5000(T) instruction set is available in the User’s Guide section of the Secure Microcontroller Data Book. MEMORY ORGANIZATION Figure 2 illustrates the address spaces which are ac- cessed by the DS5000(T). As illustrated in the figure, separate address spaces exist for program and data memory. Since the basic addressing capability of the machine is 16 bits, a maximum of 64K bytes of program memory and 64K bytes of data memory can be ac- cessed by the DS5000(T) CPU. The 8K or 32K byte RAM area inside of the DS5000(T) can be used to con- tain both program and data memory. The Real time Clock (RTC) in the DS5000T is reached in the memory map by setting a SFR bit. The MCON.2 bit (ECE2) is used to select an alternate data memory map. While ECE2=1, all MOVXs will be routed to this alternate memory map. The real time clock is a serial device that resides in this area. A full description of the RTC access and example software is given in the User’s Guide section of the Secure Microcontroller Data Book. If the ECE2 bit is set on a DS5000 without a timekeeper, the MOVXs will simply go to a nonexistent memory. Software execution would not be affected otherwise.

DS5000(T) 021998 5/19 DS5000(T) LOGICAL ADDRESS SPACES Figure 2 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ 64K 32K ÏÏ ÏÏ ÎÎ ÎÎ NV RAM PROGRAM MEMORY NV RAM DATA MEMORY SPECIAL FUNCTION REGISTERSDATA REGISTERS INTERNAL REGISTERS LEGEND: = ON–CHIP REGISTERS = ACCESSED VIA EXPANDED BUS = NV RAM MEMORY PROGRAM MEMORY DATA MEMORY PARTITION ADDR. RANGE ADDR. 127 255 128 64K 32K PROGRAM LOADING The Program Load Modes allow initialization of the NV RAM Program/Data Memory. This initialization may be performed in one of two ways: 1. Serial Program Loading which is capable of per- forming Bootstrap Loading of the DS5000(T). This feature allows the loading of the application program to be delayed until the DS5000(T) is installed in the end system. Dallas Semiconductor strongly recom- mends the use of serial program loading because of its versatility and ease of use. 2. Parallel Program Load cycles which perform the ini- tial loading from parallel address/data information presented on the I/O port pins. This mode is timing– set compatible with the 8751H microcontroller pro- gramming mode. The DS5000(T) is placed in its Program Load configura- tion by simultaneously applying a logic 1 to the RST pin and forcing the PSEN line to a logic 0 level. Immediately following this action, the DS5000(T) will look for a paral- lel Program Load pulse, or a serial ASCII carriage return (0DH) character received at 9600, 2400, 1200, or 300 bps over the serial port. The hardware configurations used to select these modes of operation are illustrated in Figure 3.

11.059 MHz

these cycles is illustrated in the electrical specs. Figure 3. Port pins 2.7 and 2.6 must be either open or communication with the DS5000(T). format which existing 8051 cross–assemblers output.

DS5000(T) 021998 7/19 PARALLEL PROGRAM LOAD CYCLES Table 1 MODE RST PSEN PROG EA P2.7 P2.6 P2.5 Program 1 0 0 V PP 10X Security Set 1 0 0 V PP 11X Verify 1 X X 1 0 0 X Prog Expanded 1 0 0 V PP 010 Verify Expanded 1 0 1 1 0 1 0 Prog MCON or Key registers 1 0 0 V PP 011 Verify MCON registers 1 0 1 1 0 1 1 The Parallel Program Cycle is used to load a byte of data into a register or memory location within the DS5000(T). The Verify Cycle is used to read this byte back for comparison with the originally loaded value to verify proper load ing. The Security Set Cycle may be used to enable and the Software Security feature of the DS5000(T). One may also enter bytes for the MCON register or for the five encryption registers using the Pro- gram MCON cycle. When using this cycle, the absolute register address must be presented at Ports 1 and 2 as in the normal program cycle (Port 2 should be 00H). The MCON contents can likewise be verified using the Verify MCON cycle. When the DS5000(T) first detects a Parallel Program Strobe pulse or a Security Set Strobe pulse while in the Program Load Mode following a Power–On Reset, the internal hardware of the DS5000(T) is initialized so that an existing 4K byte program can be programmed into a DS5000(T) with little or no modification. This initializa- tion automatically sets the Range Address for 8K bytes and maps the lowest 4K byte bank of Embedded RAM as program memory. The next 4K bytes of Embedded RAM are mapped as Data Memory. In order to program more than 4K bytes of program code, the Program/Verify Expanded cycles can be used. Up to 32K bytes of program code can be entered and verified. Note that the expanded 32K byte Program/ Verify cycles take much longer than the normal 4K byte Program/Verify cycles. A typical parallel loading session would follow this pro- cedure. First, set the contents of the MCON register with the correct range and partition only if using expand- ed programming cycles. Next, the encryption registers can be loaded to enable encryption of the program/data memory (not required). Then, program the DS5000(T) using either normal or expanded program cycles and check the memory contents using Verify cycles. The last operation would be to turn on the security lock fea- ture by either a Security Set cycle or by explicitly writing to the MCON register and setting MCON.0 to a 1.

DS5000(T) 021998 8/19 SERIAL LOADER BAUD RATES FOR DIFFERENT CRYSTAL FREQUENCIES Table 2 CRYSTAL FREQ (MHz) BAUD RATE CRYSTAL FREQ (MHz) 300 1200 2400 9600 19200 57600

14.7456 Y Y Y Y

11.0592 Y Y Y Y Y Y

9.21600 Y Y Y Y

7.37280 Y Y Y Y

5.52960 Y Y Y Y

1.84320 Y Y Y Y

A complete description for all operational aspects of the DS5000(T), is provided in the User’s Guide section of the Secure Microcontroller Data Book. DEVELOPMENT SUPPORT Dallas Semiconductor offers a kit package for develop- ing and testing user code. The DS5000TK Evaluation Kit allows the user to download Intel hex formatted code directly to the DS5000(T) from a PC–XT/AT or compat- ible computer. The kit consists of a DS5000T–32, an in- terface pod, demo software, and an RS232 connector that attaches to the COM1 or COM2 serial port of a PC. See the Development Tools section of the Secure Microcontroller Data Book for further details.

DS5000(T) 021998 9/19 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground –0.3V to +7.0V Operating Temperature 0 °C to 70°C Storage Temperature –40 °C to +70°C Soldering Temperature 260 °C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC CHARACTERISTICS (tA = 0°C to70°C; VCC = 5V + 5%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Low Voltage VIL –0.3 0.8 V 1 Input High Voltage VIH1 2.0 VCC +0.3 V 1 Input High Voltage RST, XTAL1 VIH2 3.5 VCC +0.3 V 1 Output Low Voltage @ IOL =1.6 mA (Ports 1, 2, 3) VOL1 0.15 0.45 V Output Low Voltage @ IOL =3.2 mA (Ports 0, ALE, PSEN) VOL2 0.15 0.45 V 1 Output High Voltage @ IOH =–80 µA (Ports 1, 2, 3) VOH1 2.4 4.8 V 1 Output High Voltage @ IOH =–400 µA (Ports 0, ALE, PSEN) VOH2 2.4 4.8 V 1 Input Low Current VIN = 0.45V (Ports 1, 2, 3) IIL –50 µA Transition Current; 1 to 0 VIN = 2.0V (Ports 1, 2, 3) ITL –500 µA Input Leakage Current 0.45 < VIN < VCC (Port 0) IL +10 µA RST, EA Pulldown Resistor R RE 40 125 KΩ Stop Mode Current ISM 80 µA 4 Power–Fail Warning Voltage VPFW 4.15 4.6 4.75 V 1 Minimum Operating Voltage VCCmin 4.05 4.5 4.65 V 1 Programming Supply Voltage (Parallel Program Mode) VPP 12.5 13 V 1 Program Supply Current IPP 15 20 mA Operating Current DS5000–8K@8 MHz DS5000–32K @ 12 MHz DS5000T–32–16 @ 16 MHz ICC 25.2 35.7 45.6 mA 2 Idle Mode Current @ 12 MHz ICC 4.5 6.2 mA 3

DS5000(T) 021998 10/19 AC CHARACTERISTICS EXPANDED BUS MODE TIMING SPECIFICATIONS (tA = 0°C to70°C; VCC = 5V + 5%) # PARAMETER SYMBOL MIN MAX UNITS 1 Oscillator Frequency 1/tCLK 1.0 16 MHz

2 ALE Pulse Width tALPW 2tCLK –40 ns

3 Address Valid to ALE Low tAVALL tCLK –40 ns

4 Address Hold After ALE Low tAVAAV tCLK –35 ns

5 ALE Low to Valid Instr. In @12 MHz @16 MHz tALLVI 4tCLK –150 4tCLK –90 ns ns

6 ALE Low to PSEN Low tALLPSL tCLK –25 ns

7 PSEN Pulse Width tPSPW 3tCLK –35 ns

8 PSEN Low to Valid Instr. In @12 MHz @16 MHz tPSLVI 3tCLK –150 3tCLK –90 ns ns 9 Input Instr. Hold after PSEN Going High tPSIV 0 ns 10 Input Instr. Float after PSEN Going High tPSIX tCLK –20 ns

11 Address Hold after PSEN Going High tPSAV tCLK –8 ns

12 Address Valid to Valid Instr. In @12 MHz @16 MHz tAVVI 5tCLK –150 5tCLK –90 ns ns

13 PSEN Low to Address Float tPSLAZ 0 ns

14 RD Pulse Width tRDPW 6tCLK –100 ns

15 WR Pulse Width tWRPW 6tCLK –100 ns

16 RD Low to Valid Data In @12 MHz

@16 MHz tRDLDV 5tCLK –165 5tCLK –105 ns ns

17 Data Hold after RD High tRDHDV 0 ns

18 Data Float after RD High tRDHDZ 2tCLK –70 ns

19 ALE Low to Valid Data In @12 MHz

@16 MHz tALLVD 8CLK –150 8tCLK –90 ns ns 20 Valid Addr. to Valid Data In @12 MHz @16 MHz tAVDV 9tCLK –165 9tCLK –105 ns ns

21 ALE Low to RD or WR Low tALLRDL 3tCLK –50 3tCLK +50 ns

22 Address Valid to RD or WR Low tAVRDL 4tCLK –130 ns

23 Data Valid to WR Going Low tDVWRL tCLK –60 ns

24 Data Valid to WR High @12 MHz

@16 MHz tDVWRH 7tCLK –150 7tCLK –90 ns ns

25 Data Valid after WR High tWRHDV tCLK –50 ns

26 RD Low to Address Float tRDLAZ 0 ns

27 RD or WR High to ALE High tRDHALH tCLK –40 tCLK +50 ns

PORT 2 P2.7–P2.0 OR A15–A8 FROM DPH A15–A8 FROM PCH DATA IN INSTR IN A7–A0 (PCL) A7–A0 (Rn OR DPL) RD DS5000(T) 021998 11/19 EXPANDED PROGRAM MEMORY READ CYCLE 6 7 3 4 ALE PSEN PORT 0 PORT 2 A7–A0 A15–A8 INSTR IN A7–A0 A15–A8 EXPANDED DATA MEMORY READ CYCLE

DS5000(T) 021998 12/19 EXPANDED DATA MEMORY WRITE CYCLE 3 4 24 ALE PORT 0 PORT 2 WR PSEN DATA OUTA7–A0 (Rn OR DPL) A7–A0 (PCL) INSTR IN P2.7–P2.0 OR A15–A8 FROM PDH A15–A8 FROM PCH EXTERNAL CLOCK TIMING

DS5000(T) 021998 13/19 AC CHARACTERISTICS (cont’d) EXTERNAL CLOCK DRIVE (tA = 0°C to70°C; VCC = 5V + 5%) # PARAMETER SYMBOL MIN MAX UNITS

28 External Clock High Time @12 MHz

@16 MHz tCLKHPW 20 ns ns

29 External Clock Low Time @12 MHz

@16 MHz tCLKLPW 20 ns ns

30 External Clock Rise Time @12 MHz

@16 MHz tCLKR 20 ns ns

31 External Clock Fall Time @12 MHz

@16 MHz tCLKF 20 ns ns AC CHARACTERISTICS (cont’d) SERIAL PORT TIMING – MODE 0 (tA = 0°C to70°C; VCC = 5V + 5%) # PARAMETER SYMBOL MIN MAX UNITS

35 Serial Port Cycle Time tSPCLK 12tCLK µs

36 Output Data Setup to Rising Clock Edge tDOCH 10tCLK –133 ns

37 Output Data Hold after Rising Clock EdgetCHDO 2tCLK –117 ns

38 Clock Rising Edge to Input Data Valid tCHDV 10tCLK –133 ns

39 Input Data Hold after Rising Clock EdgetCHDIV 0 ns

SERIAL PORT TIMING – MODE 0 INSTRUCTION 01 2 3 4 5 6 7 8 ALE CLOCK DATA OUT INPUT DATA 01 2 3 4 5 6 7 SET TI SET RI VALID VALIDVALIDVALIDVALIDVALIDVALID CLEAR RI WRITE TO SBUF REGISTER

DS5000(T) 021998 14/19 AC CHARACTERISTICS (cont’d) POWER CYCLING TIMING (tA = 0°C to70°C; VCC = 5V + 5%) # PARAMETER SYMBOL MIN MAX UNITS 32 Slew Rate from VCCmin to 3.3V tF 40 µs

33 Crystal Start up Time tCSU (note 5)

34 Power–On Reset Delay tPOR 21504 tCLK

DS5000(T) 021998 15/19 AC CHARACTERISTICS (cont’d) PARALLEL PROGRAM LOAD TIMING (tA = 0°C to70°C; VCC = 5V + 5%) # PARAMETER SYMBOL MIN MAX UNITS 40 Oscillator Frequency 1/tCLK 1.0 12.0 MHz

41 Address Setup to PROG Low tAVPRL 0

42 Address Hold after PROG High tPRHAV 0

43 Data Setup to PROG Low tDVPRL 0

44 Data Hold after PROG High tPRHDV 0

45 P2.7, 2.6, 2.5 Setup to VPP tP27HVP 0

46 VPP Setup to PROG Low tVPHPRL 0

47 VPP Hold after PROG Low tPRHVPL 0

48 PROG Width Low tPRW 2400 tCLK

49 Data Output from Address Valid tAVDV 48

1800* tCLK 50 Data Output from P2.7 Low tDVP27L 48 1800* tCLK 51 Data Float after P2.7 High tP27HDZ 0 48 1800* tCLK

52 Delay to Reset/PSEN Active after

Power–On tPORPV 21504 tCLK

53 Reset/PSEN Active (or Verify Inactive) to

54 VPP Inactive (Between Program Cycles) tVPPPC 1200 tCLK

55 Verify Active Time tVFT 48

2400* tCLK * Second set of numbers refers to expanded memory programming up to 32K bytes.

DS5000(T) 021998 16/19 PARALLEL PROGRAM LOAD TIMING ADDRESS ADDRESS ADDRESSP2.3–P2.0 P1.7–P1.0 PORT ALE/PROG VIH VPP EA /VPP P2.7, P2.6, P2.5 ACTIVE DATA DATA DATA +5V VCC RST PSEN 4241 43 44 52 53 50 53 CAPACITANCE (test frequency = 1 MHz; tA = 25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Output Capacitance C O 10 pF Input Capacitance C I 10 pF

DS5000(T) 021998 17/19 DS5000(T) TYPICAL ICC VS. FREQUENCY Icc CURRENT (mA) 30.0 25.0 20.0 15.0 10.0 5.0 0.0 5.0 10.0 15.0 NORMAL OPERATION IDLE MODE OPERATION FREQUENCY OF OPERATION (MHz) (VCC =+5V, tA=25°C) 45.0 40.0 35.0

16 MHz

12 MHz

8 MHz

Normal operation is measured using: 1) External crystals on XTAL1 and 2 2) All port pins disconnected 3) RST=0 volts and EA=V CC 4) Part performing endless loop writing to internal memory. Idle mode operation is measured using: 1) External clock source at XTAL1; XTAL2 floating 2) All port pins disconnected 3) RST=0 volts and EA=V CC 4) Part set in IDLE mode by software.

DS5000(T) 021998 18/19 NOTES: 1. All voltages are referenced to ground. 2. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR , tCLKF =10 ns, VIL = 0.5V; XTAL2 disconnected; EA = RST = PORT0 = VCC . 3. Idle mode ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR , tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; EA = PORT0 = VCC , RST = VSS . 4. Stop mode ICC is measured with all output pins disconnected; EA = PORT0 = V CC ; XTAL2 not connected; RST = VSS . 5. Crystal start–up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on–chip oscillator. The user should check with the crystal vendor for the worst case spec on this time. PACKAGE DRAWING DIM MIN MAX INCHES A IN. B IN. C IN. D IN. E IN. F IN. G IN. H IN. I IN. 2.080 2.100 0.680 0.700 0.290 0.325 0.090 0.110 0.030 0.060 0.145 0.185 0.016 0.020 0.590 0.610 0.009 0.015 A 1.900 D C G E F B I H

DS5000(T) 021998 19/19 DATA SHEET REVISION SUMMARY The following represent the key differences between the dates 07/20/95 to 07/24/96 of the DS5000(T) data sheet. Please review this summary carefully. 1. Correct Figure 3 to show RST active high. 2. Add Data Sheet Revision Summary.