DS4550 DALLAS | Alldatasheet
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Technical content
Features
♦ Programmable Replacement for Mechanical Jumpers and Switches ♦ Nine NV Inputs/Outputs ♦ 64-Byte NV User Memory (EEPROM) ♦ I2C-Compatible Serial Interface and JTAG ♦ Up to 8 Devices can be Multidropped on the Same I2C Bus ♦ IEEE 1149.1 Boundary Scan Compliant ♦ Open-Drain Outputs with Configurable Pullups ♦ Outputs Capable of Sinking 16mA ♦ Low Power Consumption ♦ Wide Operating Voltage Range: 2.7V to 5.5V ♦ Operating Temperature Range: -40°C to +85°C DS4550 I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory GND I/O_8 I/O_7 I/O_6I/O_3 I/O_2 I/O_1 I/O_0 TOP VIEW I/O_5 TDO TDITCK I/O_4 SCL SDAVCC TMS TSSOP DS4550 VCC FPGA CLOCK GENERATOR CPU SPEED SELECT GND 0.1µF VCC 4.7k I2C INTERFACE JTAG INTERFACE DS4550 SCL SDA TCK TMS TDI TDO I/O_0 I/O_1 I/O_2 I/O_3 I/O_4 I/O_5 I/O_6 I/O_7 I/O_8 Pin Configuration Typical Operating Circuit Rev 0; 9/04 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
PART TEMP RANGE PIN-PACKAGE DS4550E -40 °C to +85°C 20 TSSOP Add “/T&R” for tape and reel orders. I2C is a trademark of Philips Corp. Purchase of I 2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I 2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS (TA = -40°C to +85°C) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on VCC, SDA, and SCL Pins Voltage on A0, A1, A2, TCK, TMS, TDI, and I/O_n [n = 0 to 8] not to exceed +6.0V. Specification PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V CC (Note 1) +2.7 +5.5 V Input Logic 1 V IH 0.7 x VCC VCC + 0.3 V Input Logic 0 V IL -0.3 0.3 x VCC V DC ELECTRICAL CHARACTERISTICS (VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Standby Current I STBY (Note 2) 2 10 µA Input Leakage I L -1.0 +1.0 µA Input Current each I/O pin I I/O 0.4 < VI/O < 0.9 x VCC -1.0 +1.0 µA 3mA sink current 0.4 Low-Level Output Voltage (SDA) VOL SDA 6mA sink current 0.6 V I/O Pins Low-Level Output Voltage VOL I/O 16mA sink current 0.4 V Low-Level Output Voltage (TDO) VOL TDO 4mA sink current 0.4 V High-Level Output Voltage (TDO) VOH TDO 1mA source current 2.4 V I/O Pin Pullup Resistors R PU 4.0 5.5 7.5 k Ω TMS, TDI Pullup Resistors R JPU 7.5 10 12.5 kΩ I/O Capacitance C I/O (Note 3) 10 pF Power-On Reset Voltage V POR 1.6 V
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory AC ELECTRICAL CHARACTERISTICS-–I2C Interface (See Figure 5) (VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Timing referenced to V IL(MAX) and VIH(MIN).) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCL Clock Frequency f SCL (Note 4) 0 400 kHz Bus Free Time Between Stop and Start Conditions tBUF 1.3 µs Hold Time (Repeated) Start Condition tHD:STA (Note 5) 0.6 µs Low Period of SCL t LOW 1.3 µs High Period of SCL t HIGH 0.6 µs Data Hold Time tHD:DAT 0 0.9 µs Data Setup Time tSU:DAT 100 ns Start Setup Time t SU:STA 0.6 µs SDA and SCL Rise Time t R (Note 6) 20 + 0.1CB 300 ns SDA and SCL Fall Time t F (Note 6) 20 + 0.1CB 300 ns Stop Setup Time tSU:STO 0.6 µs SDA and SCL Capacitive Loading CB (Note 6) 400 pF EEPROM Write Time t WR I2C EEPROM write (Note 7) 10 20 ms AC ELECTRICAL CHARACTERISTICSJTAG Interface (See Figure 1) (VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS TCK Clock Period t 1 1000 ns TCK Clock High/Low Time t 2, t3 (Note 8) 50 500 ns TCK to TDI, TMS Setup Time t 4 15 ns TCK to TDI, TMS Hold Time t 5 10 ns TCK to TDO Delay t 6 50 ns TCK to TDO High-Z Delay t 7 50 ns EEPROM Write Time t WR JTAG EEPROM write (Note 9) 10 20 ms
Note 1: All voltages referenced to ground. Note 2: ISTBY is specified with SDA = SCL = TMS = TDI = VCC, outputs floating, and inputs connected to VCC or GND. Note 3: Guaranteed by design. Note 4: Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard mode timing. Note 5: After this period, the first clock pulse is generated. Note 6: CBtotal capacitance of one bus line in picofarads. EEPROM write time begins after a stop condition occurs. Note 8: TCK can be stopped either high or low. ble during the EEPROM write. Figure 1. JTAG Timing Diagram
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory SUPPLY CURRENT vs. SUPPLY VOLTAGE DS4550 toc01 SUPPLY VOLTAGE (V) SUPPLY CURRENT (µA) 54.543.53 0.5 1.5 2.5 5.5 I/O0-I/O7 CONTROL BITS = 0 I/O0-I/O7 PULLUPS DISABLED V CC = SDA = SCL = TCK SUPPLY CURRENT vs. TEMPERATURE DS4550 toc02 TEMPERATURE (°C) SUPPLY CURRENT (µA) 806040200-20 0.5 1.5 2.5 -40 VCC = SDA = SCL = 5.5V = TCK VCC = SDA = SCL = 2.7V = TCK I/O0-I/O7 CONTROL BITS = 0 I/O0-I/O7 PULLUPS DISABLED SUPPLY CURRENT vs. SCL FREQUENCY DS4550 toc03 SCL FREQUENCY (kHz) SUPPLY CURRENT (µA) 300200100 04 0 0 VCC = SDA = TCK = 5.0V VCC = SDA = TCK = 2.7V SUPPLY CURRENT vs. TCK FREQUENCY DS4550 toc04 TCK FREQUENCY (kHz) SUPPLY CURRENT (µA) 1750150012501000750500250 02 0 0 0 VCC = 5.0V VCC = 2.7V SDA = SCL = VCC I/O OUTPUT VOLTAGE vs. SUPPLY VOLTAGE DS4550 toc05 SUPPLY VOLTAGE (V) I/O OUTPUT VOLTAGE (V) 54321 PULL-UPS ENABLED PULL-DOWNS DISABLED HIGH IMPEDANCE EEPROM RECALL AT VPOR Typical Operating Characteristics (VCC = +5.0V, TA = +25°C; TDI, TDO, TMS pins are no connects, unless otherwise noted.)
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Pin Description PIN NAME FUNCTION 1 I/O_0 Input/Output 0. Bidirectional I/O pin. 2 I/O_1 Input/Output 1. Bidirectional I/O pin. 3 I/O_2 Input/Output 2. Bidirectional I/O pin. 4 I/O_3 Input/Output 3. Bidirectional I/O pin. 5 I/O_4 Input/Output 4. Bidirectional I/O pin. 6A 0 I 2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. 7A 1 I 2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. 8 TCK JTAG Test Clock. This signal is used to shift data into TDI on the rising edge and out of TDO on the falling edge. 9 TMS JTAG Test Mode Select. This pin is sampled on the rising edge of TCK and used to place the TAP into the various defined JTAG states. This pin has an internal pullup resistor.
10 V CC Power Supply Voltage
11 SDA I 2C Serial Data Open-Drain Input/Output
12 SCL I 2C Serial Clock Input
13 TDI JTAG Test Data Input. Test instructions and data are clocked into this pin on the rising edge of TCK. This pin has an internal pullup resistor. 14 TDO JTAG Test Data Output. Test instructions and data are clocked out of this pin on the falling edge of TCK. If not used, this pin should be left open circuit.
15 A2 I
C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device. 16 I/O_5 Input/Output 5. Bidirectional I/O pin. 17 I/O_6 Input/Output 6. Bidirectional I/O pin. 18 I/O_7 Input/Output 7. Bidirectional I/O pin. 19 I/O_8 Input/Output 8. Bidirectional I/O pin.
20 GND Ground
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory I2C INTERFACE VCC SDA SCL TMS TDI TDO TCK GND DS4550 BSC BSC BSC BSC BSC EEPROM
64 BYTES
PULLUP ENABLE (F0h-F1h) I/O CONTROL (F2h-F3h) I/O STATUS (F8h-F9h) BOUNDARY SCAN CELL (BSC) JTAG CONTROL PORT VCC VCCI/O CELL (x9) RPU I/O_n [n = 0 TO 8] VCC RJPU RJPU BSC BSC BSC Block Diagram Detailed Description The DS4550 contains nine bidirectional, NV, input/out- put (I/O) pins, and a 64-byte EEPROM user memory. The I/O pins and user memory are accessible through either the I 2C compatible serial bus or the IEEE 1149.1 JTAG interface. Programmable NV I/O Pins Each programmable I/O pin consists of an input and an open-collector output with a selectable internal pullup resistor. To enable the pullups for each I/O pin, write to the Pullup Enable Registers (F0h and F1h). To pull the output low or place the pulldown transistor into a high- impedance state, write to the I/O Control Registers (F2h and F3h). To read the voltage levels present on the I/O pins, read the I/O Status Registers (F8h and F9h). To determine the status of the output register, read the I/O Control Registers and the Pullup Resistor Registers. The I/O Control Registers and the Pullup Enable Registers are all SRAM-shadowed EEPROM registers. It is possible to disable the EEPROM writes of the regis- ters using the SEE bit in the Configuration Register. This reduces the time required to write to the register and increases the amount of times the I/O pins can be adjusted before the EEPROM is worn out.
EEPROM, SRAM-shadowed EEPROM, and SRAM. Memory locations specified as EEPROM are NV. (default), the memory location acts like EEPROM. I/O Control for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the MSB. will float if no pullup/down is connected to the pin. I/O Status for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the MSB. the state of the I/O_0 to I/O_7 pins. effect. Read this register to determine the state of the I/O_8 pin. Table 1. DS4550 Memory Map
Figure 2. Address pins connected to GND result in a ‘0’ in the corresponding bit position in the slave address. tion is described in detail in a later section. the DS4550 are IEEE 1149.1 boundary-scan compliant. WRITE), which provide memory access. Figure 3. DS4550 JTAG Block Diagram ADDRESS PINS A0, A1, AND A2.
010 A2 A1 A0 R/W
Figure 2. DS4550 I2C Slave Address Byte
logic of the device operates normally. Register and test data registers remain idle. moves the controller to the Select-IR-Scan state. puts the controller in the Exit2-DR state. ing edge on TCK with TMS LOW enters the Shift-DR state. Figure 4. TAP Controller State Diagram
back into the Test-Logic-Reset state. edge of TCK, the controller enters the Shift-IR state. data one stage through the Instruction Shift Register. controller enters the Select-DR-Scan state. shifts the data one stage toward the serial output at TDO. test data register through TDI using the Shift-DR state. inputs into the Boundary Scan test data register. Table 2. Instruction Codes
CLAMP. All digital outputs of the device output data from the Boundary Scan parallel output while connect- ing the Bypass test data register between TDI and TDO. The outputs do not change during the CLAMP instruction. HIGHZ. All digital outputs of the device are placed in a high-impedance state. The Bypass test data register is connected between TDI and TDO. IDCODE. When the IDCODE instruction is latched into the parallel Instruction register, the Identification test data register is selected. The device identification code is loaded into the Identification test data register on the rising edge of TCK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially through TDO. During Test-Logic- Reset, the identification code is forced into the Instruction register. The ID code always has a 1 in the LSB position. The next 11 bits identify the manufactur- er’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the ver- sion. See the diagram below. ADDRESS. This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the DS4550. When the ADDRESS instruction is latched into the Instruction register, TDI connects to TDO through the 8-bit Memory Address test data regis- ter during the Shift-DR state. READ. This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the DS4550. When the READ instruction is latched into the Instruction register, TDI connects to TDO through the 8-bit Memory Read test data register dur- ing the Shift-DR state. WRITE. This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the DS4550. When the WRITE instruction is latched into the Instruction register, TDI connects to TDO through the 8-bit Memory Write test data register during the Shift-DR state. When EEPROM writes occur using the JTAG interface, the DS4550 will write the whole EEP- ROM memory page (8 bytes) even though only a single byte is modified. The unmodified bytes of the page are transparently rewritten to their current values. The DS4550’s EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specifica- tion shown is at the worst-case temperature. It is capa- ble of handling many more writes at room temperature. Test Data Registers IEEE 1149.1 requires a minimum of two test data regis- ters; the Bypass Register and the Boundary Scan Register. The optional Identification test data register has been included in the DS4550 design along with three DS4550 specific registers (Address, Read, Write) to support access to the EEPROM. Bypass Register. This is a one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instruc- tions. It provides a short path between TDI and TDO. Boundary Scan Register. This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells. It is 33 bits in length. See Table 3 for the cell bit locations and definitions. Identification Register. The Identification test data register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. Memory Address Register. This 8-bit register has a latched parallel output that holds the memory address location that is to be read from or written to. This regis- ter is selected during the ADDRESS instruction. Memory Read Register. This 8-bit load-only register will latch the 8-bit value from the memory location indi- cated by the address contained in the Address test data register during the Capture-DR state. The data can then be shifted out the TDO serial output by 8 ris- ing edges of TCK during the Shift-DR state. See Table 4 for a detailed example. Memory Write Register. This 8-bit output-only register will write its 8-bit value to the memory location indicated by the address contained in the Address test data reg- ister during the Update-DR state. The data is shifted into the Write test data register through the TDI input with 8 rising edges of TCK during the Shift-DR state immediately prior to the Update-DR state. See Table 5 for a detailed example. I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory MSB LSB Version (4 Bits) Device ID (16 Bits) Manufacturer ID (11 Bits) Fixed Value (1 Bit) 0000 0001000000000000 00010100001 1 32-Bit ID Code
Table 3. Boundary Scan Control Bits [33 Bits]
32 A2 input Input Observe Only
31 A1 input Input Observe Only
30 A0 input Input Observe Only
29 SCL input Input Observe Only
28 SDA input Input Observe Only
27 SDA output Output
26 IO8 pubout Output
25 IO8 pdbout Output
24 IO8 input Input Observe Only
23 IO7 pubout Output
22 IO7 pdbout Output
21 IO7 input Input Observe Only
20 IO6 pubout Output
19 IO6 pdbout Output
18 IO6 input Input Observe Only
17 IO5 pubout Output
16 IO5 pdbout Output
Table 4. EEPROM Read Cycle Shift-IR (4 x TCK) The 4-bit instruction is shifted in through TDI. Shift-DR (8 x TCK) The 8-bit address is shifted in through TDI. Update-DR The shifted 8-bit Address Register data is output latched. Shift-IR (4 x TCK) The 4-bit instruction is shifted in through TDI. Capture-DR The 8-bit EEPROM data is loaded into the EEPROM Read Register. Shift-DR (8 x TCK) The 8-bit data is shifted out through TDO.
15 IO5 input Input Observe Only
14 IO4 pubout Output
13 IO4 pdbout Output
12 IO4 input Input Observe Only
11 IO3 pubout Output
10 IO3 pdbout Output
9 IO3 input Input Observe Only
8 IO2 pubout Output
7 IO2 pdbout Output
6 IO2 input Input Observe Only
5 IO1 pubout Output
4 IO1 pdbout Output
3 IO1 input Input Observe Only
2 IO0 pubout Output
1 IO0 pdbout Output
0 IO0 input Input Observe Only
Table 5. EEPROM Write Cycle Shift-IR (4 x TCK) The 4-bit instruction is shifted in through TDI. Shift-DR (8 x TCK) The 8-bit address is shifted in through TDI. Update-DR The shifted 8-bit Address Register data is output latched. Shift-IR (4 x TCK) The 4-bit instruction is shifted in through TDI. Shift-DR (8 x TCK) The 8-bit data is shifted in through TDI. describe I2C data transfers. clock pulses, start and stop conditions. ates a low-power mode for slave devices. master to initiate a new data transfer with a slave. dition. See the timing diagram for applicable timing. shifted into the device during the rising edge of the SCL.
is always the 9th bit transmitted during a byte transfer. forms a NACK by transmitting a one during the 9th bit. the device is not receiving data. acknowledgement is read using the bit read definition. and the R/W bit in the least significant bit. Figure 5. I2C Timing Diagram
The DS4550’s slave address of the DS4550 is deter- mined by the state of the A0, A1, and A2 address pins as shown in Figure 2. Address pins connected to GND result in a ‘0’ in the corresponding bit position in the slave address. Conversely, address pins connected to V CC result in a ‘1’ in the corresponding bit positions. When the R/ W bit is 0 (such as in A0h), the master is indicating it will write data to the slave. If R/ W = 1, (A1h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS4550 assumes the master is communicating with another I device and ignores the communication until the next start condition is sent. Memory Address: During an I 2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte trans- mitted during a write operation following the slave address byte. I2C Communication Writing a Single Byte to a Slave: The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a stop condition. Remember the master must read the slave’s acknowledgement during all byte write operations. Writing Multiple Bytes to a Slave: To write multiple bytes to a slave, the master generates a start condition, writes the slave address byte (R/ W = 0), writes the memory address, writes up to 8 data bytes, and gener- ates a stop condition. The DS4550 is capable of writing up to 8 bytes (1 page or row) with a single I 2C write transaction. This is inter- nally controlled by an address counter that allows data to be written to consecutive addresses without transmit- ting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page. Attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. The first row begins at address 00h and subsequent rows begin at multiples of 8 there on (08h, 10h, 18h, 20h, etc). To prevent address wrapping from occurring, the mas- ter must send a stop condition at the end of the page, and then wait for the bus free or EEPROM write time to elapse. Then the master can generate a new start con- dition, write the slave address byte (R/ W = 0), and the first memory address of the next memory row before continuing to write data. Acknowledge Polling: Any time an EEPROM page is written, the DS4550 requires the EEPROM write time WR) after the stop condition to write the contents of the page to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS4550, which allows communication to continue as soon as the DS4550 is ready. The alternative to acknowledge polling is to wait for a maximum period of t WR to elapse before attempting to access the device. EEPROM Write Cycles: When EEPROM writes occur using the I 2C interface, the DS4550 writes the whole EEPROM memory page even if only a single byte on a page was modified. Writes that do not modify all 8 bytes on the page are valid and do not corrupt any other bytes on the same page. Because the whole page is written, even bytes on the page that were not modified during the transaction are still subject to a write cycle. The DS4550’s EEPROM write cycles are specified in the Nonvolatile Memory Characteristics table. The specification shown is at the worst-case tem- perature. It is capable of handling many more writes at room temperature. Reading a Single Byte from a Slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read oper- ation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a start condition, writes the slave address byte with R/ W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. However, since requiring the master to keep track of the memory address counter is imprac- tical, the following method should be used to perform reads from a specified memory location. Manipulating the Address Counter for Reads: A dummy write cycle can be used to force the address counter to a particular value. To do this, the master gen- erates a start condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/ W = 1), reads data with ACK or NACK as applicable, and generates a stop condition. I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory
start condition to specify the starting memory location. of the transfer and generate a stop condition. and GND pins of the IC to minimize lead inductance. Figure 6. I2C Communication Examples *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.
I2C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. is a registered trademark of Dallas Semiconductor Corporation.
Package Information
For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo. Chip Topology TRANSISTOR COUNT: 21,161 SUBSTRATE CONNECTED TO GROUND