DS3231SN+

DS3231 DALLAS | Alldatasheet

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Technical content

Features

♦ Accuracy ±2ppm from 0°C to +40°C ♦ Accuracy ±3.5ppm from -40°C to +85°C ♦ Battery Backup Input for Continuous Timekeeping ♦ Operating Temperature Ranges Commercial: 0°C to +70°C Industrial: -40°C to +85°C ♦ Low-Power Consumption ♦ Real-Time Clock Counts Seconds, Minutes, Hours, Day, Date, Month, and Year with Leap Year Compensation Valid Up to 2100 ♦ Two Time-of-Day Alarms ♦ Programmable Square-Wave Output ♦ Fast (400kHz) I 2C Interface ♦ 3.3V Operation ♦ Digital Temp Sensor Output: ±3°C Accuracy ♦ Register for Aging Trim ♦ RST Input/Output ♦ UL Recognized DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal Rev 2; 6/05 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

Ordering Information

PART TEMP RANGE PIN-PACKAGE TOP MARK DS3231S 0°C to +70°C 16 SO DS3231 DS3231SN -40°C to +85°C 16 SO DS3231N DS3231S+ 0°C to +70°C 16 SO DS3231+ DS3231SN+ -40°C to +85°C 16 SO DS3231N+ Pin Configuration appears at end of data sheet. Purchase of I 2C components from Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I 2C Standard Specification as defined by Philips. DS3231 VCC SCL RPU RPU = tR/CB RPU INT/SQW 32kHz VBAT PUSHBUTTON RESET SDA RST N.C. N.C. N.C. N.C. VCC VCC GND VCC CPU N.C. N.C. N.C. N.C. Typical Operating Circuit +Denotes lead-free

Extremely Accurate I2C-Integrated RTC/TCXO/Crystal ABSOLUTE MAXIMUM RATINGS RECOMMENDED DC OPERATING CONDITIONS (TA = TMIN to TMAX, unless otherwise noted.) (Notes 1, 2) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage Range on VCC, VBAT, 32kHz, SCL, SDA, RST, Operating Temperature Range Lead Temperature PC Board Layout, and Assembly section. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC 2.3 3.3 5.5 VSupply Voltage VBAT 2.3 3.0 5.5 V Logic 1 Input SDA, SCL V IH 0.7 x VCC VCC + 0.3 V Logic 0 Input SDA, SCL V IL -0.3 +0.3 x VCC V Pullup Voltage (SDA, SCL, 32kHz, INT/SQW) VPU VCC = 0V 5.5V V

ELECTRICAL CHARACTERISTICS

TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC = 3.63V 200Active Supply Current I CCA (Notes 3, 4) VCC = 5.5V 300 µA VCC = 3.63V 110 Standby Supply Current I CCS I2C bus inactive, 32kHz output on, SQW output off (Note 4) VCC = 5.5V 170 µA VCC = 3.63V 575Temperature Conversion Current ICCSCONV I2C bus inactive, 32kHz output on, SQW output off VCC = 5.5V 650 µA Power-Fail Voltage V PF 2.45 2.575 2.70 V Logic 0 Output, 32kHz, INT/SQW, SDA VOL IOL = 3mA 0.4 V Logic 0 Output, RST VOL IOL = 1mA 0.4 V Output Leakage Current 32kHz, INT/SQW, SDA ILO Output high impedance -1 0 +1 µA Input Leakage SCL ILI -1 +1 µA RST Pin I/O Leakage IOL RST high impedance (Note 5) -200 +10 µA VBAT Leakage Current (VCC Active) IBATLKG 25 100 nA

Extremely Accurate I2C-Integrated RTC/TCXO/Crystal ELECTRICAL CHARACTERISTICS (continued) TA = +25°C, unless otherwise noted.) (Notes 1, 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Frequency fOUT VCC = 3.3V or VBAT = 3.3V 32.768 kHz 0°C to +40°C ±2 Frequency Stability vs. Temperature (Commercial) ∆f/fOUT VCC = 3.3V or VBAT = 3.3V, aging offset = 00h >40°C to +70°C ±3.5 ppm -40°C to <0°C ±3.5 0°C to +40°C ±2 Frequency Stability vs. Temperature (Industrial) ∆f/fOUT VCC = 3.3V or VBAT = 3.3V, aging offset = 00h >40°C to +85°C ±3.5 ppm Frequency Stability vs. Voltage ∆f/V 1 ppm/V -40°C 0.7 +25°C 0.1 +70°C 0.4 Trim Register Frequency Sensitivity per LSB ∆f/LSB Specified at: +85°C 0.8 ppm Temperature Accuracy Temp V CC = 3.3V or VBAT = 3.3V -3 +3 °C First year ±1.0Crystal Aging ∆f/f0 After reflow, not production tested 0–10 years ±5.0 ppm (VCC = 0V, VBAT = 2.3V to 5.5V, TA = TMIN to TMAX, unless otherw.ise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VBAT = 3.63V 70Active Battery Current I BATA EOSC = 0, BBSQW = 0, SCL = 400kHz (Note 4) VBAT = 5.5V 150 µA VBAT = 3.63V 0.84 3.0 Timekeeping Battery Current I BATT EOSC = 0, BBSQW = 0, EN32kHz = 1, SCL = SDA = 0V or S C L = S D A = VBAT ( Note 4) VBAT = 5.5V 1.0 3.5 µA VBAT = 3.63V 575 Temperature Conversion Current IBATTC EOSC = 0, BBSQW = 0, SCL = SDA = 0V or SCL = SDA = VBAT VBAT = 5.5V 650 µA Data-Retention Current IBATTDR EOSC = 1, SCL = SDA = 0V, +25°C 100 nA

Extremely Accurate I2C-Integrated RTC/TCXO/Crystal AC ELECTRICAL CHARACTERISTICS (VCC = VCC(MIN) to VCC(MAX) or VBAT = VBAT(MIN) to VBAT(MAX), VBAT > VCC, TA = TMIN to TMAX, unless otherwise noted.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Fast mode 100 400SCL Clock Frequency f SCL Standard mode 0 100 kHz Fast mode 1.3Bus Free Time Between STOP and START Conditions tBUF Standard mode 4.7 µs Fast mode 0.6Hold Time (Repeated) START Condition (Note 6) tHD:STA Standard mode 4.0 µs Fast mode 1.3Low Period of SCL Clock t LOW Standard mode 4.7 µs Fast mode 0.6High Period of SCL Clock t HIGH Standard mode 4.0 µs Fast mode 0 0.9Data Hold Time (Notes 7, 8) tHD:DAT Standard mode 0 0.9 µs Fast mode 100Data Setup Time (Note 9) tSU:DAT Standard mode 250 ns Fast mode 0.6Start Setup Time t SU:STA Standard mode 4.7 µs Fast mode 300Rise Time of Both SDA and SCL Signals (Note 10) tR Standard mode 20 + 0.1CB 1000 ns Fast mode 300Fall Time of Both SDA and SCL Signals (Note 10) tF Standard mode 20 + 0.1CB 300 ns Fast mode 0.6Setup Time for STOP Condition tSU:STO Standard mode 4.7 µs Capacitive Load for Each Bus Line (Note 10) CB 400 pF Capacitance for SDA, SCL C I/O 10 pF Pulse Width of Spikes That Must Be Suppressed by the Input Filter tSP 30 ns Pushbutton Debounce PB DB 250 ms Reset Active Time t RST 250 ms Oscillator Stop Flag (OSF) Delay tOSF (Note 11) 100 ms Temperature Conversion Time t CONV 125 200 ms POWER-SWITCH CHARACTERISTICS (TA = TMIN to TMAX) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 µs VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR 0µ s Recovery at Power-Up t REC (Note 12) 250 300 ms

Extremely Accurate I2C-Integrated RTC/TCXO/Crystal Pushbutton Reset Timing tRSTPBDB RST Power-Switch Timing VCC tVCCF tVCCR tREC VPF(MAX) VPF VPF VPF(MIN) RST

Extremely Accurate I2C-Integrated RTC/TCXO/Crystal Data Transfer on I2C Serial Bus SDA SCL tHD:STA tLOW tHIGH tR tF tBUF tHD:DAT tSU:DAT REPEATED START tSU:STA tHD:STA tSU:STO tSP STOP START Note 1: Limits at -40°C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: ICCA—SCL clocking at max frequency = 400kHz. Note 4: Current is the averaged input current, which includes the temperature conversion current. Note 5: The RST pin has an internal 50kΩ (nominal) pullup resistor to VCC. Note 6: After this period, the first clock pulse is generated. Note 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 8: The maximum tHD:DAT needs only to be met if the device does not stretch the low period (tLOW) of the SCL signal. Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR(MAX) + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 10: CB—total capacitance of one bus line in pF. Note 11: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V ≤ VCC ≤ VCC(MAX) and 2.3V ≤ VBAT ≤ 3.4V. Note 12: This delay applies only if the oscillator is enabled and running. If the EOSC bit is a 1, the startup time of the oscillator is added to this delay.

Extremely Accurate I2C-Integrated RTC/TCXO/Crystal STANDBY SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3231 toc01 VCC (V) ICCS (µA) 5.04.03.0 100 150 2.0 RST ACTIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE DS3231 toc02 VBAT (V) IBAT (µA) 5.04.03.0 0.800 0.900 1.000 1.100 1.200 0.700 2.0 VCC = 0V SUPPLY CURRENT vs. TEMPERATURE DS3231 toc03 TEMPERATURE (°C) IBAT (µA) 0.700 0.800 0.900 1.000 0.600 -40.0 VBAT = 3.0V FREQUENCY DEVIATION vs. TEMPERATURE vs. AGING VALUE DS3231 toc04 CRYSTAL AGING REGISTER VALUE FREQUENCY DEVIATION (ppm) 96640 32-64 -32-96 -40 -30 -20 -10 -128 128 +85°C -40°C +70°C 0°C +40°C -40°C +85°C +25°C +40°C +25°C +70°C 0°C Typical Operating Characteristics (VCC = +3.3V, TA = +25°C, unless otherwise noted.)

Extremely Accurate I2C-Integrated RTC/TCXO/Crystal Block Diagram N N N RST VCC 32kHz INT/SQW CLOCK AND CALENDAR REGISTERS USER BUFFER (7 BYTES) I2C INTERFACE AND ADDRESS REGISTER DECODE POWER CONTROL VCC VBAT GND SCL SDA TEMPERATURE SENSOR CONTROL LOGIC/ DIVIDER PUSHBUTTON RESET; SQUARE-WAVE BUFFER; INT/SQW CONTROL CONTROL AND STATUS REGISTERS OSCILLATOR AND CAPACITOR ARRAY DS3231

Extremely Accurate I2C-Integrated RTC/TCXO/Crystal Pin Description PIN NAME FUNCTION 1 32kHz 32kHz Output. This open-drain pin requires an external pullup resistor. It may be left open if not used. 2V CC DC Power Pin for Primary Power Supply. This pin should be decoupled using a 0.1µF to 1.0µF capacitor. If not used, connect to ground.

3 INT/SQW

Active-Low Interrupt or Square-Wave Output. This open-drain pin requires an external pullup resistor. It may be left open if not used. This multifunction pin is determined by the state of the INTCN bit in the Control Register (0Eh). When INTCN is set to logic 0, this pin outputs a square wave and its frequency is determined by RS2 and RS1 bits. When INTCN is set to logic 1, then a match between the timekeeping registers and either of the alarm registers activates the INT/SQW pin (if the alarm is enabled). Because the INTCN bit is set to logic 1 when power is first applied, the pin defaults to an interrupt output with alarms disabled.

4 RST

Acti ve- Low Reset. Thi s p i n i s an op en- d r ai n i np ut/outp ut. It i nd i cates the status of V C C r el ati ve to the V P F sp eci fi cati on. As V C C fal l s b el ow V P F , the RS T p i n i s d r i ven l ow . W hen V C C exceed s V P F , for tR S T, the RS T p i n i s d r i ven hi g h i m p ed ance. The acti ve- l ow , op en- d r ai n outp ut i s com b i ned w i th a d eb ounced p ushb utton i np ut functi on. Thi s p i n can b e acti vated b y a p ushb utton r eset r eq uest. It has an i nter nal 50kΩ nom i nal val ue p ul l up r esi stor to V C C . N o exter nal p ul l up r esi stor s shoul d b e connected . If the cr ystal osci l l ator i s d i sab l ed , the star tup ti m e of the osci l l ator i s ad d ed to the tR S T d el ay. 5–12 N.C. No Connection. Must be connected to ground.

13 GND Ground

14 V BAT

Backup Power-Supply Input. This pin should be decoupled using a 0.1µF to 1.0µF low-leakage capacitor. If the I2C interface is inactive whenever the device is powered by the VB A T input, the decoupling capacitor is not required. If VB A T is not used, connect to ground. UL recognized to ensure against reverse charging when used with a lithium battery. Go to www.maxim-ic.com/qa/info/ul. 15 SDA Serial Data Input/Output. This pin is the data input/output for the I2C serial interface. This open-drain pin requires an external pullup resistor. 16 SCL Serial Clock Input. This pin is the clock input for the I2C serial interface and is used to synchronize data movement on the serial interface. Detailed Description The DS3231 is a serial RTC driven by a temperature- compensated 32kHz crystal oscillator. The TCXO pro- vides a stable and accurate reference clock, and maintains the RTC to within ±2 minutes per year accu- racy from -40°C to +85°C. The TCXO frequency output is available at the 32kHz pin. The RTC is a low-power clock/calendar with two programmable time-of-day alarms and a programmable square-wave output. The INT/SQW provides either an interrupt signal due to alarm conditions or a square-wave output. The clock/cal- endar provides seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. The internal registers are accessible though an I 2C bus interface. A temperature-compensated voltage reference and comparator circuit monitors the level of V CC to detect power failures and to automatically switch to the back- up supply when necessary. The RST pin provides an external pushbutton function and acts as an indicator of a power-fail event.

arately in the following sections. user-initiated temperature conversion is completed. and once every 64 seconds afterwards. but greater than VBAT, the DS3231 is powered by V CC. device is powered by VBAT. See Table 1. DS3231 debounces the switch by pulling the RST low. bypassed and RST immediately goes high. the 24-hour or 12-hour format with an AM/PM indicator. selection is controlled by the bit INTCN. main registers update during a read. Table 1. Power Control

low while SCL is high, generating a START condition. register is defined as the 12- or 24-hour mode select bit. gled when the years register overflows from 99 to 00. The day-of-week register increments at midnight. time and date entries result in undefined operation. ters in case the main registers update during a read. Figure 1. Timekeeing Registers Note: Unless otherwise specified, the registers’ state is not defined when power is first applied.

10 Hour

10 Hour Hour Alarm 2 Hours 1–12 + AM/PM

The DS3231 contains two time-of-day/date alarms. Alarm 1 can be set by writing to registers 07h to 0Ah. Alarm 2 can be set by writing to registers 0Bh to 0Dh. result in illogical operation. a match with day of the week. once-per-second update of the time and date registers. Table 2. Alarm Mask Bits

The DS3231 has two additional registers (control and status) that control the real-time clock, alarms, and square-wave output. Control Register (0Eh) Bit 7: Enable Oscillator ( EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the oscilla- tor is stopped when the DS3231 switches to V BAT. This bit is clear (logic 0) when power is first applied. When the DS3231 is powered by V CC, the oscillator is always on regardless of the status of the EOSC bit. Bit 6: Battery-Backed Square-Wave Enable (BBSQW). When set to logic 1 and the DS3231 is being powered by the V BAT pin, this bit enables the square-wave output when V CC is absent. When BBSQW is logic 0, the INT/SQW pin goes high imped- ance when V CC falls below the power-fail trip point. This bit is disabled (logic 0) when power is first applied. Bit 5: Convert Temperature (CONV). Setting this bit to 1 forces the temperature sensor to convert the temper- ature into digital code and execute the TCXO algorithm to update the capacitance array to the oscillator. This can only happen during the idle period. The status bit, BSY, prevents the bit from being set when BSY = 1. The user should check the status bit BSY before forcing the controller to start a new TCXO execution. A user-ini- tiated temperature conversion does not affect the inter- nal 64-second update cycle. A user-initiated temperature conversion does not affect the BSY bit for approximately 2ms. The CONV bit remains at a 1 from the time it is written until the conver- sion is finished, at which time both CONV and BSY go to 0. The CONV bit should be used when monitoring the status of a user-initiated conversion. Bits 4 and 3: Rate Select (RS2 and RS1). These bits control the frequency of the square-wave output when the square wave has been enabled. The following table shows the square-wave frequencies that can be select- ed with the RS bits. These bits are both set to logic 1 (8.192kHz) when power is first applied. Bit 2: Interrupt Control (INTCN). This bit controls the INT/SQW signal. When the INTCN bit is set to logic 0, a square wave is output on the INT/SQW pin. When the INTCN bit is set to logic 1, then a match between the timekeeping registers and either of the alarm registers activates the INT/SQW (if the alarm is also enabled). The corresponding alarm flag is always set regardless of the state of the INTCN bit. The INTCN bit is set to logic 1 when power is first applied. Bit 1: Alarm 2 Interrupt Enable (A2IE). When set to logic 1, this bit permits the alarm 2 flag (A2F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A2IE bit is set to logic 0 or INTCN is set to logic 0, the A2F bit does not initiate an interrupt signal. The A2IE bit is disabled (logic 0) when power is first applied. Bit 0: Alarm 1 Interrupt Enable (A1IE). When set to logic 1, this bit permits the alarm 1 flag (A1F) bit in the status register to assert INT/SQW (when INTCN = 1). When the A1IE bit is set to logic 0 or INTCN is set to logic 0, the A1F bit does not initiate the INT/SQW sig- nal. The A1IE bit is disabled (logic 0) when power is first applied. DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EOSC BBSQW CONV RS2 RS1 INTCN A2IE A1IE RS2 RS1 SQUARE-WAVE OUTPUT FREQUENCY 00 1Hz 01 1.024kHz 10 4.096kHz 11 8.192kHz SQUARE-WAVE OUTPUT FREQUENCY Control Register (0Eh)

DS3231 Status Register (0Fh) Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period and may be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: 1) The first time power is applied. 2) The voltages present on both V CC and V BAT are insufficient to support oscillation. 3) The EOSC bit is turned off in battery-backed mode. 4) External influences on the crystal (i.e., noise, leak- age, etc.). This bit remains at logic 1 until written to logic 0. Bit 3: Enable 32kHz Output (EN32kHz). This bit indi- cates the status of the 32kHz pin. When set to logic 1, the 32kHz pin is enabled and outputs a 32.768kHz square-wave signal. When set to logic 0, the 32kHz pin goes to a high-impedance state. The initial power-up state of this bit is logic 1, and a 32.768kHz square-wave signal appears at the 32kHz pin after a power source is applied to the DS3231 (if the oscillator is running). Bit 2: Busy (BSY). This bit indicates the device is busy executing TCXO functions. It goes to logic 1 when the conversion signal to the temperature sensor is asserted and then is cleared when the device is in the 1-minute idle state. Bit 1: Alarm 2 Flag (A2F). A logic 1 in the alarm 2 flag bit indicates that the time matched the alarm 2 regis- ters. If the A2IE bit is logic 1 and the INTCN bit is set to logic 1, the INT /SQW pin is also asserted. A2F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Bit 0: Alarm 1 Flag (A1F). A logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 regis- ters. If the A1IE bit is logic 1 and the INTCN bit is set to logic 1, the INT /SQW pin is also asserted. A1F is cleared when written to logic 0. This bit can only be written to logic 0. Attempting to write to logic 1 leaves the value unchanged. Crystal Aging The crystal aging offset register provides an 8-bit code to add to the codes in the capacitance array registers. The code is encoded in two’s complement. One LSB represents one small capacitor to be switched in or out of the capacitance array at the crystal pins. The offset register is added to the capacitance array register under the following conditions: during a normal temper- ature conversion, if the temperature changes from the previous conversion, or during a manual user conver- sion (setting the CONV bit). To see the effects of the aging register on the 32kHz output frequency immedi- ately, a manual conversion should be started after each aging register change. Positive aging values add capacitance to the array, slowing the oscillator frequency. Negative values remove capacitance from the array, increasing the oscillator frequency. The change in ppm per LSB is different at different tem- peratures. The frequency vs. temperature curve is shift- ed by the values used in this register. At +25°C, one LSB typically provides about 0.1ppm change in frequency. Extremely Accurate I2C-Integrated RTC/TCXO/Crystal BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Sign Data Data Data Data Data Data Data Crystal Aging Offset (10h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OSF 0 0 0 EN32kHz BSY A2F A1F Status Register (0Fh)

Temperature Registers (11h–12h) Temperature is represented as a 10-bit code with a res- olution of +0.25°C and is accessible at location 11h and 12h. The temperature is encoded in two’s comple- ment format. The upper 8 bits are at location 11h and the lower 2 bits are in the upper nibble at location 12h. Upon power reset, the registers are set to a default temperature of 0°C and the controller starts a tempera- ture conversion. New temperature readings are stored in this register. I2C Serial Data Bus The DS3231 supports a bidirectional I 2C bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiv- ing data is defined as a receiver. The device that con- trols the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and gener- ates the START and STOP conditions. The DS3231 operates as a slave on the I 2C bus. Connections to the bus are made through the SCL input and open-drain SDA I/O lines. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The DS3231 works in both modes. The following bus protocol has been defined (Figure 2):

• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low, while the clock line is high, defines a START condition. Stop data transfer: A change in the state of the data line from low to high, while the clock line is high, defines a STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and the STOP conditions is not limited, and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse, which is associ- ated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line high to enable the master to generate the STOP condition. DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Sign Data Data Data Data Data Data Data Temperature Register (Upper Byte) (11h) BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Data Data 0 00000 Temperature Register (Lower Byte) (12h)

acknowledge on SDA. After the DS3231 acknowl- edges the slave address + write bit, the master transmits a word address to the DS3231. This sets the register pointer on the DS3231, with the DS3231 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the DS3231 acknowledging each byte received. The register pointer increments after each data byte is trans- ferred. The master generates a STOP condition to terminate the data write. Slave transmitter mode (DS3231 read mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. Serial data is transmitted on SDA by the DS3231 while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by hardware after reception of the slave address and direction bit. The slave address byte is the first byte received after the master generates a START condition. The slave address byte contains the 7-bit DS3231 address, which is 1101000, fol- lowed by the direction bit (R/ W), which is 1 for a read. After receiving and decoding the slave address byte, the DS3231 outputs an acknowledge on SDA. The DS3231 then begins to transmit data starting with the register address pointed to by the register pointer. If the register pointer is not written to before the initiation of a read mode, the first address that is read is the last one stored in the register point- er. The DS3231 must receive a not acknowledge to end a read. Handling, PC Board Layout, and Assembly The DS3231 package contains a quartz tuning-fork crystal. Pick-and-place equipment can be used, but precautions should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning should be avoided to prevent damage to the crystal. Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal line. All N.C. (no connect) pins must be connect- ed to ground. Moisture-sensitive packages are shipped from the facto- ry dry packed. Handling instructions listed on the pack- age label must be followed to prevent damage during reflow. See IPC/JEDEC J-STD-020 standard for moisture- sensitive device (MSD) classifications and reflow pro- files. Exposure to reflow is limited to 2 times maximum. DS3231 Extremely Accurate I2C-Integrated RTC/TCXO/Crystal

Extremely Accurate I2C-Integrated RTC/TCXO/Crystal Chip Information TRANSISTOR COUNT: 33,000 SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS Thermal Information Theta-JA: +73°C/W Theta-JC: +23°C/W 32kHz SCL SDA V BAT GND N.C. N.C. N.C. N.C. TOP VIEW SO VCC INT/SQW N.C. RST N.C. N.C. N.C. DS3231S Pin Configuration

Extremely Accurate I2C-Integrated RTC/TCXO/Crystal Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circu it patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 19 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc. is a registered trademark of Dallas Semiconductor Corporation.

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo). 56-G4009-001.EPS