DS28E04-100

DS28E04-100 DALLAS | Alldatasheet

Document overview

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Technical content

1 of 36 REV: 102704 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS28E04-100 is a 4096-bit, 1-Wire ® EEPROM chip with seven address inputs. The address inputs are directly mapped into the 1-Wire 64-bit Device ID Number to easily enable the host system to identify the physical location or functional association of the DS28E04-100 in a multidevice 1-Wire network en- vironment. The 4096-bit EEPROM array is configured as 16 pages of 32 bytes with a 32 byte scratchpad to perform write operations. EEPROM memory pages can be individually write protected or put in EPROM- emulation mode, where bits can only be changed from a 1 to a 0 state. In addition to the memory, the DS28E04-100 has two general-purpose I/O ports that can be used for input or to generate level and/or pulse outputs. Activity registers also capture port activity for state change monitoring. The DS28E04- 100 communicates over the single-contact 1-Wire bus. The communication follows the standard Dallas Semiconductor 1-Wire protocol.

APPLICATIONS

/g183/g32Autoconfiguration of Modular Systems such as Central-Office Switches, Cellular Base Stations, Access Products, Optical Network Units, and PBXs /g183/g32Accessory/PCB Identification TYPICAL OPERATING CIRCUIT PX.Y µC RPUP VCC IO V CC POL GND A0 DS28E04 #1 IO V CC POL GND A0 DS28E04 #7RST1 RST0 LED

FEATURES

/g183/g324096 bits of EEPROM Memory Partitioned into

16 Pages of 256 Bits

/g183/g32Seven Address Inputs for Physical Location Configuration /g183/g32Two General-Purpose PIO Pins with Pulse- Generation Capability /g167/g32Individual Memory Pages can be Permanently Write-Protected or put in OTP EPROM- Emulation Mode (“Write to 0”) /g167/g32Communicates to Host with a Single Digital Signal at 15.3kbps or 111kbps Using 1-Wire Protocol /g167/g32Parasitic or VCC Powered /g167/g32Conditional Search Based on PIO Status or PIO Activity /g167/g32Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise /g167/g32Reads and Writes Over a Wide 2.8V to 5.25V Voltage Range from -40°C to +85°C /g167/g3216-Pin, 150-mil SO Package

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE DS28E04S-100 -40°C to +85°C 16 SO (150 mils) DS28E04S-100/T&R -40°C to +85°C Tape-and-Reel PIN CONFIGURATION IO GND N.C. GND N.C. V CC POL SO (150 mils) DS28E04-100 4096-Bit Addressable 1-Wire EEPROM with PIO www.maxim-ic.com Commands, Registers, and Modes are capitalized for clarity. 1-Wire is a registered trademark of Dallas Semiconductor Corp.

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 2 of 36 ABSOLUTE MAXIMUM RATINGS All Pins: Voltage to GND -0.5V, +6V All Pins: Sink Current 20mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -40°C to +85°C Soldering Temperature See IPC/JEDEC J-STD-020A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(VPUP = 2.8V to 5.25V, VCC = VPUP, floated or grounded, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Ground Current I GND (Notes 1, 2, 3) 20 mA Supply Current ICC VCC = VPUP (Note 3) 1 mA Standby Supply Current ICCS Device idle; A0 to A6 floating 11 µA PINS A0 TO A6 Input Low Voltage V ILA (Note 1) 0.30 V Input High Voltage V IHA VX = max(VPUP, VCC) (Note 1) VX - 0.3V V Input Load Current I LA Pin at GND (Note 4) -1.1 µA POL PIN Input Low Voltage V ILPOL (Note 1) 0.30 V Input High Voltage V IHPOL VX = max(VPUP, VCC) (Note 1) VX - 0.3V V Leakage Current I LKPOL Pin at 5.25V 1 µA PIO PINS Input Low Voltage V ILP (Note 1) 0.30 V Input High Voltage V IHP VX = max(VPUP, VCC) (Note 1) VX - 0.3V V Output Low Voltage at 4mA VOLP (Note 5) 0.4 V Leakage Current I LKP Pin at 5.25V 1 µA Minimum Sensed PIO Pulse tPWMIN (Note 6) 1 10 µs Output Pulse Duration t PULSE (Note 7) 250 1000 ms IO PIN GENERAL DATA 1-Wire Pullup Resistance RPUP (Notes 1, 8) 0.3 2.2 k/g87 Input Capacitance C IO (Notes 3, 9) 100 800 pF IO pin at VPUP, A0 to A6 floating, VCC at GND 0.05 11.00 Input Load Current I L IO pin at VPUP, A0 to A6 floating, VCC at VPUP 0.05 8.25 µA High-to-Low Switching Threshold VTL (Notes 3, 10, 11) 0.46 4.40 V Input Low Voltage V IL (Notes 1, 12) 0.3 V Input High Voltage V IH VX = max(VPUP, VCC) (Note 1) VX - 0.3V V Low-to-High Switching Threshold VTH (Notes 3, 10, 13) 1.0 4.9 V Switching Hysteresis V HY (Notes 3, 10, 14) 0.21 1.70 V Output Low Voltage V OL At 4mA Current Load (Note 5) 0.4 V Standard speed, RPUP = 2.2k/g87 5 Overdrive speed, RPUP = 2.2k/g87 2 Recovery Time (Notes 1, 15) tREC Overdrive speed, directly prior to reset pulse; RPUP = 2.2k/g87 5 µs Standard speed (Note 16) 0.5 5.0 Rising-Edge Hold-Off Time (Note 3) tREH Overdrive speed Not applicable (0) µs Standard speed 65 Time Slot Duration (Note 1) tSLOT Overdrive speed 9 µs

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 3 of 36 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN, 1-Wire RESET, PRESENCE DETECT CYCLE Standard speed, VPUP > 4.5V 480 640 Standard speed (Note 17) 504 640 Overdrive speed, VPUP > 4.5V 48 80 Reset Low Time (Note 1) t RSTL Overdrive speed (Note 17) 53 80 µs Standard speed 15 60 Presence-Detect High Time tPDH Overdrive speed (Note 17) 2 7 µs Standard speed, VPUP > 4.5V 1.10 3.75 Standard speed 1.1 7.0 Presence-Detect Fall Time (Notes 3, 18) tFPD Overdrive speed 0 1.1 µs Standard speed 60 240 Overdrive speed, VPUP > 4.5V 8 24 Presence-Detect Low Time tPDL Overdrive speed (Note 17) 8 26 µs Standard speed, VPUP > 4.5V 64 75 Standard speed 67 75 Presence-Detect Sample Time (Note 1) tMSP Overdrive speed 8.1 10 µs IO PIN, 1-Wire WRITE Standard speed 60 120 Write-0 Low Time (Note 1) t W0L Overdrive speed (Note 17) 7 16 µs Standard speed 5 15 - /g101 Write-1 Low Time (Notes 1, 19) tW1L Overdrive speed 1 2 - /g101 µs IO PIN, 1-Wire READ Standard speed 5 15 - /g100 Read Low Time (Notes 1, 20) tRL Overdrive speed 1 2 - /g100 µs Standard speed tRL + /g100 15 Read Sample Time (Notes 1, 20) tMSR Overdrive speed tRL + /g100 2 µs EEPROM Programming Current I PROG (Note 21) 1 mA Programming Time t PROG (Note 22) 10 ms At +25°C 200k Write/Erase Cycles (Endurance) NCY At +85°C (worst case) 50k /g190 Data Retention t DR At +85°C (worst case) 10 years Note 1: System requirement. Note 2: Maximum instantaneous pulldown current through all pins combined. Note 3: Guaranteed by design, simulation only. Not production tested. Note 4: This load current is caused by the internal weak pullup, which asserts a logical 1 to address pins that are not connected. The logical state of the address pins must not change during the execution of ROM function commands during those time slots in which these bits are relevant. Note 5: The I-V characteristic is linear for voltages less than 1V. Note 6: Width of the narrowest pulse that trips the activity latch. Back to back pulses that are active for < t PWMIN (max) and that have an intermediate inactive time < tPWMIN (max) are not guaranteed to be filtered. Note 7: The Pulse function requires that VCC power is available; otherwise the command will not be executed. Note 8: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Note 9: Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2k/g87 resistor is used to pull up the data line, 2.5µs after VPUP has been applied the parasite capacitance will not affect normal communications. Note 10: VTL, VTH, and VHY are a function of the internal supply voltage. Note 11: Voltage below which, during a falling edge on IO, a logic 0 is detected. Note 12: The voltage on IO needs to be less than or equal to VILMAX whenever the master drives the line low. Note 13: Voltage above which, during a rising edge on IO, a logic 1 is detected. Note 14: After VTH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'. Note 15: Applies to a single DS28E04-100 without VCC supply, attached to a 1-Wire line. Note 16: The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached. Note 17: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table. Note 18: Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is 80% of VPUP and the time at which the voltage is 20% of VPUP. Note 19: /g101 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. Note 20: /g100 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold of the bus master.

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 4 of 36 Note 21: Current drawn during the EEPROM programming interval. If the device does not get VCC power, the pullup circuit on IO during the programming interval should be such that the voltage at IO is greater than or equal to VPUP(min). If VPUP in the system is close to Vpup(min) then a low-impedance bypass of RPUP that can be activated during programming may need to be added. Note 22: The tPROG interval begins tREHmax after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from IPROG to IL or ICCS, respectively. LEGACY VALUES DS28E04-100 VALUES PARAMETER STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED MIN MAX MIN MAX MIN MAX MIN MAX tSLOT (incl. tREC) 61µs (undef) 7µs (undef) 65µs 1) (undef) 9µs (undef) tRSTL 480µs (undef) 48µs 80µs 504µs 640µs 53µs 80µs tPDH 15µs 60µs 2µs 6µs 15µs 60µs 2µs 7µs tPDL 60µs 240µs 8µs 24µs 60µs 240µs 8µs 26µs tW0L 60µs 120µs 6µs 16µs 60µs 120µs 7µs 16µs 1) Intentional change, longer recovery time requirement due to modified 1-Wire front end. PIN DESCRIPTION PIN NAME FUNCTION 1 A3 Address bit input (place value = 8), with weak pullup. 2 A2 Address bit input (place value = 4), with weak pullup. 3 A1 Address bit input (place value = 2), with weak pullup. 4 A0 Least significant address bit input (place value = 1), with weak pullup. 5, 12 GND Ground Reference 6, 11 N.C. Not Connected 7 V CC Optional power supply for the chip; float or ground if V CC power is not available. 8 POL Power-up polarity (logical state) for P0 and P1; pin has a weak pulldown. 9 P0 Remote-controlled I/O pin, open drain with weak pulldown. 10 P1 Remote-controlled I/O pin, open drain with weak pulldown. 13 A6 Address bit input (place value = 64), with weak pullup. 14 A5 Address bit input (place value = 32), with weak pullup. 15 A4 Address bit input (place value = 16), with weak pullup. 16 IO 1-Wire Bus Interface. Open drain, requires external pullup resistor. DETAILED DESCRIPTION The DS28E04-100 combines 4096 bits of EEPROM, a 16-byte control page, two general-purpose PIO pins, seven external address pins, and a fully featured 1-Wire interface in a single chip. PIO outputs are configured as open- drain and provide an on-resistance of 100 /g87 max. A robust PIO channel-access communication protocol ensures that PIO output-setting changes occur error-free. The DS28E04-100 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory or the control page. Data is first written to the scratchpad from which it can be read back. The copy scratchpad command transfers the data to its final memory location. Each DS28E04-100 has a device ID number that is 64 bits long. The user can define seven bits of this number through address pins. The remaining 57 bits are factory-lasered into the chip. The device ID number guarantees unique identification and is used to address the device in a multidrop 1-Wire network environment, where multiple devices reside on a common 1-Wire bus and operate independently of each other. The DS28E04- 100 also supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity. The DS28E04-100 has an optional V CC supply connection. When an external supply is absent, device power is supplied parasitically from the 1-Wire bus. When an external supply is present, PIO states are maintained in the absence of the 1-Wire bus power source. Applications of the DS28E04-100 include autoconfiguration and state monitoring of modular systems such as central-office switches, cellular base stations, access products, optical network units, and PBXs, and accessory/PC board identification.

Figure 14. After a ROM function command is successfully executed, the memory/control functions become these commands is described in Figure 9. All data is read and written least significant bit first. Figure 1. Block Diagram

16 Pages of

32 Bytes Each

Figure 4. 1-Wire CRC Generator set to 55h or AAh. Any other setting leaves them open for unrestricted write access. through the Read Scratchpad command prior to copying into the main array. refreshed, i.e., reprogrammed with the current data. the execution of the copy scratchpad command with a target address of a copy-protected memory page.

Figure 5. Memory Map Address locations 0000h to 021Fh are nonvolatile. Address locations 0220h to 0225 are volatile. 55h: Write Protected; AAh: EPROM mode. page 0, address 0201h with page 1, etc. write-protect the address nor activate any function.

is cleared to 00h by a power-on reset, or by successful execution of the Reset Activity Latches command. the various signals that determine whether the device responds to a conditional search is illustrated in Figure 7. selected channels must match the corresponding polarity. Figure 7. CONDITIONAL SEARCH LOGIC command. To include a PIO channel, the bits in this register that correspond to those channels need to be set to 1. and cannot be changed to 1. This register is cleared to 00h by a power-on reset.

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 11 of 36 Conditional Search Channel Polarity Selection Register ADDR b7 b6 b5 b4 b3 b2 b1 b0 0224h 0 0 0 0 0 0 SP1 SP0 The data in this register specifies the polarity of each selected PIO channel for the device to respond to the conditional search command. This register can only be written through the Write Registers command. Within a PIO channel, the data source may be either the channel's input pin or the channel's activity latch, as specified by the PLS bit in the Control/Status register at address 0225h. This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7. Bits 2 to 7 have no function; they always read 0 and cannot be changed to 1. This register is cleared to 00h at power-up. Control/Status Register ADDR b7 b6 b5 b4 b3 b2 b1 b0 0225h VCCP POL 0 0 PORL 0 CT PLS The data in this register reports status information and further configures the device for conditional search. This register can only be written through the Write Registers command. This register is read/write. The power-up state of the PORL bit is "1". CT and PLS power up as "0". The functional assignments of the individual bits are explained in the table below. Bits 2, 4, and 5 have no function; they always read 0 and cannot be set to 1. Control/Status Register Details BIT DESCRIPTION BIT(S) DEFINITION PLS: Pin or Activity Latch Select b0 Selects either the PIO pins or the PIO activity latches as input for the conditional search. 0: pin selected (default) 1: activity latch selected CT: Conditional Search Logical Term b1 Specifies whether the data of two channels needs to be OR’ed or AND’ed to meet the qualifying condition for the device to respond to a conditional search. If only a single channel is selected in the channel selection mask (0223h) this bit is a don't care. 0: bitwise OR (default) 1: bitwise AND PORL: Power-On Reset Latch b3 Specifies whether the device has performed a power-on reset. This bit can only be cleared to 0 by writing to the Control/Status Register. As long as this bit is 1 the device will always respond to a Conditional Search ROM sequence. POL: PIO Default Polarity (Read-Only) b6 Reports the state of the POL pin. The state of the POL pin specifies whether the PIO pins P0 and P1 power up high or low. The polarity of a pulse generated at a PIO pin is the opposite of the pin's power- up state. 0: PIO powers up 0 1: PIO powers up 1 VCCP: VCC Power Status (Read-Only) b7 For VCC-powered operation, the VCC pin needs to be connected to a voltage source equal to VPUP. 0: V CC power not available 1: V CC-powered operation

Figure 8. Address Registers should obtain the contents of these registers by reading the scratchpad.

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 13 of 36 MEMORY/CONTROL FUNCTION COMMANDS The Memory/Control Function Flow Chart (Figure 9) describes the protocols necessary to access the memory and the PIO pins of the DS28E04-100. Examples on how to use these functions are included at the end of this document. The communication between master and DS28E04-100 takes place either at standard speed (default, OD = 0) or at Overdrive peed (OD = 1). If not explicitly set into the Overdrive Mode, the DS28E04-100 powers up in standard speed. WRITE SCRATCHPAD COMMAND [0Fh] The Write Scratchpad command applies to the data memory, and the writeable addresses in the register page. After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset of T4:T0. The ending offset (E4:E0) is the byte offset at which the master stops writing data. Only full data bytes are accepted. If the last data byte is incomplete, its content will be ignored and the partial byte flag PF will be set. When executing the Write Scratchpad command, the CRC generator inside the DS 28E04-100 (Figure 18) calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. This CRC is generated using the CRC16 poly nomial by first clearing the CRC generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target Addresses (TA1 and TA2) as supplied by the master, and all the data bytes. The master may end the Write Scratchpad command at any time. However, if the end of the scratchpad is reached (E4:E0 = 11111b), the master can send 16 read-time slots and receive the CRC generated by the DS28E04-100. If a Write Scratchpad is attempted to a write-protected location, the scratchpad is loaded with the data already in memory, rather than the data transmitted. Similarly, if the target address page is in EPROM mode, the scratchpad is loaded with the bitwise logical AND of the transmitted data and data already in memory. READ SCRATCHPAD COMMAND [AAh] The Read Scratchpad command allows verification of the target address and the scratchpad data. After issuing the command code, the master begins reading. The first two bytes are the target address. The next byte is the ending offset/data status byte (E/S) followed by the scratchpad data, which may be different from what the master originally sent. This is of particular importance if the target address is within the register page or a page in either Write-Protected or EPROM modes. See the Write Scratchpad description for details. The master should read E4:E0-T4:T0+1 bytes, after which it receives the inverted CRC16, based on data as it was sent by the DS28E04- 100. If the master continues reading after the CRC, all data will be logic 1s. COPY SCRATCHPAD [55h] The Copy Scratchpad command is used to copy data from the scratchpad to the data memory and the writable sections of the Register Page. After issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern, which should have been obtained by an immediately preceding Read Scratchpad command. This 3-byte pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the target address is valid, the PF flag is not set, and the target memory is not copy- protected, the AA (Authorization Accepted) flag is set and the copy begins. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset will be copied to memory, starting at the target address. Anywhere from 1 to 32 bytes can be copied with this command. The device’s internal data transfer takes 10ms maximum during which the voltage on the 1-Wire bus must not fall below 2.8V. After waiting 10ms, the master may issue read time slots to receive AAh confirmation bytes until the master issues a reset pulse. If the PF flag is set or the target memory is copy-protected, the copy will not begin and the AA flag will not be set.

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 14 of 36 Figure 9-1. Memory/Control Function Flow Chart 0Fh Write Scratch- pad ? Bus Master TX EEPROM Array Target Address TA1 (T7:T0), TA2 (T15:T8) Y N To Figure 9 2nd Part From Figure 9 2nd Part Bus Master TX Memory Function Command To ROM Functions Flow Chart (Figure 14) From ROM Functions Flow Chart (Figure 14) Master TX Reset ? Master TX Data Byte To Scratchpad Offset N Y DS28E04 sets Scratchpad Offset = (T4:T0), Clears PF, AA Scrpad. Offset = 11111b? DS28E04 TX CRC16 of Command, Address, Data Bytes as they were sent by the bus master DS28E04 Increments Scratchpad Offset Master TX Reset ? Y N Bus Master RX “1”s N Partial Byte ? PF = 1 Y N Y Applies only if the page is not write protected or in EPROM mode. If write- protected, then the DS28E04 copies the data byte from the target address into the scratchpad. If in EPROM mode, then the DS28E04 stores the bitwise logical AND of the transmitted byte and the data byte from the targeted address into the scratchpad.

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 15 of 36 Figure 9-2. Memory/Control Function Flow Chart (continued) AAh Read Scratch- Pad ? DS28E04 sets Scratchpad Offset = (T4:T0) Bus Master RX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte Bus Master RX Data Byte from Scratchpad Offset Bus Master RX CRC16 of Command, Address, E/S Byte, Data Bytes as sent by the DS28E04 Y Bus Master RX “1”s Master TX Reset ? Y N Master TX Reset ? DS28E04 Increments Scratchpad Offset Scrpad. Offset = E4:E0 ? Y Y N N N From Figure 9 1st Part To Figure 9 1st Part To Figure 9 3rd Part From Figure 9 3rd Part See note in Write Scratchpad flow chart for additional details.

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 16 of 36 Figure 9-3. Memory/Control Function Flow Chart (continued) From Figure 9 2nd Part To Figure 9 2nd Part To Figure 9 4th Part From Figure 9 4th Part * 1-Wire idle high 10ms for power 55h Copy Scratch- Pad ? Bus Master TX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte Y N Bus Master RX “1”s Master TX Reset ? Y N YAuth. Code Match ? N N Copy- Protected ? Y DS28E04 copies Scratch- pad Data to Address AA = 1 DS28E04 TX “0” Master TX Reset ? Master TX Reset ? Y N DS28E04 TX “1” N Y Applicable to all R/W memory locations. YT15:T0 < 0220h ? N PF = 0 ? Y N

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 17 of 36 Figure 9-4. Memory/Control Function Flow Chart (continued) F0h Read Memory ? Y N Bus Master TX TA1 (T7:T0), TA2 (T15:T8) From Figure 9 3rd Part To Figure 9 3rd Part N Bus Master RX “1”s Master TX Reset ? Y Address < 226h ? Y N DS28E04 sets Memory Address = (T15:T0) DS28E04 Increments Address Counter Bus Master RX “1”s N Address < 225h? Master TX Reset ? Y N Y Master TX Reset? Bus Master RX Data Byte from Memory Address Y N CCh Write Register? Bus Master TX TA1 (T7:T0), TA2 (T15:T8) Y N Master TX Reset? Bus Master TX Data Byte DS28E04 increments Address Counter DS28E04 Copies Data to Register Y Address < 226h? N N Y To Figure 9 5th Part From Figure 9 5th Part Y 223h /g163 Address /g163 225h? N

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 18 of 36 Figure 9-5. Memory/Control Function Flow Chart (continued) From Figure 9 4th Part To Figure 9 4th Part To Figure 9 6th Part From Figure 9 6th Part F5h PIO Access Read? DS28E04 Samples PIO Pin Status PIO Sample Counter = 0 Y N Sample Count = 31? Y NMaster TX Reset? Bus Master RX PIO Pin Status DS28E04 Increments PIO Sample Counter DS28E04 Samples PIO Pin Status Bus Master RX PIO Pin Status PIO Sample Counter = 0 DS28E04 Samples PIO Pin Status Bus Master RX CRC16 of Command and 32 Bytes of PIO Pin Status (1st Pass) CRC16 of 32 Bytes of PIO Pin Status (Subsequent Passes) Y N 5Ah PIO Access Write? Bus Master TX new PIO Output Data Byte Bus Master TX inverted new PIO Output Data Byte Transmission OK? DS28E04 Updates PIO Output Latch Bus Master RX Confirmation AAh DS28E04 Samples PIO Pin Status Bus Master RX PIO Pin Status Y N Master TX Reset? N Y Bus Master RX “1”s Y N Master TX Reset? Note 1) See the command description for the exact timing of the PIO pin sampling and updating. N Y 1) 1)

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 19 of 36 Figure 9-6. Memory/Control Function Flow Chart (continued) From Figure 9 5th Part To Figure 9 5th Part A5h PIO Access Pulse? Y NC3h Reset Activity Latches? DS28E04 Clears all PIO Activity Latches Bus Master RX Confirmation AAh Y N Master TX Reset? Bus Master TX PIO Selection Mask Bus Master TX inverted PIO Selection Mask Transmission OK? DS28E04 Initiates PIO Pulse Bus Master RX Confirmation AAh DS28E04 Samples PIO Pin Status Bus Master RX PIO Pin Status Y N Master TX Reset? N Y Bus Master RX “1”s Y N Master TX Reset? Note 1) See the command description for the exact timing of the PIO pin sampling and updating. 1) N Y N Bus Master RX “1”s Master TX Reset ? Y Bus Master RX “1”s

affected by a Read Memory command. register data, it is important to verify correct writing by reading the registers using the Read Memory command. at any time with a 1-Wire Reset. The state of the POL pin does not affect this command. rising edge of the MS bit of the previous byte, as shown in Figure 10. The value of "x" is approximately 0.2µs. Figure 10. PIO Access Read Timing Diagram being the write confirmation byte (AAh).

does not affect this command. After the command code, the master transmits a byte that determines the new state of the PIO output transistors. the data the master can either continue writing more data to the PIO or issue a 1-Wire reset to end the command. Figure 11. PIO Access Write Timing Diagram must repeat the selection mask in its inverted form. Only if the transmission was error-free does the pulse occur.

Figure 13. Hardware Configuration the 1-Wire Signaling section. produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC. Note that there will also be a CRC mismatch if one or more of the external address inputs are connected to GND. for a reset pulse. This command can be used with a single or multiple devices on the bus.

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 24 of 36 SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their device ID numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the device ID numbers of all slave devices. For each bit of the device ID number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its device ID number bit. On the second slot, each slave device participating in the search outputs the complemented value of its device ID number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the romcode tree. After one complete pass, the bus master knows the device ID number of a single device. Additional passes identify the device ID numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. Note: Since the DS28E04-100 lasered ROM CRC is calculated assuming the address inputs are all logic 1, then any address inputs that are connected to GND are not validated. It is recommended to do a double search when building a list of devices on the 1-Wire line. CONDITIONAL SEARCH [ECh] The Conditional Search ROM command operates similarly to the Search ROM command except that only those devices, which fulfill certain conditions (CSR = 1), will participate in the search. This function provides an efficient means for the bus master to identify devices on a multidrop system that have to signal an important event. After each pass of the conditional search that successfully determined the 64-bit ROM code for a specific device on the multidrop bus, that particular device can be individually accessed as if a Match ROM had been issued, since all other devices will have dropped out of the search process and will be waiting for a reset pulse. The DS28E04-100 responds to the conditional search if the CSR signal is active. See the description of the registers at addresses 0223h to 0225h and Figure 7 for more details. SKIP ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a Read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). RESUME [A5h] To maximize the data throughput in a multidrop environment, the Resume function is available. This function checks the status of the RC bit and, if it is set, directly transfers control to the Memory functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume Command function. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the Resume Command function. OVERDRIVE SKIP ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the DS28E04-100 in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus, this command sets all Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Overdrive-supporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result).

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 25 of 36 Figure 14-1. ROM Functions Flow Chart From Figure 14 2nd Part To Memory Functions Flow Chart (Figure 9) Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 RC = 1 DS28E04 TX Family Code (1 Byte) Bit 0 Match? Y N Bit 1 Match? Y N Bit 63 Match? Y N DS28E04 TX Bit 0 DS28E04 TX Bit 0 Master TX Bit 0 DS28E04 TX Bit 1 DS28E04 TX Bit 1 Master TX Bit 1 DS28E04 TX Bit 63 DS28E04 TX Bit 63 Master TX Bit 63 RC = 1 Bit 0 Match? Y N Bit 1 Match? Y N Bit 63 Match? Y N To Figure 14 2nd Part RC = 0RC = 0 RC = 0 RC = 0 YY Y Y NF0h Search ROM Command? N55h Match ROM Command? N ECh Cond. Search Command? N 33h Read ROM Command? To Figure 14 2nd Part From Memory Functions Flow Chart (Figure 9) Bus Master TX ROM Function Command DS28E04 TX Presence Pulse OD Reset Pulse? N Y OD = 0 Bus Master TX Reset Pulse From Figure 14, 2nd Part CSR = 1? Y N DS28E04 TX Bit 0 DS28E04 TX Bit 0 Master TX Bit 0 DS28E04 TX Bit 1 DS28E04 TX Bit 1 Master TX Bit 1 DS28E04 TX Bit 63 DS28E04 TX Bit 63 Master TX Bit 63 RC = 1 Bit 0 Match? Y N Bit 1 Match? Y N Bit 63 Match? Y NDS28E04 TX CRC Byte DS28E04 TX Ext. Address (7 bits) DS28E04 TX Serial Number (40 bits) DS28E04 TX "0" (1 bit) The CRC is hard-coded assuming all external address bits are 1's.

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 26 of 36 Figure 14-2. ROM Functions Flow Chart (continued) From Figure 14 1st Part From Figure 14 1st Part To Figure 14, 1st Part RC = 1 ? N Y RC = 0 ; OD = 1 Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 RC = 1 Bit 0 Match? Y N Bit 1 Match? Y N Bit 63 Match? Y N Y N69h Overdrive Match ROM? RC = 0 ; OD = 1 Master TX Reset ? Y N Master TX Reset ? N Y Y N3Ch Overdrive Skip ROM? Y NA5h Resume Command? RC = 0 Y N CCh Skip ROM Command? To Figure 14 1st Part

the definitions of the write and read time slots. during a write time slot and how long data is valid during a read time slot. Figure 16. Read/Write Timing Diagram

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 29 of 36 Master-to-Slave For a write-one time slot, the voltage on the data line must have crossed the V TH threshold before the write-one low time t W1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the V TH threshold until the write-zero low time t W0LMIN is expired. For the most reliable communication, the voltage on the data line should not exceed V ILMAX during the entire t W0L or tW1L window. After the V TH threshold has been crossed, the DS28E04-100 needs a recovery time tREC before it is ready for the next time slot. Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below V TL until the read low time t RL is expired. During the t RL window, when responding with a 0, the DS28E04-100 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the DS28E04-100 does not hold the data line low at all, and the voltage starts rising as soon as t RL is over. The sum of t RL + /g100 (rise time) on one side and the internal timing generator of the DS28E04-100 on the other side define the master sampling window (t MSRMIN to tMSRMAX) in which the master must perform a read from the data line. For the most reliable communication, t RL should be as short as permissible, and the master should read close to but no later than t MSRMAX. After reading from the data line, the master must wait until t SLOT is expired. This guarantees sufficient recovery time t REC for the DS28E04-100 to get ready for the next time slot. Note that t REC specified herein applies only to a single DS28E04-100 attached to a 1-Wire line. For multidevice configurations, t REC needs to be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an interface that performs active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire line drivers can be used. IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS) In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up, or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a search ROM command coming to a dead end or cause a device-specific function command to abort. For better performance in network applications, the DS28E04-100 uses a new 1-Wire front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave device itself. The 1-Wire front end of the DS28E04-100 differs from traditional slave devices in four characteristics. 1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line impedance than a digitally switched transistor, converting the high-frequency ringing known from traditional devices into a smoother low-bandwidth transition. The slew-rate control is specified by the parameter t FPD, which has different values for standard and Overdrive speed. 2) There is additional lowpass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed. 3) There is a hysteresis at the low-to-high switching threshold V TH. If a negative glitch crosses VTH but does not go below VTH - VHY, it will not be recognized (Figure 17, Case A). The hysteresis is effective at any 1-Wire speed. 4) There is a time window specified by the rising edge hold-off time t REH during which glitches are ignored, even if they extend below V TH - V HY threshold (Figure 17, Case B, t GL < t REH). Deep voltage droops or glitches that appear late after crossing the V TH threshold and extend beyond the t REH window cannot be filtered out and are taken as the beginning of a new time slot (Figure 17, Case C, tGL /g179 tREH). Only devices that have the parameters t FPD, V HY, and t REH specified in their electrical characteristics use the improved 1-Wire front end.

Figure 17. Noise Suppression Scheme the data, and decides whether to continue with an operation or to reread the portion of the data with the CRC error. master. The DS28E04-100 transmits this CRC only if E4:E0 = 11111b, i.e., the end of the scratchpad is hit. then reads the scratchpad, one will receive a CRC of the command, TA1, TA2, and the data byte. in 32 bytes read from the PIO pins. For more information on generating CRC values, refer to Application Note 27.

Figure 18. CRC-16 Hardware Description and Polynomial RST 1-Wire Reset Pulse generated by master. PD 1-Wire Presence Pulse generated by slave. Select Command and data to satisfy the ROM function protocol. WS Command "Write Scratchpad". RS Command "Read Scratchpad". CPS Command "Copy Scratchpad". WREG Command "Write Register". PIOR Command "PIO Access Read". PIOW Command "PIO Access Write". PIOP Command "PIO Access Pulse". RAL Command "Reset Activity Latches". TA-E/S Target address TA1, TA2 with E/S byte. <data to EOM> Transfer of as many data bytes as are needed to reach the end of the memory. <register data> Data for registers at addresses 223h to 225h, 1 to 3 bytes, depending on start address. CRC16\\ Transfer of an inverted CRC16. FF loop Indefinite loop where the master reads FF bytes. AA loop Indefinite loop where the master reads AA bytes. Programming Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time.

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 32 of 36 COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—COLOR CODES Master to slave Slave to master Programming WRITE SCRATCHPAD (CANNOT FAIL) RST PD Select WS TA <32 – T4:T0 bytes> CRC16\\ FF loop READ SCRATCHPAD (CANNOT FAIL) RST PD Select RS TA-E/S <E4:E0 - T4:T0 +1 bytes> CRC16\\ FF loop COPY SCRATCHPAD 1-Wire POWERED (SUCCESS) RST PD Select CPS TA-E/S wait tPROGMAX AA loop COPY SCRATCHPAD (INVALID ADDRESS OR PF = 1 OR COPY PROTECTED) RST PD Select CPS TA-E/S FF loop READ MEMORY (SUCCESS) RST PD Select RM TA <data to EOM> FF loop READ MEMORY (INVALID ADDRESS) RST PD Select RM TA FF loop WRITE REGISTER (SUCCESS) RST PD Select WREG TA <register data> FF loop WRITE REGISTER (INVALID ADDRESS) RST PD Select WREG TA FF loop

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 33 of 36 PIO ACCESS READ (CANNOT FAIL) RST PD Select PIOR <32 bytes PIO data> CRC16\\ PIO ACCESS WRITE (SUCCESS) RST PD Select PIOW <new PIO data> <inverted new PIO data> <AAh> <PIO data> PIO ACCESS WRITE (INVALID DATA BYTE) RST PD Select PIOW <new PIO data> <invalid data byte> FF loop PIO ACCESS PULSE (SUCCESS) RST PD Select PIOP <selection mask> <inverted selection mask> <AAh> <PIO data> PIO ACCESS PULSE (INVALID SELECTION MASK) RST PD Select PIOP <selection mask> <invalid selection mask> FF loop RESET ACTIVITY LATCHES (CANNOT FAIL) RST PD Select RAL AA loop Loop until master sends Reset Pulse Loop until master sends Reset Pulse

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 34 of 36 MEMORY FUNCTION EXAMPLE Write 5 bytes to memory page 1, starting at address 0021h. Read the entire memory and the PIO-related registers. With only a single DS28E04-100 connected to the bus master, the communication looks like this: MASTER MODE DATA (LSB FIRST) COMMENTS TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX 0Fh Issue “Write Scratchpad” command TX 21h TA1, beginning offset = 21h TX 00h TA2, address = 00 21h TX <5 data bytes> Write 5 bytes of data to scratchpad TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX AAh Issue “Read Scratchpad” command RX 21h Read TA1, beginning offset = 21h RX 00h Read TA2, address = 00 21h RX 05h Read E/S, ending offset = 00101b, AA, PF = 0 RX <5 data bytes> Read scratchpad data and verify RX <2 bytes CRC16\\> Read CRC to check for data integrity TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX 55h Issue “Copy Scratchpad” command TX 21h TA1 TX 00h TA2 (AUTHORIZATION CODE) TX 05h E/S ---- <1-Wire idle high> Wait 10ms for the copy function to complete RX AAh Read copy status, AAh = success TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX F0h Issue “Read Memory” command TX 00h TA1, beginning offset = 00h TX 00h TA2, address = 00 00h RX <550 data bytes> Read the entire memory TX (Reset) Reset pulse RX (Presence) Presence pulse

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 35 of 36 PIO ACCESS READ EXAMPLE Read the state of the PIOs 32 times. With only a single DS28E04-100 connected to the bus master, the communication looks like this: MASTER MODE DATA (LSB FIRST) COMMENTS TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX F5h Issue “PIO Access Read” command RX <32 data bytes> Read 32 PIO samples RX <2 bytes CRC16\\> Read CRC to check for data integrity TX (Reset) Reset pulse RX (Presence) Presence pulse The inverted CRC16 is transmitted after 32 bytes of PIO data. PIO ACCESS WRITE EXAMPLE Set both PIOs to 0 and then to 1. Both PIOs are pulled high to V CC or VPUP by a resistor. With only a single DS28E04-100 connected to the bus master, the communication looks like this: MASTER MODE DATA (LSB FIRST) COMMENTS TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX 5Ah Issue “PIO Access Write” command TX FCh Write new PIO output state TX 03h Write inverted new PIO output state RX AAh Read confirmation byte RX FCh Read new PIO pin status TX FFh Write new PIO output state TX 00h Write inverted new PIO output state RX AAh Read confirmation byte RX FFh Read new PIO pin status TX (Reset) Reset pulse RX (Presence) Presence pulse

DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 36 of 36 PIO ACCESS PULSE EXAMPLE Generate a pulse on PIO1. Both PIOs are pulled high to V CC by a resistor. POL = 1. VCC power is present. With only a single DS28E04-100 connected to the bus master, the communication looks like this: MASTER MODE DATA (LSB FIRST) COMMENTS TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX A5h Issue “PIO Access Pulse” command TX FEh Write PIO selection mask TX 01h Write inverted PIO selection mask RX AAh Read confirmation byte RX 1111110Xb Read PIO pin status 1) TX (Reset) Reset pulse RX (Presence) Presence pulse 1) The "X" indicates the state of PIO0, which is not defined in this example.

PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)