DS28E01-100 DALLAS | Alldatasheet
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1 of 16 REV: 071207 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. DS28E01-100 1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine Abridged Data Sheet GENERAL DESCRIPTION The DS28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations. All memory pages can be write protected, and one page can be put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 state. Each DS28E01- 100 has its own guaranteed unique 64-bit ROM registration number that is factory lasered into the chip. The DS28E01-100 communicates over the single-contact 1-Wire® bus. The communication follows the standard Dallas Semiconductor 1-Wire protocol with the registration number acting as node address in the case of a multi-device 1-Wire network.
APPLICATIONS
Printer Cartridge Configuration and Monitoring Medical Sensor Authentication and Calibration System Intellectual Property Protection TYPICAL OPERATING CIRCUIT µC IO DS28E01 GND RPUP VCC
FEATURES
1024 bits of EEPROM memory partitioned into four pages of 256 bits On-chip 512-bit SHA-1 engine to compute 160-bit Message Authentication Codes (MAC) and to generate secrets Write access requires knowledge of the secret and the capability of computing and transmitting a 160-bit MAC as authorization User-programmable page write-protection for page 0, page 3 or all four pages together User-programmable OTP EPROM emulation mode for page 1 ("write to 0") Communicates to host with a single digital signal at 15.3k bits or 125k bits per second using 1-Wire protocol Switchpoint Hysteresis an d Filtering to Optimize Performance in the Presence of Noise Reads and writes over a wide voltage range of 2.8V to 5.25V from -40°C to +85°C 6-lead TSOC, 2-lead SFN or solder-bumped chipscale surface mount package
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS28E01P-100 -40°C to 85°C 6-pin TSOC DS28E01P-100/T&R -40°C to 85°C TSOC Tape & reel DS28E01P-100+ -40°C to 85°C 6-pin TSOC DS28E01P-100+T&R -40°C to 85°C TSOC Tape & reel DS28E01G-100+T&R -40°C to 85°C 2-pin SFN Tape & reel + Indicates lead-free compliance. Ordering Information and Pin Configuration continued at the end of the data sheet. Request full data sheet at: www.maxim-ic.com/fullds/DS28E01-100 PIN CONFIGURATION TSOC 150 mil Top view 6 NC 5 NC 4 NC GND 1 IO 2 NC 3 www.maxim-ic.com Commands, Registers, and Modes are capitalized for clarity. 1-Wire is a registered trademark of Dallas Semiconductor Corp.
Abridged Data Sheet DS28E01-100 2 of 16 ABSOLUTE MAXIMUM RATINGS IO Voltage to GND -0.5V, +6V IO Sink Current 20mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDEC J-STD-020A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(TA = -40°C to +85°C; see Note 1.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS IO PIN GENERAL DATA 1-Wire Pullup Voltage VPUP (Note 2) 2.8 5.25 V 1-Wire Pullup Resistance RPUP (Notes 2, 3) 0.3 2.2 kΩ Input Capacitance CIO (Notes 4, 5) 1000 pF Input Load Current IL IO pin at VPUP 0.05 6.7 µA High-to-Low Switching Threshold VTL (Notes 5, 6, 7) 0.46 VPUP - 1.8V V Input Low Voltage VIL (Notes 2, 8) 0.5 V Low-to-High Switching Threshold VTH (Notes 5, 6, 9) 1.0 VPUP - 1.1V V Switching Hysteresis VHY (Notes 5, 6, 10) 0.21 1.70 V Output Low Voltage VOL At 4mA Current Load (Note 11) 0.4 V Standard speed, RPUP = 2.2kΩ 5 Overdrive speed, RPUP = 2.2kΩ 2 Recovery Time (Notes 2, 12) tREC Overdrive speed, directly prior to reset pulse; RPUP = 2.2kΩ 5 µs Standard speed 0.5 5.0 Rising-Edge Hold-off Time (Notes 5, 13) tREH Overdrive speed Not applicable (0) µs Standard speed 65 Time slot Duration (Note 2, 14) tSLOT Overdrive speed 8 µs IO PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE Standard speed 480 640 Reset Low Time (Note 2) tRSTL Overdrive speed 48 80 µs Standard speed 15 60 Presence Detect High Time tPDH Overdrive speed 2 6 µs Standard speed 60 240 Presence Detect Low Time tPDL Overdrive speed 8 24 µs Standard speed 60 75 Presence Detect Sample Time (Notes 2, 15) tMSP Overdrive speed 6 10 µs IO PIN, 1-Wire WRITE Standard speed 60 120 Overdrive speed, VPUP > 4.5V 5 15.5 Write-0 Low Time (Notes 2, 16, 17) tW0L Overdrive speed 6 15.5 µs Standard speed 1 15 Write-1 Low Time (Notes 2, 17) tW1L Overdrive speed 1 2 µs IO PIN, 1-Wire READ Standard speed 5 15 - δ Read Low Time (Notes 2, 18) tRL Overdrive speed 1 2 - δ µs Standard speed tRL + δ 15 Read Sample Time (Notes 2, 18) tMSR Overdrive speed tRL + δ 2 µs
Abridged Data Sheet DS28E01-100 3 of 16 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS EEPROM Programming Current IPROG (Notes 5, 19) 0.8 mA Programming Time tPROG (Note 20) 10 ms At 25°C 200k Write/Erase Cycles (En- durance) (Notes 21, 22) NCY At 85°C (worst case) 50k --- Data Retention (Notes 23, 24, 25) tDR At 85°C (worst case) 40 years SHA-1 ENGINE SHA Computation Current (Notes 5, 19) ILCSHA See full version of data sheet. mA SHA Computation Time (Note 5) tCSHA See full version of data sheet. ms Note 1: Specifications at TA = -40°C are guaranteed by design only and not production-tested. Note 2: System requirement. Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Note 4: Maximum value represents the internal parasite capacitance when VPUP is first applied. If RPUP = 2.2kΩ, 2.5µs after VPUP has been applied the parasite capacitance will not affect normal communications. Note 5: Guaranteed by design, characterization and/or simulation only. Not production tested. Note 6: VTL, VTH, and VHY are a function of the internal supply voltage, which is itself a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Note 7: Voltage below which, during a falling edge on IO, a logic 0 is detected. Note 8: The voltage on IO needs to be less than or equal to VIL(MAX) at all times the master is driving IO to a logic-0 level. Note 9: Voltage above which, during a rising edge on IO, a logic 1 is detected. Note 10: After VTH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'. Note 11: The I-V characteristic is linear for voltages less than 1V. Note 12: Applies to a single device attached to a 1-Wire line. Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge. Note 14: Defines maximum possible bit rate. Equal to tW0L(min) + tREC(min). Note 15: Interval after tRSTL during which a bus master is guaranteed to sample a logic-0 on IO if there is a DS28E01-100 present. Minimum limit is tPDH(max); maximum limit is tPDH(min) + tPDL(min). Note 16: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below. Note 17: ε in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1Lmax + tF - ε and tW0Lmax + tF - ε respectively. Note 18: δ in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLmax + tF. Note 19: Current drawn from IO during EEPROM programming or SHA-1 computation interval. Note 20: See full version of data sheet. Note 21: Write-cycle endurance is degraded as TA increases. Note 22: Not 100% production-tested; guaranteed by reliability monitor sampling. Note 23: Data retention is degraded as TA increases. Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing. Note 25: EEPROM writes may become non-functional after the data retention time is exceeded. Long-time storage at elevated temperatures is not recommended; the device may lose its write-capability after 10 years at 125°C or 40 years at 85°C.
Abridged Data Sheet DS28E01-100 4 of 16 LEGACY VALUES DS28E01-100 VALUES PARAMETER STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED MIN MAX MIN MAX MIN MAX MIN MAX tRSTL 480µs (undef.) 48µs 80µs 480µs 640µs 48µs 80µs tPDH 15µs 60µs 2µs 6µs 15µs 60µs 2µs 6µs tPDL 60µs 240µs 8µs 24µs 60µs 240µs 8µs 24µs tW0L 60µs 120µs 6µs 16µs 60µs 120µs 6µs 15.5µs 1) Intentional change, longer recovery time requirement due to modified 1-Wire front end. PIN DESCRIPTION NAME FUNCTION IO 1-Wire bus interface. Open drain, requires external pull-up resistor. GND Ground reference NC Not connected
DESCRIPTION
The DS28E01-100 combines 1024 bits of EEPROM organize d as four 256-bit pages, a 64-bit secret, a register page, a 512-bit SHA-1 engine, a 64-bit ROM registration numb er in a single chip. Data is transferred serially through the 1-Wire protocol, which requires only a single data lead and a ground return. The DS28E01-100 has an additional memory area called the scratchpad that acts as a buffer when writing to the memory, the register page, or when installing a new secret. Data is first written to the scratchpad from where it can be read back. After the data has been verified, a copy scratchpad command transfers t he data to its final memory location, provided that the DS28E01-100 receives a matching 160-bit MAC. The comp utation of the MAC involves the secret and additional data stored in the DS28E01-100 including the device’s registration number. Only a new secret can be loaded without providing a MAC. The SHA-1 engine is also ac tivated to compute 160-bit MACs when performing an authenticated read of a memory page and when computing a new secret, instead of loading it. The DS28E01-100 understands a unique command "Refresh Scratchpad." Proper use of a refresh sequence after a copy scratchpad operation reduces the num ber of weak bit failures if the device is used in a touch environment (see the Writing with Verification section). The refresh sequence also provides a means to restore functionality in a device with bits in a weak state. The device's 64-bit ROM registration number guarantees uni que identification and is used to address the device in a multidrop 1-Wire network environment, where multip le devices reside on a common 1-Wire bus and operate independently of each other. Applications of the DS28E01-100 include printer cartridge configuration and monitoring, medical sensor authentication and calibration, and system intellectual property protection. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS28E01-100. The DS28E01-100 has six main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3) four 256-bit pages of EEPROM, 4) regi ster page, 5) 64-bit secrets memory, and 6) a 512-bit SH A-1 (Secure Hash Algorithm) engine. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the seven ROM function commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume Communication, 6) Overdrive-Skip ROM, or 7) Overdrive-Match ROM. Upon completion of an overdrive ROM command byte executed at standard speed, the device enters overdrive mode where all subsequent commu- nication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 10. After a ROM function command is successfully executed, the memory and SHA-1 functions become accessible and the master can provide any one of the 9 available func tion commands. The function protocols are described in Figure 8 *. All data is read and written least significant bit first. * For Figure 8 see the full version of the data sheet.
Figure 1. Block Diagram
4 Pages of
Figure 2. Hierarchical Structure for 1-Wire Protocol
scratchpad clears this flag. Figure 7. Address Registers and uses the modified address as the target address. The ma ster should always send eight complete data bytes. compare the CRC to the value it has calculated itself in order to determi ne if the communication was successful. memory. Alternatively, the load first secret or compute next secret command can be issued to change the secret. See the descriptions of these commands for more information.
Abridged Data Sheet DS28E01-100 9 of 16 TRANSACTION SEQUENCE The protocol for accessing the DS28E01-100 through the 1-Wire port is as follows: Initialization ROM Function Command Memory/SHA Function Command Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initializat ion sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presen ce pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS28E01-100 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can is sue one of the seven ROM function commands that the DS28E01-100 supports. All ROM function commands are 8 bits long. A list of these commands follows (refer to the flow chart in Figure 10). READ ROM [33h] This command allows the bus master to read the DS28E 01-100’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC. MATCH ROM [55h] The Match ROM command, followed by a 64-bit ROM seq uence, allows the bus master to address a specific DS28E01-100 on a multidrop bus. On ly the DS28E01-100 that exactly ma tches the 64-bit ROM sequence, including the external address, responds to the follow ing Memory/Control Function command. All other slaves wait for a reset pulse. This command can be used with a single or multiple devices on the bus. SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the nu mber of devices on the 1-Wire bus or their device ID numbers. By taking advantage of the wir ed-AND property of the bus, the master can use a process of elimination to identify the device ID numbers of all slav e devices. For each bit of the device ID number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its device ID number bit. On the second slot, each slave device participating in the search outputs the complemented value of its device ID number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are ze ro, the master knows that slave devices exist with both states of the bit. By choosing which state to write, t he bus master branches in the ROM code tree. After one complete pass, the bus master knows the device ID num ber of a single device. Additional passes identify the device ID numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. SKIP ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result).
Abridged Data Sheet DS28E01-100 10 of 16 Figure 10-1. ROM Functions Flow Chart From Figure 10 2nd Part To Memory Functions Flow Chart (Figure 8) Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 Bit 63 Match ? RC = 0 DS28E01 TX Bit 0 DS28E01 TX Bit 0 Master TX Bit 0 DS28E01 TX Bit 1 DS28E01 TX Bit 1 Master TX Bit 1 DS28E01 TX Bit 63 DS28E01 TX Bit 63 Master TX Bit 63 RC = 1 Bit 1 Match ? Bit 0 Match ? Y N Y N Y NBit 63 Match ? RC = 0 RC = 1 Bit 1 Match ? Bit 0 Match ? Y N Y N Y N RC = 0 DS28E01 TX CRC Byte DS28E01 TX Serial Number (6 Bytes) DS28E01 TX Family Code (1 Byte) RC = 0 To Figure 10 2nd Part NF0h Search ROM Command ? N55h Match ROM Command ? N CCh Skip ROM Command ? YY Y Y N 33h Read ROM Command ? To Figure 10 2nd Part From Memory Functions Flow Chart (Figure 8) Bus Master TX ROM Function Command DS28E01 TX Presence Pulse OD Reset Pulse ? N Y OD = 0 Bus Master TX Reset Pulse From Figure 10, 2nd Part
Abridged Data Sheet DS28E01-100 11 of 16 Figure 10-2. ROM Functions Flow Chart (continued) To Figure 10 1st Part From Figure 10 1st Part From Figure 10 1st Part To Figure 10, 1st Part Y NA5h Resume Command ? RC = 1 ? Y N3Ch Overdrive Skip ROM ? RC = 0 ; OD = 1 Master TX Reset ? Y N N Y Master TX Reset ? N Y Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 Bit 63 Match ? RC = 0 ; OD = 1 RC = 1 Bit 1 Match ? Y N Y N Bit 0 Match ? Y N Y N 69h Overdrive Match ROM ?
Abridged Data Sheet DS28E01-100 12 of 16 RESUME [A5h] To maximize the data throughput in a multidrop environm ent, the Resume function is available. This function checks the status of the RC bit and, if it is set, directly transfers control to the Memory functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive Match ROM command. Once the RC bit is se t, the device can repeatedly be accessed through the Resume Command function. Accessing another device on t he bus clears the RC bit, preventing two or more devices from simultaneously responding to the Resume Command function. OVERDRIVE SKIP ROM [3Ch] On a single-drop bus this command can save time by a llowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the norm al Skip ROM command, the Overdrive Skip ROM sets the DS28E01-100 in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus, this command sets all Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Over drive-supporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence . This speeds up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). OVERDRIVE MATCH ROM [69h] The Overdrive Match ROM command followed by a 64-bit RO M sequence transmitted at Overdrive Speed allows the bus master to address a specific DS28E01-100 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS28E01-100 that exactly matches the 64-bit ROM sequence responds to the subsequent Memory or SHA Function command. Slaves already in Overdrive mode from a previous Overdrive Skip or successful Overdrive Match command remain in Overdrive mode. All overdrive-capable slaves return to standard speed at the next Reset Pulse of minimum 480µs duration. The Over drive Match ROM command can be used with a single or multiple devices on the bus. 1-Wire SIGNALING The DS28E01-100 requires strict protocols to ensure data integrity. The prot ocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Pres ence Pulse, Write-Zero, Write-One, and Read-Data. Except for the Presence pulse, the bus master initia tes all falling edges. The DS28E01-100 can communicate at two different speeds, standard speed, and Overdrive Speed. If not explicitly set into the Overdrive mode, the DS28E01-100 communicates at standard speed. While in Overdrive Mode the fast timing applies to all waveforms. To get from idle to active, the voltage on the 1-Wire line needs to fall from V PUP below the threshold V TL. To get from active to idle, the voltage needs to rise from V ILMAX past the threshold V TH. The time it takes for the voltage to make this rise is seen in Figure 11 as ' ε' and its duration depends on the pullup resistor (R PUP) used and the capacitance of the 1-Wire network attached. The voltage V ILMAX is relevant for the DS28E01-100 when determining a logical level, not triggering any events. Figure 11 shows the initialization sequence required to begin any communication with the DS28E01-100. A Reset Pulse followed by a Presence Pulse indicates the DS28E01-1 00 is ready to receive data, given the correct ROM and Memory/Control Function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for t RSTL + t F to compensate for the edge. A t RSTL duration of 480µs or longer exits the Overdrive Mode, returning the device to standard speed. If the DS28E01-100 is in Overdrive Mode and tRSTL is no longer than 80µs, the device remains in Overdrive Mode. If the device is in Overdrive Mode and t RSTL is between 80µs and 480µs, the device will reset, but the communication speed is undetermined.
Figure 12. Read/Write Timing Diagram (continued) the DS28E01-100 needs a recovery time tREC before it is ready for the next time slot. data line low; its internal timing generator determines wh en this pulldown ends and the voltage starts rising again. define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read from the data line.
applications, the DS28E01-100 uses a new 1-Wire front end, which makes it less sensitive to noise. The 1-Wire front end of the DS28E01-100 differs from traditional slave devices in three characteristics. 1) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed. below VTH - VHY, it will not be recognized (Figure 13, Case A). The hysteresis is effective at any 1-Wire speed. taken as the beginning of a new time slot (Figure 13, Case C, tGL ≥ tREH). Figure 13. Noise Suppression Scheme the CRC value from the first 56 bits of the 64-bit ROM and compare it to the value read from the DS28E01-100. This 8-bit CRC is received in the true form (noninverted) when reading the ROM. details (including Figure 14) see the full version of the data sheet.
Abridged Data Sheet DS28E01-100 16 of 16 PIN CONFIGURATION (CONTINUED) PIN CONFIGURATION (CONTINUED) µCSP*, Top View with Laser Mark, Contacts Not Visible. A2 = IO A3 = GND All Other Bumps: NC yywwrr = Date/Revision ###xx = Lot Number See 21-0093, pkg. code B9-8, for package outline. * Refer to package reliability report for important guidelines on qualified usage conditions. A B C 1 2 3 A1 Mark DS28E01 yywwrr ###xx Bottom View Side View SFN, approx. 6 x 6 x 0.9 mm 1 2 SFN, pinout: Package Outline Drawing 56-00SFN-000 The SFN Package is qualified for electromechanical contact applications only, not for soldering. (CONTINUED) SFN PACKAGE ORIENTATION ON TAPE-AND-REEL PART TEMP RANGE PIN-PACKAGE DS28E01X-100 -40 to 85°C µCSP, 10k pcs, Tape-and-Reel DS28E01X-100-S -40 to 85°C µCSP, 2.5k pcs, Tape-and-Reel User Direction of Feed Leads face up in orientation shown above. Contact factory for availability of the µCSP.
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)