DS2755 DALLAS | Alldatasheet
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Technical content
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
FEATURES
Snapshot Mode Allows Instantaneous Power Measurement Accurate Current Measurement for Coulomb Counting (Current Accumulation) - 2% ±4 μV over ±64mV Input Range - 2% ±200 μA over ±3.2A Range Using a 20mΩ Sense Resistor Current Measurement - 9-Bit Bidirectional Snapshot Measurement - 12-Bit Bidirectional Average Updated Every 88ms - 15-Bit Bidirectional Average Updated Every 2.8s Voltage Measurement - 9-Bit Snapshot Measurement - 10-Bit Measurement Updated Every 4ms Temperature Measurement - 10-Bit Measurement, 0.125 °C Resolution Using Integrated Sensor Host Alerted When Accumulated Current or Temperature Exceeds User-Selectable Limits 96 Bytes of Lockable EEPROM 8 Bytes of General-Purpose SRAM Dallas 1-Wire ® Interface with Unique 64-Bit Device Address with Standard 16kbps or Overdrive 142kbps Timing 3mm Dimension of 8-Pin TSSOP Package Allows Mounting on Side of Thin Prismatic Li+ and Li+/Polymer Cells
APPLICATIONS
Portable Consumer Products PIN CONFIGURATION
DESCRIPTION
The DS2755 high-precision battery fuel gauge is a data-acquisition and information-storage device tailored for cost-sensitive and space-constrained 1- cell Li+/polymer battery-pack applications. The DS2755 provides the key hardware components required to accurately estimate remaining capacity by integrating low-power, precision measurements of temperature, voltage, current, and current accumulation, as well as nonvolatile (NV) data storage, into the small footprint of a 3.0mm x 4.4mm 8-pin TSSOP package. Through its 1-Wire interface, the DS2755 gives the host system read/write access to status and control registers, instrumentatio n registers, and general- purpose data storage. Each device has a unique factory-programmed 64-bit net address that allows it to be individually addressed by the host system, supporting multibattery operation.
ORDERING INFORMATION
PART MARKING TEMP RANGE DESCRIPTION DS2755E+ 2755 -20°C to +70°C 8-Pin TSSOP, Lead Free DS2755E+T&R 2755 -20°C to +70°C DS2755E+ on Tape-and-Reel www.maxim-ic.com 1-Wire is a registered trademark of Dallas Semiconductor. DS2755 High-Accuracy Battery Fuel Gauge with Snapshot VIN DQ SNS IS2 PIO V SS 2 VDD 4 IS1 DS2755E 8-Pin TSSOP Package
select either the DQ pin or PIO pin as the interrupt signal. switches, vibration motors, speakers, and LEDs, or the I/O pin can be configured as an interrupt output. security for unchanging battery data. SRAM provides inexpensive storage for temporary data. Figure 1. APPLICATION EXAMPLE
1 Cell Li+
DS2755: High-Accuracy Battery Fuel Gauge with Snapshot 3 of 20 ABSOLUTE MAXIMUM RATINGS* Voltage on PIO Pin, Relative to VSS -0.3V to +12V Voltage on All Other Pins, Relative to VSS -0.3V to +6V Continuous Sink Current, DQ, PIO 12mA Operating Temperature Range -40°C to +85°C Storage Temperature Range -55°C to +125°C Soldering Temperature See J-STD-020 Specification * This is a stress rating only and functional operation of the device at these or any ot her conditions above those indicated in t he operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (2.5V ≤ VDD ≤ 5.5V, TA = -20°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V DD (Note 1) 2.5 5.5 V Data Pin DQ (Note 1) -0.3 +5.5 V VIN Pin V IN (Note 1) -0.3 +5.5 V DC ELECTRICAL CHARACTERISTICS (2.5V ≤ VDD ≤ 5.5V, TA = -20°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DQ = VDD, EEC bit = 0, 0°C to +50°C, 2.5V < VDD < 4.2V 75 100 μA Active Current I ACTIVE DQ = VDD, EEC bit = 0 110 Sleep-Mode Current I SLEEP DQ = 0V (Note 3) 1 2 μA Current Measurement Input Range VIS1-IS2 (Note 2) ±64 mV Current Register Offset Error IOERR (Note 5) ±7.813 μV Current Gain Error I GERR (Note 2, 6) ±1 %I reading
24 Hour Accumulated
VIS1-IS2 = 0, OBEN set, (Note 2, 7, 4) -200 -100 0 µVhr Current Sampling Frequency fSAMP 1456 Hz IS1-VSS, IS2-SNS Filter Resistors RKS +25°C 10 kΩ Input Resistance: VIN R IN VIN = VDD 5 MΩ Voltage Offset Error V OERR (Note 8) ±5 mV Voltage Gain Error V GERR ±2 %V reading Temperature Error T ERR (Note 9) ±3 °C Input Logic High: DQ, PIO VIH (Note 1) 1.5 V Input Logic Low: DQ, PIO VIL (Note 1) 0.4 V Output Logic Low: DQ, PIO VOL IOL = 4mA (Note 1) 0.4 V DQ Pulldown Current I PD 1 μA DQ Capacitance C DQ 60 pF DQ Low-to-Sleep Time t SLEEP 2.1 s Undervoltage Detect V UV (Note 1) 2.45 2.5 2.55 V Undervoltage Delay t UVD 90 100 110 ms 0°C to +50°C (Note 10) ±1 ±2 Internal Timebase Accuracy tERR
DS2755: High-Accuracy Battery Fuel Gauge with Snapshot 4 of 20 ELECTRICAL CHARACTERISTICS—1-WIRE INTERFACE (2.5V ≤ VDD ≤ 5.5V, TA = -20°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Snapshot Trigger 0 t SWL 1 16 μs Snapshot Delay t SDLY 80 100 120 μs STANDARD TIMING Time Slot t SLOT 60 120 μs Recovery Time t REC 1 μs Write-0 Low Time t LOW0 60 119 μs Write-1 Low Time t LOW1 1 15 μs Read Data Valid t RDV 15 μs Reset Time High t RSTH 480 μs Reset Time Low t RSTL 480 960 μs Presence-Detect High t PDH 15 60 μs Presence-Detect Low t PDL 60 240 μs Interrupt Time Low t IL 480 1920 μs OVERDRIVE TIMING Time Slot t SLOT 6 16 μs Recovery Time t REC 1 μs Write-0 Low Time t LOW0 6 16 μs Write-1 Low Time t LOW1 1 2 μs Read Data Valid t RDV 2 μs Reset Time High t RSTH 48 μs Reset Time Low t RSTL 48 80 μs Presence-Detect High t PDH 2 6 μs Presence-Detect Low t PDL 8 24 μs Interrupt Time Low t IL 48 192 μs EEPROM RELIABILITY SPECIFICATION (2.5V ≤ VDD ≤ 5.5V, TA = -20°C to +70°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Copy to EEPROM Time t EEC 2 10 ms EEPROM Copy Endurance NEEC (Note 11) 50,000 cycles Note 1: All voltages are referenced to VSS. Note 2: Specifications relative to V IS1 - VIS2. Note 3: The DS2755 requires a maximum of 25µAH of charge to transition into sleep mode. Note 4: Summation of worst case time base and current measurement sampling errors. Note 5: Continuous offset cancellation corrects o ffset errors in the current measurement system. Individual values reported by the Current register have a maximum offset of ±0.5 LSb’s (±7.8125μV). Individual values reported in the Average Current register have a maximum offset of ±2 LSb’s (±7.8125μV). Note 6: Current Gain Error specifies the gain error in the Current r egister value compared to a reference voltage between IS1 and IS2. The DS2755 does not compensate for sense resistor characteristics, and any error terms arising from the sense resistor should be taken into account when calculating total current measurement error. Note 7: Achieving the 24 Hour Accumulated Current Error assumes pos itive offset accumulation blanking is enabled (OBEN bit set) and can require a one time 3.5s in-system calibration after mounting to the printed circuit board. Variations in temperature and supply voltage are compensated for by periodic offset corrections performed automatically during Active mode operation. Note 8: Voltage offset measurement is with respect to 4.2V at +25°C. Note 9: Self heating due to output pin loading and sense resistor power dissipation can alter the Temperature reading from ambient conditions. Note 10: Typical value for tERR valid at 3.7V and +25°C. tERR applies to all internal timings (ex. fSAMP, tSLEEP, tUVD) except for the 1-Wire Interface timings. Note 11: Four year data retention at +50°C.
Figure 2. FUNCTIONAL DIAGRAM displayed in Voltage Register. 3 PIO General purpose programmable I/O pin or optional interrupt output.
5 IS1 Current sense filter input 1
6 IS2 Current sense filter input 2
7 SNS Sense resistor connection. SNS attaches to pack end of current sense resistor. 143kbps. Optional interrupt output.
1 AND either of the following occur:
external capacitor. The RC filter extends the input range beyond ±64mV in pulse load or pulse charge applications. In snapshot mode, the Current regist er holds the current measured immediately following the snapshot trigger. The following register formats specify the update interval and units for the Current and Average Current registers. Figure 3. CURRENT REGISTER FORMAT
Figure 8. TEMPERATURE REGISTER FORMAT in this section, the PIO interrupt method must not be enabled. See the Interrupt Signaling section. level of the PIO pin is reported when the Special Feature Register is read via the serial interface. To use the PIO pin as an output, write the desired output value to the PIO bit in the Special Feature Register. the PIO bit forces the pin to a Hi-Z state. A pullup resistor or current source must be provided to force the pin high. is low for more than tSLEEP, regardless of the state of the PMOD bit. IE is set, an interrupt will be signaled if the alarm compar ator thresholds are crossed. A 1-Wire RESET clears IE. The host must re-enable interrupts by setting IE in the last transaction on the bus. falling or rising edge of either the RESET or Presence Pulse. bit (bit 7 in the Special Feature Register). A pullup resistor or current source must be provided to force the pin high. The host can sense the interrupt on the falling edge of PIO. The host may then poll the DS2755 to determine which threshold has been met or exceeded.
Figure 9. INTERRUPT THRESHOLD REGISTER FORMATS Measurement of the current and volt age can be synchronized to a system event with the Snapshot mode. voltage sample. The Snapshot results are reported in the Current and Voltage registers for retrieval by the host. process, it should be used sparingly.
within a single GSM timeslot. Figure 10. SNAPSHOT SYNCHRONIZATION TIMING byte register is read, the MSB and LSB values are latched and held for the duration of the Read Data command. results, always read the MSB and the LSB of a two-byte register during the same Read Data command sequence. require the host system to write them to a 0 value. RAM regardless of whether the block is locked or not.
Figure 9. EEPROM Access via Shadow RAM Table 1. MEMORY MAP
00 Reserved
01 Status Register R
07 EEPROM Register R/W
08 Special Feature Register R/W
10 Accumulated Current Register MSB R/W
11 Accumulated Current Register LSB R/W
18 Temperature Register MSB R
19 Temperature Register LSB R
*Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only. Figure 11. STATUS REGISTER FORMAT
only. The desired default value should be set in bit 5 of address 31h. The factory default is 0. address 31h. The factory default is 0. desired default value should be set in bit 3 of address 31h. The factory default is 0. should be set in bit 2 of address 31h. The factory default is 0. desired default value should be set in bit 1 of address 31h. The factory default is 0. of address 31h is 0 (Standard 1-Wire timing). Figure 12. EEPROM REGISTER FORMAT Lock command. After the Lock command is executed, the LOCK bit is reset to 0. The factory default is 0. locked (read-only), while a 0 indicates block 1 is unlocked (read/write). locked (read-only), while a 0 indicates block 1 is unlocked (read/write). locked (read-only), while a 0 indicates block 0 is unlocked (read/write).
DS2755: High-Accuracy Battery Fuel Gauge with Snapshot 16 of 20 TRANSACTION SEQUENCE The protocol for accessing the DS2755 through the 1-Wire port is as follows: Initialization Net Address Command Function Command Transaction/Data The sections that follow describe each of these steps in detail. All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the bus master followed by a presence pulse simultaneously transmitted by the DS2755 and any other slaves on the bus. The presence pulse tells the bus master that one or more devices are on the bus and ready to operate. For more details, see the I/O Signaling section. NET ADDRESS COMMANDS Once the bus master has detected the presence of one or more slaves, it can issue one of the net address commands described in the following paragraphs. The name of each command is followed by the 8-bit opcode for that command in square brackets. Figure 17 presents a transaction flowchart of the net address commands. Read Net Address [33h or 39h]. This command allows the bus master to read the DS2755’s 1-Wire net address. This command can only be used if there is a single slave on the bus. If more than one slave is present, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The RNAOP bit in the Status Register selects the opcode for this command, with RNAOP = 0 indicating 33h and RNAOP = 1 indicating 39h. Match Net Address [55h]. This command allows the bus master to specifically address one DS2755 on the 1-Wire bus. Only the addressed DS2755 responds to any subsequent function command. All other slave devices ignore the function command and wait for a reset pulse. This command can be used with one or more slave devices on the bus. Skip Net Address [CCh]. This command saves time when there is only one DS2755 on the bus by allowing the bus master to issue a function command without specifying the address of the slave. If more than one slave device is present on the bus, a su bsequent function command can cause a data collision when a ll slaves transmit data at the same time. Search Net Address [F0h]. This command allows the bus master to use a process of elimination to identify the 1- Wire net addresses of all slave devices on the bus. The s earch process involves the r epetition of a simple three- step routine: read a bit, read the complement of the bit, t hen write the desired value of that bit. The bus master performs this simple three-step routine on each bit locati on of the net address. After one complete pass through all 64 bits, the bus master knows the address of one devic e. The remaining devices can then be identified on additional iterations of the process. See Chapter 5 of the Book of DS19xx i Button® Standards for a comprehensive discussion of a net address search, including an act ual example. This publication can be found on the Maxim/Dallas website at www.maxim-ic.com. FUNCTION COMMANDS After successfully completing one of the net address co mmands, the bus master can access the features of the DS2755 with any of the function commands described in t he following paragraphs. The name of each function is followed by the 8-bit opcode for that command in square brackets. Read Data [69h, XX]. This command reads data from the DS2755 star ting at memory address XX. The LSb of the data in address XX is available to be read immediately after the MSb of the address has been entered. Because the address is automatically incremented after the MSb of each byte is received, the LSb of the data at address XX + 1 is available to be read immediately after the MSb of the data at address XX. If the bus master continues to read beyond address FFh, the DS2755 outputs logic 1 until a re set pulse occurs. Addresses labeled “reserved” in the memory map contain undefined data. The Read Data command can be terminated by the bus master with a reset pulse at any bit boundary. iButton is a registered trademark of Dallas Semiconductor.
data to be stored at address XX can be written immedi ately after the MSb of t he address has been entered. to shadow RAM rather than EEPROM. See the Memory section for more details. command execution time, tEEC, is 2ms typical and starts after the last address bit is transmitted. Sync [D2h, XX]. This command allows the bus to be used to tr igger current and voltage Snapshot readings. Following the issue of the Sync command, the bus returns to the idle state awaiting the measurement trigger. measurements. One Snapshot command must be issued for each Snapshot trigger event. Table 2. FUNCTION COMMANDS
Figure 17. NET ADDRESS COMMAND FLOW CHART
1 BYTE
6 BYTES
the DS2755 waits for tPDH and then transmits the Presence Pulse for tPDL. Figure 18. 1-WIRE INITIALIZATION SEQUENCE 1μs minimum recovery time, tREC, between cycles. must be pulled high within 15 μs in Standard mode or 2 μs in Overdrive mode after the st art of the write-time slot. the end of the write-time slot. the DS2755 accepts the bit value to be a 0. See Figure 19 for more information. A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level. DS2755. All read-time slots must be tSLOT in duration with a 1μs minimum recovery time, tREC, between cycles.
Figure 19. 1-WIRE WRITE AND READ TIME SLOTS