DS2720CU

DS2720 DALLAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 21

Technical content

FEATURES

/g167 Rechargeable Lithium-Ion (Li+) Safety Circuit - Overvoltage Protection - Overcurrent/Short-Circuit Protection - Undervoltage Protection - Overtemperature Protection /g167 Controls High-Side N-Channel Power MOSFETs Driven from 9V Charge Pump /g167 System Power Management and Control Feature Support /g167 Eight Bytes of Lockable EEPROM /g167 Dallas 1-Wire ® Interface with Unique 64-Bit Device Address /g167 8-Pin /g32/g109SOP Package /g167 Low Power Consumption: - Active Current: 12.5 /g109A typ - Sleep Current: 1.5 /g109A typ PIN CONFIGURATION PIN DESCRIPTION PLS - Battery-Pack Positive Terminal Input PS - Power-Switch Sense Input DQ - Data Input/Output V SS - Device Ground VDD - Power-Supply Input CP - Reservoir Capacitor CC - Charge Control Output DC - Discharge Control Output

DESCRIPTION

The DS2720 single-cell rechargeable Li+ protection IC provides electronic safety functions required for rechargeable Li+ applications including protecting th e battery during charge, protection of the circuit from damage during periods of excess current flow and maximization of battery life by limiting the level of cell depletion. Protection is fa cilitated by electronically disconn ecting the charge and discharge conduction path with switching devices such as low-cost N-channel power MOSFETs. Since the DS2720 provides high-side drive to external N-channel protection MOSFETs from a 9V charge pump, superior on-resistance performan ce results compared to common low-side protector circuits using the same FETs. The FET on-resistance actually decreases as the battery discharges. Adding to the uniqueness of the DS2720 is the ability of the system to control the FETs from either the data interface or a dedicated input thereby eliminating the power-sw itch control redundancy of rechargeable Li+ battery systems. Through its 1-Wire interface, the DS2720 gives the hos t system read/write access to status and control registers, instrumentation registers, and general-purpose data storage. Each device has a factory- programmed 64-bit net address that allows it to be individually addressed by the host system. DS2720U /g109SOP PS 8PLS DQ V SS VDD CC DC CP DS2720 Efficient, Addressable Single-Cell Rechargeable Lithium Protection IC www.maxim-ic.com 1-Wire is a registered trademark of Dallas Semiconductor.

Two types of user-memory are provided on the DS 2720 for battery information storage: EEPROM and lockable EEPROM. EEPROM memory saves important batte ry data in true nonvolatile (NV) memory that is unaffected by severe ba ttery depletion, accidental shorts , or ESD events. Lockable EEPROM becomes ROM when locked to provide additional security for unchanging battery data.

ORDERING INFORMATION

DS2720AU DS2720 in 8-Lead /g109SOP in Bulk with VOVA = 4.275V DS2720AU/T&R DS2720 in 8-Lead /g109SOP in Tape-and-Reel with VOVA = 4.275V DS2720BU DS2720 in 8-Lead /g109SOP in Bulk with VOVB = 4.35V DS2720BU/T&R DS2720 in 8-Lead /g109SOP in Tape-and-Reel with VOVB = 4.35V DS2720CU DS2720 in 8-Lead /g109SOP in Bulk with VOVC = 4.30V DS2720CU/T&R DS2720 in 8-Lead /g109SOP in Tape-and-Reel with VOVC = 4.30V

Figure 1. BLOCK DIAGRAM

Table 1. DETAILED PIN DESCRIPTION closure of a switch to VSS on this pin. PS has a high-impedance internal pullup. DATA terminal of the battery pack. DQ has an internal 0.5/g109A pull-down. VSS Device Ground. Connect directly to the negative terminal of the battery cell. Figure 2. APPLICATION EXAMPLE

mode, DS2720 resumes safety monitoring and conditionally turns on the protection FETs. Table 2. POWER MODE TRANSITION CONDITIONS (1) DS2720 does not transition to Active Mode if VDD < VSC. below and summarized in Table 3 and Figure 3. Table 3. PROTECTION CONDITIONS AND DS2720 RESPONSES All voltages are with respect to VSS. (1) During transition from sleep to active, tOVD = 0. RTST when recovery charge enabled. (3) With test current ITST flowing from VDD to PLS (pullup on PLS).

Overvoltage. If the cell voltage sensed at V DD exceeds overvoltage threshold V OV for a period longer than overvoltage delay t OVD, the DS2720 shuts off the external char ge FET and sets the OV flag in the protection register. Discharging remains enabled during overvoltage . The charge FET is re-enabled (unless another protection conditi on prevents it), when the cell voltage falls below charge enable threshold VCE, or a discharge causes VDD - VPLS > VOC. Undervoltage. If the cell voltage sensed at V DD drops below undervoltage threshold V UV for a period longer than undervoltage delay t UVD, the DS2720 shuts off the charge and discharge FETs, sets the UV flag in the protection register, and enters sleep mode. The DS2720 turns on both the charge and discharge FETs after the cell voltage rises above VUV and a charger is present. Short Circuit. If the cell voltage sensed at VDD drops below depletion threshold V SC for a period of t SCD, the DS2720 shuts off the charge and discharge FETs and sets the DOC flag in the protection register. The current path through the charge and discharge FETs is not re-established until the voltage on PLS rises above V DD - VOC. The DS2720 provides a test current through internal resistor R TST from VDD to PLS to pull up PLS when V DD rises above V SC. The test current allows the DS 2720 to detect the removal of the offending low-impedance load. Additionally, a recovery charge path through R TST from PLS to V DD is enabled. Overcurrent. If the voltage across the protection FETs (V DD - V PLS) is greater than V OC for a period longer than tOCD, the DS2720 shuts off the external charge a nd discharge FETs and sets the DOC flag in the protection register. The current path is not re-established until the voltage on PLS rises above V DD - VOC. The DS2720 provides a test current through internal resistor R TST from V DD to PLS to detect the removal of the offending low-impedance load. Overtemperature. If the device temperature exceeds T MAX, the DS2720 immediately shuts off the external discharge and charge FETs. The FETs are not turned back on until the cell temperature drops below T MAX AND the host resets the OT bit.

Figure 3. Li+ PROTECTION CIRCUITRY EXAMPLE WAVEFORMS IOC = Current that produces a voltage drop across FETs equal to VOC threshold. short-circuit threshold, VSC.

which should be written with the default values for the status register. to shadow RAM regardless of whether the block is locked or not. Table 4. MEMORY MAP

00 Protection Register R/W

01 Status Register R

07 EEPROM Register R

08 Special Feature Register R/W

(1) Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only. Figure 4. PROTECTION REGISTER FORMAT

detect future events. The OV bit is a volatile R/W bit, initialized to 0 upon power-on-reset (POR). volatile R/W bit, initialized to 1 upon POR. CC pin is driven high (VOHCC). The CC bit is a 0 when the CC pin is driven low (VOLCC). the DC pin is driven high (VOHDC). The DC bit is a 0 when the DC pin is driven low (VOLDC). from sleep mode to active mode. The CE bit is a volatile R/W bit, initialized to 1 upon POR. transitions from sleep mode to active mode. The DE bit is a volatile R/W bit, initialized to 1 upon POR. in detail in the following paragraphs. Figure 5. STATUS REGISTER FORMAT

BIT 5— This bit is read only. The value of this bit is set by bit 5 of address 31h and is factory set to 0. The value of address 31h bit 5 must not be changed. be set in bit 4 of address 31h. The factory default for RNAOP is 0. BIT 3— This bit is read only. The value of this bit is set by bit 3 of address 31h and is factory set to 0. The value of address 31h bit 3 must not be changed. in the following paragraphs. Figure 6. EEPROM REGISTER FORMAT EEC—EEPROM Copy Flag. A 1 in this read-only bit indicates that a copy data command is in progress. written to unlocked EEPROM blocks if the DS2720 is in the active mode of operation. bit is a volatile R/W bit, initialized to 0 upon POR. 30 to 33h) is locked (read-only) while a 0 indicates block 1 is unlocked (read/write). 20 to 23h) is locked (read-only) while a 0 indicates block 0 is unlocked (read/write).

detail in the following paragraphs. Figure 7. SPECIAL FEATURE REGISTER FORMAT to detect future events. This bit is initialized to a 1 upon POR. a volatile R/W bit, initialized to 0 upon POR. a low-impedance connection to VSS. Connecting PS to VSS wakes up the DS2720 if it was in sleep mode. If the DS2720 was in active mode, PS has no effect. 1-Wire Bus System section of this data sheet.

Figure 10. 1-WIRE BUS INTERFACE CIRCUITRY The sections that follow describe each of these steps in detail. RNAOP = 0 indicating 33h and RNAOP = 1 indicating 39h. one or more slave devices on the bus.

Skip Net Address [CCh]. This command saves time when there is only one 1-Wire device on the bus by allowing the bus master to issue a function command w ithout specifying the address of the slave. If more than one slave device is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at the same time. Search Net Address [F0h]. This command allows the bus master to use a process of elimination to identify the 1-Wire net addresses of all slave devices on the bus. The search process involves the repetition of a simple three-step routine: read a bit, r ead the complement of the bit, then write the desired value of that bit. The bus master performs this simple three-step routine on each bit location of the net address. After one complete pass through all 64 bits, the bus master knows the address of one device. The remaining devices can then be identified on additional iterations of the process. See Chapter 5 of the Book of DS19xx iButton® Standards for a comprehensive discussion of a net address search, including an actual example. Resume Command [A5H]. In a typical application the DS2720 can be accessed several times to complete control adjustment. To maximize data throughput in a multidrop environment, the resume command has been implemented. This function checks the st atus of an internal flag. If it is set, it directly transfers control in similar fashion to the skip net address command. The only way to set the internal flag is through successfully executing the match net address or search net address. Once the flag has been set, the device can be repeatedly accessed through the resume command. Accessing another device on the bus clears the flag, thus preventing two or more devi ces from simultaneously responding to the resume command function. FUNCTION COMMANDS After successfully completing one of the net address commands, the bus master can access the features of the DS2720 with any of the function commands described in the following paragraphs. The name of each function is followed by the 8-bit opcode for that command in square brackets. The function commands are summarized in Table 5. Read Data [69h, XX]. This command reads data from the DS2720 starting at memory address XX. The LSb of the data in address XX is available to be re ad immediately after the MSb of the address has been entered. Because the address is automatically incremented after the MSb of each byte is received, the LSb of the data at address XX + 1 is available to be read immediately after the MSb of the data at address XX. If the bus master continues to read beyond address FF h, data is read starting at memory address 00 and the address is automatically incremented until a reset pulse occurs. Addresses labeled “Reserved” in the memory map contain undefined data. The read data command can be terminated by the bus master with a reset pulse at any bit boundary. Write Data [6Ch, XX]. This command writes data to the DS2720 starting at memory address XX. The LSb of the data to be stored at address XX can be written immediately after the MSb of address has been entered. Because the address is automatically incremented after the MSb of each byte is written, the LSb to be stored at address XX + 1 can be written immediately after the MSb to be stored at address XX. If the bus master continues to write beyond address FFh, the data starting at address 00 is overwritten. Writes to read-only addresses, re served addresses and locked EEPRO M blocks are ignored. Incomplete bytes are not written. Writes to unlocked EEPROM blocks are to shadow RAM rather than EEPROM. See the Memory section for more details. Copy Data [48h, XX]. This command copies the contents of shadow RAM to EEPROM for the 4-byte EEPROM block containing address XX. Copy data co mmands that address locked blocks are ignored. While the copy data command is executing, the EEC bit in the EEPROM register is set to 1 and writes to iButton is a registered trademark of Dallas Semiconductor.

DS2720 while in the sleep mode. Table 5. FUNCTION COMMANDS

Figure 11. NET ADDRESS COMMAND FLOW CHART

1 BYTE

6 BYTES

data. All of these types of signaling except the presence pulse are initiated by the bus master. The initialization sequence required to begin any communication with the DS2720 is shown in Figure 12. A presence pulse following a reset pulse indicates the DS2720 is ready to accept a net address command. PDH and then transmits the presence pulse for tPDL. Figure 12. 1-WIRE INITIALIZATION SEQUENCE slot, the bus line must be pulled low and held low for the duration of the write-time slot. with a 1/g109s minimum recovery time, tREC, between cycles. See Figure 13 for more information.

Figure 13. 1-WIRE WRITE- AND READ-TIME SLOTS

ABSOLUTE MAXIMUM RATINGS* Voltage on PLS, Relative to VSS -0.3V to +18V Voltage on CC, DC, and CP Pins, Relative to VSS -0.3V to +12V Voltage on any Other Pin, Relative to VSS -0.3V to +6V Operating Temperature Range -40°C to +85°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDEC-STD-020A This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (-20/g176C to +70/g176C, 2.5V /g163 VDD /g163 5.5V) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Supply Voltage V DD 2.5 5.5 V 1 Data Pin DQ -0.3 5.5 V 1 DC ELECTRICAL CHARACTERISTICS (-20/g176C to +70/g176C, 2.5V /g163 VDD /g163 4.5V) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES DQ = VDD 0/g176C /g163 TA /g163 50/g176C 12.5 20 /g109A 2Active Current I ACTIVE DQ = VDD 25 /g109A 2 Sleep Mode Current I SLEEP DQ = 0V, PS floating 1.5 2.5 /g109A Input Logic High: DQ V IH1 1.5 V 1 Input Logic High: PS VIH2 VDD - 0.2V V1 , 6 Input Logic Low: DQ V IL1 0.4 V 1 Input Logic Low: PS VIL2 0.2 V 1 Output Logic High: CC, DC VOHCP RLOAD > 10M/g87 8.5 9.0 9.5 V 1 Output Logic Low: CC VOLCC RLOAD > 10M/g87 VDD VDD + 0.1 V1 Output Logic Low: DC VOLDC RLOAD > 10M/g87 VPLS /g163 10V VPLS VPLS +

0.1 V1 , 7

Output Logic Low: DQ VOL1 IOL = 4mA 0.4 V 1 DQ Input Pulldown Current IPD VDQ = 0.4V 0.1 0.5 2.5 /g109A PS Pullup Current IPS VPS = 0.4V 100 nA CC Pulldown Resistance RCCPD 1.2 4 k/g87 DC Pulldown Resistance RDCPD 12 16 k/g87

ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUITRY (0/g176C to +50/g176C, 2.5V /g163 VDD /g163 4.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES VOVA 4.250 4.275 4.300 Overvoltage Detect V OVB 4.325 4.350 4.375 V 1, 3 VOVC 4.275 4.300 4.325 Charge Enable V CE Typ - 75mV VOV/1.022 Typ + 75mV V1 , 3 Undervoltage Detect V UV Typ - 120mV VOV/1.55 Typ + 120mV V1 , 3 Overtemperature Detect T MAX 70 90 110 /g176C 3 Overcurrent Detect V OC 140 200 260 mV 1, 3 Short-Circuit Detect V SC 2.0 2.3 2.6 V 1 Overvoltage Delay t OVD 0.75 1.0 1.25 s 3 Undervoltage Delay t UVD 90 125 160 ms 3 Overcurrent Delay t OCD 12 16 20 ms 3 Short-Circuit Delay t SCD 50 100 150 /g109s Test Resistance, ITST Active R TST1 31 1 k/g87 5 Test Resistance, Recovery Charging RTST2 51 5 k/g87 5 Charger Detect Voltage V CH 20 60 120 mV ELECTRICAL CHARACTERISTICS: 1-WIRE INTERFACE (-20/g176C to +70/g176C, 2.5V /g163 VDD /g163 5.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Time Slot t SLOT 60 120 /g109s Recovery Time t REC 1 /g109s Write 0 Low Time t LOW0 60 120 /g109s Write 1 Low Time t LOW1 11 5 /g109s Read Data Valid t RDV 15 /g109s Reset Time High t RSTH 480 /g109s Reset Time Low t RSTL 480 960 /g109s Presence Detect High t PDH 15 60 /g109s Presence Detect Low t PDL 60 240 /g109s Active Transition to CC/DC Engage tON 100 ms 4 DQ Capacitance C DQ 25 pF

SPECIFICATION: (-20/g176C to +70/g176C, 2.5V /g163 VDD /g163 5.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Copy to EEPROM Time t EEC 15 m s EEPROM Copy Endurance N EEC 25,000 cycles EEPROM Data Retention t EEDR 4 years NOTES 1. All voltages are referenced to VSS. 2. Specified with no resistive load on CC, DC, or CP. 3. Contact the factory for different voltage trip points and delay periods. 4. Typical load capacitance on CC, DC is 1000pF CP (charge pump reservoir cap) = 0.1/g109F. DC load total on CC, DC, CP > 10M/g87. 5. RTST = |VPLS - VDD| / I measured, with VPLS = 3.2V, VDD = 3.6V when test current, ITST, active for RTST1 ; and VPLS = 4.0V, VDD = 2.5V when recovery charging for RTST2. 6. Maximum high-to-low fall time is 5/g109s. 7. Internal 10V clamp on DC pin limits DC output logic low when PLS > 10V 8. Short-circuit delay tested with VDD ramped from 3.1V to 1.9V in 5/g109s. Delay measured from VDD = 2.5V to DC pin fall to 7V from VOHCP.