DS2431

DS2431 DALLAS | Alldatasheet

Document overview

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Technical content

1 of 23 REV: 050704 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS2431 is a 1024-bit, 1-Wire ® EEPROM chip organized as four memory pages of 256 bits each. Data is written to an 8-byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, the four memory pages can individually be write protected or put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 state. The DS2431 communicates over the single- conductor 1-Wire bus. The communication follows the standard Dallas Semiconductor 1-Wire protocol. Each device has its own unalterable and unique 64- bit ROM registration number that is factory lasered into the chip. The registration number is used to address the device in a multidrop 1-Wire net environment.

APPLICATIONS

Accessory/PC Board Identification Medical Sensor Calibration Data Storage Analog Sensor Calibration Including IEEE- P1451.4 Smart Sensors Ink and Toner Print Cartridge Identification After-Market Management of Consumables TYPICAL OPERATING CIRCUIT µC I/O DS2431 GND RPUP VCC

FEATURES

! 1024 Bits of EEPROM Memory Partitioned into Four Pages of 256 Bits ! Individual Memory Pages can be Permanently Write Protected or Put in EPROM-Emulation Mode ("Write to 0") ! Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise ! IEC 1000-4-2 Level 4 ESD Protection (8kV Contact, 15kV Air) ! Reads and Writes Over a Wide Voltage Range of 2.8V to 5.25V from -40°C to +85°C ! Communicates to Host with a Single Digital Signal at 15.4kbps or 111kbps Using 1-Wire Protocol

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE DS2431 -40°C to 85°C TO-92 DS2431/T&R -40°C to 85°C TO-92, tape & reel DS2431P -40°C to 85°C TSOC DS2431P/T&R -40°C to 85°C TSOC, tape & reel DS2431X -40°C to 85°C CSP, tape & reel PIN CONFIGURATION 1 2 3 1 2 3 TO-92 TSOC, Top View TSOC, TO-92 pinout: All other pins -- NC CSP, approx. 68 × 68 mil Top view, bumps not visible A B A1 = NC A2 = I/O B1 = NC B2 = GND DS2431 1024-Bit 1-Wire EEPROM www.maxim-ic.com Commands, Registers, and Modes are capitalized for clarity. 1-Wire is a registered trademark of Dallas Semiconductor Corp.

DS2431: 1024-Bit, 1-Wire EEPROM 2 of 23 ABSOLUTE MAXIMUM RATINGS I/O Voltage to GND -0.5V, +6V I/O Sink Current 20mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -40°C to +85°C Soldering Temperature See IPC/JEDEC J-STD-020A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(VPUP = 2.8V to 5.25V, TA = -40°C to +85°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I/O PIN GENERAL DATA 1-Wire Pullup Resistance RPUP (Notes 1, 2) 0.3 2.2 kΩ Input Capacitance C IO (Notes 3, 4) 100 800 pF Input Load Current I L I/O pin at VPUP 0.05 2.2 µA High-to-Low Switching Threshold VTL (Notes 4, 5, 6) 0.5 4.1 V Input Low Voltage V IL (Notes 1, 7) 0.3 V Low-to-High Switching Threshold VTH (Notes 4, 5, 8) 1.0 4.9 V Switching Hysteresis V HY (Notes 4, 5, 9) 0.22 1.70 V Output Low Voltage V OL At 4mA (Note 10) 0.4 V Standard speed, RPUP = 2.2kΩ 5 Overdrive speed, RPUP = 2.2kΩ 2Recovery Time (Notes 1,11) tREC Overdrive speed, directly prior to reset pulse; RPUP = 2.2kΩ 5 µs Standard speed (Note 12) 0.5 5.0Rising-Edge Hold-off Time t REH Overdrive speed Not applicable (0) µs Standard speed 65Timeslot Duration (Note 1) t SLOT Overdrive speed (Note 13) 9 µs I/O PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE Standard speed, VPUP > 4.5V 480 640 Standard speed (Note 12) 504 640 Overdrive speed, VPUP > 4.5V 48 80Reset Low Time (Note 1) t RSTL Overdrive speed (Note 13) 53 80 µs Standard speed, VPUP > 4.5V 15 60 Standard speed (Note 13) 15 63Presence Detect High Time tPDH Overdrive speed (Note 13) 2 7 µs Standard speed, VPUP > 4.5V 1.1 3.75 Standard speed 1.1 7Presence Detect Fall Time (Notes 4, 14) tFPD Overdrive speed 1.1 µs Standard speed 60 240 Overdrive speed, VPUP > 4.5V 8 24Presence Detect Low Time tPDL Overdrive speed (Note 13) 8 26 µs Standard speed, VPUP > 4.5V 64 75 Standard speed 70 75Presence Detect Sample Time (Note 1) tMSP Overdrive speed 8.1 10 µs

DS2431: 1024-Bit, 1-Wire EEPROM 3 of 23 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I/O PIN, 1-Wire WRITE Standard speed 60 120Write-0 Low Time (Note 1) t W0L Overdrive speed (Note 13) 71 6 µs Standard speed 5 15 - εWrite-1 Low Time (Notes 1, 15) tW1L Overdrive speed 1 2 - ε µs I/O PIN, 1-Wire READ Standard speed 5 15 - δRead Low Time (Notes 1, 16) tRL Overdrive speed 1 2 - δ µs Standard speed tRL + δ 15Read Sample Time (Notes 1, 16) tMSR Overdrive speed tRL + δ 2 µs EEPROM Programming Current I PROG (Note 17) 1 mA Programming Time t PROG (Note 18) 12.5 ms At 25°C 200kWrite/Erase Cycles (Endurance) NCY At 85°C (worst case) 50k --- Data Retention t DR At 85°C (worst case) 10 years Note 1: System requirement. Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Note 3: Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2kΩ resistor is used to pull up the data line, 2.5µs after VPUP has been applied the parasite capacitance will not affect normal communications. Note 4: Guaranteed by design, simulation only. Not production tested. Note 5: VTL, VTH, and VHY are a function of the internal supply voltage. Note 6: Voltage below which, during a falling edge on I/O, a logic 0 is detected. Note 7: The voltage on I/O needs to be less or equal to VILMAX whenever the master drives the line low. Note 8: Voltage above which, during a rising edge on I/O, a logic 1 is detected. Note 9: After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least VHY to be detected as logic '0'. Note 10: The I-V characteristic is linear for voltages less than 1V. Note 11: Applies to a single DS2431 attached to a 1-Wire line. Note 12: The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached. Note 13: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below. Note 14: Interval during the negative edge on I/O at the beginning of a Presence Detect pulse between the time at which the voltage is 80% of VPUP and the time at which the voltage is 20% of VPUP. Note 15: ε represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. Note 16: δ represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold of the bus master. Note 17: Current drawn from I/O during the EEPROM programming interval. The pullup circuit on I/O during the programming interval should be such that the voltage at I/O is greater than or equal to Vpup(min). If Vpup in the system is close to Vpup(min) then a low impedance bypass of Rpup which can be activated during programming may need to be added. Note 18: Interval begins tWiLMIN after the leading negative edge on IO for the last timeslot of the E/S byte for a valid Copy Scratchpad sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from IPROG to IL. LEGACY VALUES DS2431 VALUES PARAMETER STANDARD SPEED OVERDRIVE SPEED STANDARD SPEED OVERDRIVE SPEED MIN MAX MIN MAX MIN MAX MIN MAX tRSTL 480µs (undef.) 48µs 80µs 504µs 640µs 53µs 80µs tPDH 15µs 60µs 2µs 6µs 15µs 63µs 2µs 7µs tPDL 60µs 240µs 8µs 24µs 60µs 240µs 8µs 26µs tW0L 60µs 120µs 6µs 16µs 60µs 120µs 7µs 16µs 1) Intentional change, longer recovery time requirement due to modified 1-Wire front end. PIN DESCRIPTION NAME FUNCTION I/O 1-Wire Bus Interface. Open drain, requires external pullup resistor. GND Ground Reference N.C. Not Connected

DS2431: 1024-Bit, 1-Wire EEPROM 4 of 23

DESCRIPTION

The DS2431 combines 1024 bits of EEPROM, an 8-byte register/control page with up to 7 user read/write bytes, and a fully-featured 1-Wire interface in a single chip. Each DS2431 has its own 64-bit ROM registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability. Data is transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return. The DS2431 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory or the register page. Data is first written to the scratchpad from which it can be read back. After the data has been verified, a copy scratchpad command transfers the data to its final memory location. Applications of the DS2431 include accessory/PC board identification, medical sensor calibration data storage, analog sensor calibration including IEEE-P1451.4 Smart Sensors, ink and toner print cartridge identification, and after-market management of consumables. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2431. The DS2431 has four main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3) four 32-byte pages of EEPROM, and 4) 64-bit register page. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the seven ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive-Skip ROM or 7) Overdrive-Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device enters Overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 9. After a ROM function command is successfully executed, the memory functions become accessible and the master may provide any one of the four memory function commands. The protocol for these memory function commands is described in Figure 7. All data is read and written least significant bit first. Figure 1. Block Diagram

4 Pages of

Figure 5. Memory Map write-protect the address nor activate any function. 16 rows are divided equally into 4 memory pages (32 bytes each). These 4 pages are the primary data memory. associated protection byte in the register row. The last two rows contain protection registers, and reserved bytes. functionality and should not be used.

other protection control register setting leaves the associated memory page open for unrestricted write access. with the current data) in the device. write-protected main memory pages (i. e., refresh) are blocked. the target memory address. Writing data to the scratchpad clears this flag. Figure 6. Address Registers

DS2431: 1024-Bit, 1-Wire EEPROM 8 of 23 WRITING WITH VERIFICATION To write data to the DS2431, the scratchpad has to be used as intermediate storage. First the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. Note that Copy Scratchpad commands must be performed on 8-byte boundaries, i. e., the 3 LSBs of blocked. Under certain conditions (see Write Scratchpad command) the master will receive an inverted CRC16 of the command, address (actual address sent) and data at the end of the Write Scratchpad command sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself to decide if the communication was successful and proceed to the Copy Scratchpad command. If the master could not receive the CRC16, it should send the Read Scratchpad command to verify data integrity. As a preamble to the scratchpad data, the DS2431 repeats the target address TA1 and TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the scratchpad or there was a loss of power since data was last written to the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag together with a cleared PF flag indicates that the device did not recognize the Write command. If everything went correctly, both flags are cleared. Now the master can continue reading and verifying every data byte. After the master has verified the data, it can send the Copy Scratchpad command, for example. This command must be followed exactly by the data of the three address registers, TA1, TA2, and E/S. The master should obtain the contents of these registers by reading the scratchpad. MEMORY FUNCTION COMMANDS The Memory Function Flow Chart (Figure 7) describes the protocols necessary for accessing the memory of the DS2431. An example on how to use these functions to write to and read from the device is included at the end of this document. The communication between master and DS2431 takes place either at regular speed (default, OD = 0) or at Overdrive Speed (OD = 1). If not explicitly set into the Overdrive Mode, the DS2431 assumes regular speed. WRITE SCRATCHPAD COMMAND [0Fh] The Write Scratchpad command applies to the data memory, and the writable addresses in the register page. In order for the scratchpad data to be valid for copying to the array, the user must perform a Write Scratchpad command of 8 bytes starting at a valid row boundary. The Write Scratchpad command accepts invalid addresses, and partial rows, but subsequent Copy Scratchpad commands are blocked. After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset of T2:T0. The ES bits E2:E0 are loaded with the starting byte offset, and increment with each susequent byte. Effectively, E2:E0 is the byte offset of the last full byte written to the scratchpad. Only full data bytes are accepted. When executing the Write Scratchpad command, the CRC generator inside the DS2431 (Figure 13) calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target Addresses (TA1 and TA2), and all the data bytes. Note that the CRC16 calculation is performed with the actual TA1 and TA2 and data sent by the master. The master may end the Write Scratchpad command at any time. However, if the end of the scratchpad is reached (E2:E0 = 111b), the master may send 16 read-time slots and receive the CRC generated by the DS2431. If a Write Scratchpad is attempted to a write-protected location, the scratchpad is loaded with the data already in memory, rather than the data transmitted. Similarly, if the target address page is in EPROM mode, the scratchpad is loaded with the bitwise logical AND of the transmitted data and data already in memory.

DS2431: 1024-Bit, 1-Wire EEPROM 9 of 23 Figure 7-1. Memory Function Flow Chart 0Fh Write Scratch- pad ? Bus Master TX TA1 (T7:T0), TA2 (T15:T8) Y N To Figure 7 nd Part From Figure 7 nd Part Bus Master TX Memory Function Command To ROM Functions Flow Chart (Figure 9) From ROM Functions Flow Chart (Figure 9) Applies only if the memory area is not protected. If write-protected, then the DS2431 copies the data byte from the tar- get address into the SP. If in EPROM mode, then the DS2431 loads the bitwise logical AND of the transmitted byte and the data byte from the targeted address into the SP. Master TX Reset ? Master TX Data Byte To Scratchpad DS2431 sets Sets PF = 1 Clears AA = 0 Sets E2:E0 = T2:T0 DS2431 Increments E2:E0 Master TX Reset ? Y DS2431 TX CRC16 of Command, Address, Data Bytes as they were sent by the bus master N Y PF = 0 N Y E2:E0 = 7 ? Bus Master RX “1”s N N Y T2:T0 = 0 ?

DS2431: 1024-Bit, 1-Wire EEPROM 10 of 23 Figure 7-2. Memory Function Flow Chart (continued) AAh Read Scratch- Pad ? DS2431 sets Scratchpad Byte Counter = T2:T0 Bus Master RX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte Bus Master RX Data Byte from Scratchpad Bus Master RX CRC16 of Command, Address, E/S Byte, Data Bytes as sent by the DS2431 Y Master TX Reset ? Y Bus Master RX “1”s N Master TX Reset ? DS2431 Increments Byte Counter Byte Counter = E2:E0 ? Y Y N N N From Figure 7 st Part To Figure 7 st Part To Figure 7 rd Part From Figure 7 rd Part

DS2431: 1024-Bit, 1-Wire EEPROM 11 of 23 Figure 7-3. Memory Function Flow Chart (continued) * 1-Wire idle high for power From Figure 7 nd Part To Figure 7 nd Part To Figure 7 th Part From Figure 7 th Part 55h Copy Scratch- Pad ? Bus Master TX TA1 (T7:T0), TA2 (T15:T8) and E/S Byte Y N Bus Master RX “1”s Master TX Reset ? Y N YAuth. Code Match ? N N Copy- Protected ? Y DS2431 copies Scratch- pad Data to Address AA = 1 DS2431 TX “0” Master TX Reset ? Master TX Reset ? Y N DS2431 TX “1” N Y Applicable to all R/W memory locations. YT15:T0 < 0090h ? N PF = 0 ? Y N

DS2431: 1024-Bit, 1-Wire EEPROM 12 of 23 Figure 7-4. Memory Function Flow Chart (continued) F0h Read Memory ? Address < 90h ? Y N Bus Master TX TA1 (T7:T0), TA2 (T15:T8) Y N DS2431 sets Memory Address = (T15:T0) DS2431 Increments Address Counter Bus Master RX “1”s N Address < 8Fh ? Master TX Reset ? Y N Y Master TX Reset ? Bus Master RX Data Byte from Memory Address Y N From Figure 7 rd Part To Figure 7 rd Part N Bus Master RX “1”s Master TX Reset ? Y

DS2431: 1024-Bit, 1-Wire EEPROM 13 of 23 READ SCRATCHPAD COMMAND [AAh] The Read Scratchpad command allows verifying the target address and the integrity of the scratchpad data. After issuing the command code, the master begins reading. The first two bytes are the target address. The next byte is the ending offset/data status byte (E/S) followed by the scratchpad data, which may be different from what the master originally sent. This is of particular importance if the target address is within the register page or a page in either Write Protection or EPROM modes. See the Write Scratchpad description for details. The master should read through the scratchpad (E2:E0 – T2:T0 + 1 bytes), after which it will receive the inverted CRC, based on data as it was sent by the DS2431. If the master continues reading after the CRC, all data will be logic 1s. COPY SCRATCHPAD [55h] The Copy Scratchpad command is used to copy data from the scratchpad to writable memory sections. After issuing the Copy Scratchpad command, the master must provide a 3-byte authorization pattern, which should have been obtained by an immediately preceding Read Scratchpad command. This 3-byte pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the target address is valid, the PF flag is not set, and the target memory is not copy-protected, the AA (Authorization Accepted) flag is set and the copy begins. All eight bytes of scratchpad contents are copied to the target memory location. The device’s internal data transfer takes 13ms maximum during which the voltage on the 1-Wire bus must not fall below 2.8V. A pattern of alternating 0s and 1s are transmitted after the data has been copied until the master issues a reset pulse. If the PF flag is set or the target memory is copy-protected, the copy will not begin and the AA flag will not be set. READ MEMORY [F0h] The Read Memory command is the general function to read data from the DS2431. After issuing the command, the master must provide the 2-byte target address. After these two bytes, the master reads data beginning from the target address and may continue until address 008Fh. If the master continues reading, the result will be logic 1s. The device's internal TA1, TA2, E/S, and scratchpad contents are not affected by a Read Memory command. 1-Wire BUS SYSTEM The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the DS2431 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master. HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or tri-state outputs. The 1-Wire port of the DS2431 is open drain with an internal circuit equivalent to that shown in Figure 8. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The DS2431 supports both a Standard and Overdrive communication speed of 15.4kbps (max) and 111kbps (max), respectively. Note that legacy 1-Wire products support a standard communication speed of 16.3kbps and Overdrive of 142kbps. The slightly reduced rates for the DS2431 are a result of additional recovery times, which in turn were driven by a 1-Wire physical interface enhancement to improve noise immunity. The value of the pullup resistor primarily depends on the network size and load conditions. The DS2431 requires a pullup resistor of 2.2k Ω (max) at any speed. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs (Overdrive speed) or more than 120µs (standard speed), one or more devices on the bus may be reset.

Figure 8. Hardware Configuration result). The resultant family code and 48-bit serial number result in a mismatch of the CRC. single or multiple devices on the bus.

DS2431: 1024-Bit, 1-Wire EEPROM 15 of 23 SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its registration number bit. On the second slot, each slave device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the romcode tree. After one complete pass, the bus master knows the registration number of a single device. Additional passes identify the registration numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. SKIP ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a Read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). RESUME [A5h] To maximize the data throughput in a multidrop environment, the Resume function is available. This function checks the status of the RC bit and, if it is set, directly transfers control to the Memory functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume Command function. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the Resume Command function. OVERDRIVE SKIP ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the DS2431 in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus, this command sets all Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Overdrive-supporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). OVERDRIVE MATCH ROM [69h] The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive Speed allows the bus master to address a specific DS2431 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the DS2431 that exactly matches the 64-bit ROM sequence responds to the subsequent memory function command. Slaves already in Overdrive mode from a previous Overdrive Skip or successful Overdrive Match command remain in Overdrive mode. All overdrive-capable slaves return to standard speed at the next Reset Pulse of minimum 480µs duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus.

DS2431: 1024-Bit, 1-Wire EEPROM 16 of 23 Figure 9-1. ROM Functions Flow Chart From Figure 9 nd PartTo Memory Functions Flow Chart (Figure 7) Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 Bit 63 Match ? RC = 0 DS2431 TX Bit 0 DS2431 TX Bit 0 Master TX Bit 0 DS2431 TX Bit 1 DS2431 TX Bit 1 Master TX Bit 1 DS2431 TX Bit 63 DS2431 TX Bit 63 Master TX Bit 63 RC = 1 Bit 1 Match ? Bit 0 Match ? Y N Y N Y NBit 63 Match ? RC = 0 RC = 1 Bit 1 Match ? Bit 0 Match ? Y N Y N Y N RC = 0 DS2431 TX CRC Byte DS2431 TX Serial Number (6 Bytes) DS2431 TX Family Code (1 Byte) RC = 0 To Figure 9 nd PartNF0h Search ROM Command ? N55h Match ROM Command ? N CCh Skip ROM Command ? YY YY N33h Read ROM Command ? To Figure 9 nd Part From Memory Functions Flow Chart (Figure 7) Bus Master TX ROM Function Command DS2431 TX Presence Pulse OD Reset Pulse ? N Y OD = 0 Bus Master TX Reset Pulse From Figure 9, 2 nd Part

DS2431: 1024-Bit, 1-Wire EEPROM 17 of 23 Figure 9-2. ROM Functions Flow Chart (continued) To Figure 9 st Part From Figure 9 st Part From Figure 9 st Part To Figure 9, 1 st Part Y NA5h Resume Command ? RC = 1 ? Y N3Ch Overdrive Skip ROM ? RC = 0 ; OD = 1 Master TX Reset ? Y N N Y Master TX Reset ? N Y Master TX Bit 0 Master TX Bit 63 Master TX Bit 1 Bit 63 Match ? RC = 0 ; OD = 1 RC = 1 Bit 1 Match ? Y N Y N Bit 0 Match ? Y N Y N69h Overdrive Match ROM ? OD = 0 OD = 0 OD = 0

the DS2431 needs a recovery time tREC before it is ready for the next time slot. Figure 11. Read/Write Timing Diagram

magnitude of noise injected by the slave device itself. The 1-Wire front end of the DS2431 differs from traditional slave devices in four characteristics. which has different values for standard and Overdrive speed. 2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed. below VTH - VHY, it will not be recognized (Figure 12, Case A). The hysteresis is effective at any 1-Wire speed. taken as the beginning of a new time slot (Figure 12, Case C, tGL ≥ tREH). Figure 12. Noise Suppression Scheme

(noninverted) form. It is computed at the factory and lasered into the ROM. to continue with an operation or to reread the portion of the data with the CRC error. master. The DS2431 transmits this CRC only if E2:E0 = 111b. by the DS2431. The DS2431 transmits this CRC only if the reading continues through the end of the scratchpad. For more information on generating CRC values, refer to Application Note 27. Figure 13. CRC-16 Hardware Description and Polynomial

DS2431: 1024-Bit, 1-Wire EEPROM 22 of 23 COMMAND-SPECIFIC 1-Wire COMMUNICATION PROTOCOL—LEGEND SYMBOL DESCRIPTION RST 1-Wire Reset Pulse generated by master. PD 1-Wire Presence Pulse generated by slave. Select Command and data to satisfy the ROM function protocol. WS Command "Write Scratchpad". RS Command "Read Scratchpad". CPS Command "Copy Scratchpad". RM Command "Read Memory". TA Target Address TA1, TA2. TA-E/S Target Address TA1, TA2 with E/S byte. <8 – T2:T0 bytes> Transfer of as many bytes as needed to reach the end of the scratchpad for a given target address. <data to EOM> Transfer of as many data bytes as are needed to reach the end of the memory. CRC16\\ Transfer of an inverted CRC16. FF loop Indefinite loop where the master reads FF bytes. AA loop Indefinite loop where the master reads AA bytes. Programming Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time. WRITE SCRATCHPAD (CANNOT FAIL) RST PD Select WS TA <8 – T2:T0 bytes> CRC16\\ FF loop READ SCRATCHPAD (CANNOT FAIL) RST PD Select RS TA-E/S <8 – T2:T0 bytes> CRC16\\ FF loop COPY SCRATCHPAD (SUCCESS) RST PD Select CPS TA-E/S Programming AA loop COPY SCRATCHPAD (INVALID ADDRESS OR PF = 1 OR COPY PROTECTED) RST PD Select CPS TA-E/S FF loop READ MEMORY (SUCCESS) RST PD Select RM TA <data to EOM> FF loop READ MEMORY (INVALID ADDRESS) RST PD Select RM TA FF loop

DS2431: 1024-Bit, 1-Wire EEPROM 23 of 23 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2004 Maxim Integrated Products • Printed USA MAXIM is a registered trademark of Maxim Integrated Products, Inc. DALLAS is a registered trademark of Dallas Semiconductor Corporation. MEMORY FUNCTION EXAMPLE Write to the first 8 bytes of memory page 1. Read the entire memory. With only a single DS2431 connected to the bus master, the communication looks like this: MASTER MODE DATA (LSB FIRST) COMMENTS TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX 0Fh Issue “Write scratchpad” command TX 20h TA1, beginning offset=20h TX 00h TA2, address=0020h TX <8 data bytes> Write 8 bytes of data to scratchpad RX <2 bytes CRC16\\> Read CRC to check for data integrity TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX AAh Issue “Read scratchpad” command RX 20h Read TA1, beginning offset=20h RX 00h Read TA2, address=0020h RX 07h Read E/S, ending offset=111b, AA, PF = 0 RX <8 data bytes> Read scratchpad data and verify RX <2 bytes CRC16\\> Read CRC to check for data integrity TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX 55h Issue “copy scratchpad” command TX 20h TA1 TX 00h TA2 (AUTHORIZATION CODE) TX 07h E/S ---- <1-Wire idle high> Wait 13 ms for the copy function to complete RX AAh Read copy status, AAh = success TX (Reset) Reset pulse RX (Presence) Presence pulse TX CCh Issue “Skip ROM” command TX F0h Issue “Read Memory” command TX 00h TA1, beginning offset=00h TX 00h TA2, address=0000h RX <144 data bytes> Read the entire memory TX (Reset) Reset pulse RX (Presence) Presence pulse

PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)