DS2411R/R

DS2411 DALLAS | Alldatasheet

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Technical content

1-Wire is a registered trademark of Dallas Semiconductor. 1 of 11 052003

FEATURES

/g167 Unique, Factory-Lasered and Tested 64-Bit Registration Number (8-Bit Family Code Plus 48-Bit Serial Number Plus 8-Bit CRC Tester); Guaranteed No Two Parts Alike /g167 Standby Current <1µA /g167 Built-In Multidrop Controller Enables Multiple DS2411s to Reside on a Common 1-Wire /g226 Network /g167 Multidrop Compatible with Other 1-Wire Products /g167 8-Bit Family Code Identifies Device as DS2411 to the 1-Wire Master /g167 Low-Cost TSOC, SOT23-3, and Flip-Chip Surface-Mount Packages /g167 Directly Connects to a Single-Port Pin of a Microprocessor and Communicates at up to 15.4kbps /g167 Overdrive Mode Boosts Communication Speed to 125kbps /g167 Operating Range: 1.5V to 5.25V, -40°C to +85°C

ORDERING INFORMATION

T&R -40/g176C to +85/g176C SOT23-3, Tape-and-Reel DS2411P -40/g176C to +85/g176C TSOC DS2411P/ T&R -40/g176C to +85/g176C TSOC, Tape-and-Reel DS2411X -40/g176C to +85/g176C Flip Chip, Tape-and-Reel PIN CONFIGURATION 1 2 SOT23-3, Top View TSOC, Top View AB Flip Chip, Top view, bumps not visible PIN DESCRIPTION PIN NAME SOT23 TSOC FLIP CHIP I/O 1 2 A1 VCC 26B 2 GND 3 1 B1 N.C. — 3 A2 N.C. — 4 — N.C. — 5 —

DESCRIPTION

The DS2411 silicon serial number is a low-cost, electronic registration number with external power supply. It provides an absolutely unique identity that can be determined with a minimal electronic interface (typically, a single port pin of a microcontroller). The DS2411’s registration number is a factory-lasered, 64-bit ROM that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit family code (01h). Data is transferred serially through the Dallas Semiconductor’s 1-Wire protocol. The external power supply is required, extending the operating voltage range of the device below typical 1-Wire devices. DS2411 Silicon Serial Number with VCC Input www.maxim-ic.com

ABSOLUTE MAXIMUM RATINGS* I/O Voltage to GND -0.5V to +6V VCC Voltage to GND -0.5V to +6V I/O, VCC Current ±20mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDEC J-STD- 020A Specification /g42 This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. ELECTRICAL CHARACTERISTICS (VCC = 1.5V to 5.25V; TA = -40/g176C to +85/g176C.) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Operating Temperature T A (Note 1) -40 +85 /g176C Supply Voltage V CC (Note 1) 1.5 5.25 V 1-Wire Pullup V CC = VPUP (Note 1) 1.5 5.25 V I/O PIN GENERAL DATA 1-Wire Pullup Resistance R PUP (Notes 1, 2) 0.3 2.2 k/g87 Power-Up Delay t PWRP VCC stable to first 1-Wire command (Notes 1, 3) 1200 µs Input Capacitance C IO (Note 3) 100 pF Input Load Current I L 0V ≤ V(I/O) ≤ VCC -1 +1 µA Standby Supply Current I CCS V(I/O) ≤ VIL, or V(I/O) ≥ VIH 1 µA Active Supply Current I CCA 100 µA High-to-Low Switching Threshold VTL (Notes 3, 4, 5) 0.4 3.2 V Input Low Voltage V IL (Note 1) 0.30 V Input High Voltage V IH (Note 1) VCC - 0.3 V Low-to-High Switching Threshold VTH (Notes 3, 4, 6) 0.75 3.4 V Switching Hysteresis V HY (Notes 3, 7) 0.18 V Output Low Voltage at 4mA V OL (Note 8) 0.4 V Standard speed (Note 9, 3) 1.25 5Rising Edge Holdoff t REH Overdrive speed (Note 9, 3) 0.5 2 µs Standard speed, RPUP = 2.2k/g87 (Note 1) 5 Overdrive speed, RPUP = 2.2k/g87 (Note 1) 2Recovery Time t REC Overdrive speed, directly prior to reset pulse; RPUP = 2.2k/g87 (Note 1) 5 µs Standard speed 65 Overdrive VCC ≥ 2.2V 8Timeslot Duration t SLOT Overdrive VCC ≥ 1.5V 10 µs

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE Standard speed 480 640Reset Low Time t RSTL Overdrive speed 60 80 µs Standard speed 15 60 Overdrive VCC ≥ 2.2V 2 6Presence-Detect High Time t PDH Overdrive VCC ≥ 1.5V 2 8.5 µs Standard speed 60 240 Overdrive VCC ≥ 2.2V 8 24Presence-Detect Low Time t PDL Overdrive VCC ≥ 1.5V 8 30 µs Standard speed (Note 10, 3) 0.4 8Presence-Detect Fall Time t FPD Overdrive speed (Note 10, 3) 0.05 1 µs Standard speed (Note 1) 60 75 Overdrive VCC ≥ 2.2V (Note 1) 6 10Presence-Detect Sample Time tMSP Overdrive VCC ≥ 1.5V (Note 1) 8.5 10 µs I/O PIN, 1-Wire WRITE Standard speed (Notes 1, 13) 60 120 Overdrive VCC ≥ 2.2V (Notes 1, 13) 61 6Write-0 Low Time t W0L Overdrive VCC ≥ 1.5V (Notes 1, 13) 81 6 µs Standard speed (Notes 1, 11, 13) 5 15 - /g101Write-1 Low Time t W1L Overdrive speed (Notes 1, 11, 13) 1 2 - /g101µs I/O PIN, 1-Wire READ Standard speed (Notes 1, 11) 5 15 - /g101Read Low Time t RL Overdrive speed (Notes 1, 11) 1 2 - /g101µs Standard speed (Notes 1, 12) tRL + /g10015Read Sample Time t MSR Overdrive speed (Notes 1, 12) tRL + /g1002 µs Note 1: System requirement. Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2480B may be required. Minimum allowable pullup resistance is slightly great er than the value necessary to produce the absolute maximum current (20mA) during 1-Wire low times at V PUP = 5.25V assuming VOL = 0V. Note 3: Not production tested. Note 4: V TL and VTH are functions of VCC and temperature. Note 5: Voltage below which during a falling edge on I/O, a logic ‘0’ is detected. Note 6: Voltage above which during a rising edge on I/O, a logic ‘1’ is detected. Note 7: After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by V HY to be detected as logic ‘0’. Note 8: The I-V characteristic is linear for voltages less than 1V. Note 9: The earliest recognition of a negative edge is possible at t REH after V TH has been reached on the previous edge. Note 10: Interval during the negative edge on I/O at the beginning of a presence-detect pulse between the time at which the voltage is 90% of V PUP and the time at which the voltage is 10% of VPUP.

VIL to the input-high threshold of the bus master. when the voltage rises above VTH during a positive edge on I/O. may issue presence-detect pulses. hardware configuration, transaction sequence, and 1-Wire signaling (signal type and timing). the bus, as shown in Figure 4. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 15.4kbps in standard speed and 125kbps in overdrive. interpret the low as either a timeslot, or a reset depending on the duration. Figure 1. DS2411 REGISTRATION NUMBER

The communication sequence for accessing the DS2411 through the 1-Wire bus is as follows: /g167 Initialization /g167 ROM Function Command /g167 Read Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS2411 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the three ROM function commands. All ROM function command codes are 1 byte long. A list of these commands follows (see the flowchart in Figure 5). Read ROM [33h] This command allows the bus master to read the DS2411’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command should only be used if there is a single slave device on the bus. If more than one slave is present on the bus, a data collision results when all slaves try to transmit at the same time (open drain produces a wi red-AND result), and the resulting registration number read by the master will be invalid. Search ROM [F0h] When a system is initially brought up, the bus ma ster might not know the number of devices on the 1-Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimina tion to identify the registration numbe rs of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its registration number bit. On the second slot, each slav e device participating in the search outputs the complemented value of its registration number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the romcode tree. After one complete pass, the bus master knows the registration number of a single device. Add itional passes identify the registration numbers of the remainin g devices. Refer to App Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. Overdrive Skip ROM [3Ch] This command causes all overdrive-capable slave devices on the 1-Wire network to enter overdrive speed (OD = 1). All communication following this command has to occur at overdrive speed until a reset pulse of minimum 480/g109s duration resets all devices on the bus to regular speed (OD = 0). To subsequently address a specific overdrive-supporting device, a reset pulse at overdrive speed has to be issued followed by a read ROM or search ROM command sequence. Overdrive speeds up the time for the search process.

Figure 5. ROM FUNCTIONS FLOW CHART

The DS2411 requires strict protocols to ensure data integrity. The prot ocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, and Read Data. Except for the presence pulse the bus mast er initiates all these signals. The DS2411 can communicate at two different speeds: standard speed and Overdrive speed. If not explicitly set into the Overdrive mode, the DS2411 will comm unicate at standard speed. While in Overdrive Mode the fast timing applies to all waveforms. To get from idle to active, the voltage on the 1-Wire line needs to fall from V PUP below the threshold VTL. To get from active to idle, the voltage needs to rise from V ILMAX past the threshold V TH. The voltage VILMAX is relevant for the DS2411 when determining a logical level, but not for triggering any events. The initialization sequence required to begin any co mmunication with the DS2411 is shown in Figure 6. A Reset Pulse followed by a Presence Pulse indicate s the DS2411 is ready to receive data, given the correct ROM and memory function command. In a mixed population network, the reset low time t RSTL needs to be long enough for the slowest 1-Wire slav e device to recognize it as a reset pulse. If the bus master uses slew-rate control on the falling edge, it must pull down the line for t RSTL + tF to compensate for the edge. A t RSTL duration of 480 µs or longer will exit the Overdrive Mode returning the device to standard speed. If the DS2411 is in Overdrive Mode and t RSTL is no longer than 80 µs, the device will remain in Overdrive Mode. After the bus master has released the line it goes into receive mode (RX). Now, the 1-Wire bus is pulled to VPUP via the pullup resistor or, in case of a DS2480B driver, by active circuitry. When the threshold VTH is crossed, the DS2411 waits for t PDH and then transmits a Presence Pulse by pulling the line low for tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP. The tRSTH window must be at least the sum of t PDHMAX, tPDLMAX, and t RECMIN. Immediately after t RSTH is expired, the DS2411 is ready for data comm unication. In a mixed population network, t RSTH should be extended to minimum 480 µs at standard speed and 48 µs at Overdrive speed to accommodate other 1- Wire devices. Read/Write Time Slots Data communication with the DS2411 takes place in time slots that carry a single bit each. Write time slots transport data from bus master to slave. Read time-slots transfer data from slave to master. The definitions of the write and read time slots are illustrated in Figure 7. All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold V TL, the DS2411 starts its internal timing generator that determines when the data line will be sampled during a write time slot and how long data will be valid during a read time slot. Master to Slave For a write-one time slot, the voltage on the data line must have crossed the V THMAX threshold after the write-one low time t W1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the V THMIN threshold until the write-zero low time t W0LMIN is expired. For most reliable communication the voltage on the data line should not exceed V ILMAX during the entire t W0L window. After the VTHMAX threshold has been crossed, the DS2411 needs a recovery time tREC before it is ready for the next time slot.

A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTLMIN until the read low time t RL is expired. During the t RL window, when responding with a 0, the DS2411 will start pulling the data line low; its intern al timing generator determines when this pull-down ends and the voltage starts rising again. When responding with a 1, the DS2411 will not hold the data line low at all, and the voltage starts rising as soon as tRL is over. The sum of t RL + /g100 (rise rime) on one side and the internal timing generator of the DS2411 on the other side define the master sampling window (t MSRMIN to t MSRMAX) in which the master must perform a read from the data line. For most reliable communication, t RL should be as short as permissible and the master should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees sufficient recovery time t REC for the DS2411 to get ready for the next time slot. Improved Network Behavior In a 1-Wire environment, line ter mination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks therefore are suscep tible to noise of various origins. Depending on the physical size and topology of the network, reflec tions from end points and branch points can add up or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, as a conseque nce, result in a search ROM command coming to a dead end. For better performance in network app lications, the DS2411 uses a new 1-Wire front end, which makes it less sensitive to noise and also reduces the magnitude of noise injected by the slave device itself. The 1-Wire front end of the DS2411 differs from traditional slave devices in four characteristics. 1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line impedance than a digitally switched transistor, converting the high frequency ringing known from traditional devices into a smoother low-bandwidth transition. The slew rate control is specified by the parameter t FPD, which has different values for standard and Overdrive speed. 2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. As a consequence, the duration of the setup time t SU at standard speed is larger than with traditional devices. This additional filtering does not apply at Overdrive speed. 3) There is a hysteresis at the low-to-high switching threshold V TH. If a negative glitch crosses V TH but doesn’t go below VTH - VHY, it will not be recognized (Figure 8, Case A). The hysteresis is effective at any 1-Wire speed. 4) There is a time window specified by the rising edge hold-off time t REH during which glitches will be ignored, even if they extend below V TH - VHY threshold (Figure 8, Case B, t GL < tREH). Deep voltage droops or glitches that appear late after crossing the V TH threshold and extend beyond the t REH window cannot be filtered out and will be taken as beginning of a new time slot (Figure 8, Case C, tGL /g179 tREH). The duration of the hold-off time is independent of the 1-Wire speed. Only devices which have the parameters tFPD, VHY and tREH specified in their electrical characteristics use the improved 1-Wire front end.

NOISE SUPPRESSION SCHEME Figure 8 VPUP VTH VHY tREH tGL tREH tGL Case A Case CCase B CRC GENERATION To validate the registration number transmitted fro m the DS2411, the bus master can generate a CRC value from the 8-bit family code and unique 48-bit serial number as it is received. If the CRC matches the last 8 bits of the registration number, the transmission is error free. The equivalent polynomial function of this CRC is: CRC = x8 + x5 + x4 + 1. CUSTOM DS2411 Customization of a portion of the unique 48-bit serial number by the customer is available. Dallas Semiconductor will register and assign a specific customer ID in the 12 most significant bits of the 48-bit field. The next most significant bits are selectable by the customer as a starting value, and the least significant bits are non-selectable and will be auto matically incremented by one. Certain quantities and conditions apply for these custom parts. Contact your Maxim/Dalla s Semiconductor sales representative for more information.