DS2252T_06 DALLAS | Alldatasheet
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1 of 16 REV: 061306 GENERAL DESCRIPTION The DS2252T secure microcontroller module is an 8051-compatible micr ocontroller based on nonvolatile RAM technology. It is designed for systems that need to protect memory contents from disclosure. This in cludes key data, sensitive algorithms, and proprietary information of all types. Like other members of the secure microcontroller family, it provides full compatibility with th e 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the user can program, then reprogra m the microcontroller while in-system. This allows frequent changing of sensitive processes with minimal effort. PIN CONFIGURATION Operating information and detailed summary of this product’s security features are contained in the Secure Microcontroller User’s Guide. This data sheet provides ordering information, pinout, and electrical specifications.
FEATURES
8051-Compatible Microcontroller 8, 32, or 64kbytes of Nonvolatile SRAM for Program and/or Data Memory Storage In-System Programming via On-Chip Serial Port Capable of Modifying its Own Program and/or Data Memory in the End System Firmware Security Features Memory Stored in Encrypted Form Encryption Using On-Chip 64-Bit Key Automatic True Random Key Generator Self-Destruct Input (SDI) Improved Security Over Previous Generations Protects Memory Contents from Piracy Crashproof Operation Maintains All Nonvolatile Resources Up to
10 Years in the Absence of V
Early Warning Power-Fail Interrupt Watchdog Timer Precision Reference for Power Monitor Fully 8051 Compatible
128 Bytes Scratchpad RAM
32 Parallel I/O Port Pins
Permanently Powered Real-Time Clock
ORDERING INFORMATION
PART RAM SIZE (kB) MAX CRYSTAL SPEED (MHz) TIMEKEEPING? DS2252T-64-16 64 16 Yes DS2252T-64-16# 64 16 Yes DS2252T-128-16 128 16 Yes DS2252T-128-16# 128 16 Yes # Denotes RoHS-compliant device that may contain lead exempt under the RoHS requirements. DS2252T Soft Microcontroller Module www.maxim-ic.com 1 20 21 40 40-Pin SIMM DS2252T
The DS2252T provides an array of mechanisms to prev ent an attacker from examining the memory. It is designed to resist all levels of threat including obse rvation, analysis, and physical attack. As a result, a massive effort would be required to obtain any info rmation about memory contents. Furthermore, the “Soft” nature of the DS2252T allows frequent modification of secure information. This minimizes that value of any information that is obtained. Using a security system based on the DS5002FP, the DS2252T protects the memory contents from disclosure. It loads program memory via its serial por t and encrypts it in real time prior to storing it in SRAM. Once encrypted, the RAM contents and the progr am flow are unintelligible. The real data exists only inside the processor chip after being decrypted. Any attempt to discover the on-chip data, encryption keys, etc., results in its destruction. Extensive use of nonvolatile lithium-b acked technology creates a microcontroller that retains data for over 10 years at room temperature, but which can be erased instantly if tampered with. The DS2252T even interfaces directly to external tamper protection hardware. The DS2252T provides a permanently powered real time lock with inte rrupts for time stamp and date. It keeps time to one hundredth of a second using its onboard 32 kHz crystal. Like other Secure Microcontrollers in the family, the DS2252T provides crashproof operation in portable systems or systems with unreliable power. These featur es include the ability to save the operating state, Power-fail Reset, Power-fail Inte rrupt, and Watchdog Timer. All nonvolatile memory and resources are maintained for over 10 years at room temperature in the absence of power. A user loads programs into the DS2252T via its on- chip Serial Bootstrap Loader. This function supervises the loading of software into NV RAM, valid ates it, then becomes transparent to the user. It also manages the loading of new encryption keys automatically. Soft ware is stored in onboard CMOS SRAM. Using its internal Partit ioning, the DS2252T can divide a co mmon RAM into user selectable program and data segments. This Partition can be sele cted at program loading tim e, but can be modified anytime later. The microcontroller will decode memory access to the SRAM, access memory via its Byte- wide bus and write-protect the memory portion designated as program (ROM).
DS2252T BLOCK DIAGRAM Figure 1
PIN NAME PIN NAME PIN NAME PIN NAME 1 P1.0 11 P1.5 21 P3.1/TXD 31 P3.6/ WR 2 V CC 12 P0.4 22 ALE 32 P2.4 3 P1.1 13 P1.6 23 P3.2/ INT0 33 P3.7/ RD 4 P0.0 14 P0.5 24 PROG 34 P2.3 5 P1.2 15 P1.7 25 P3.3/ INT1 35 XTAL2 6 P0.1 16 P0.6 26 P2.7 36 P2.2 7 P1.3 17 RST 27 P3.4/T0 37 XTAL1 8 P0.2 18 P0.7 28 P2.6 38 P2.1 9 P1.4 19 P3.0/RXD 29 P3.5/T1 39 GND 10 P0.3 20 SDI 30 P2.5 40 P2.0 PIN DESCRIPTION PIN DESCRIPTION 4, 6, 8, 10, 12, 14, 16, P0.0 - P0.7. General purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data bus. When used in this mode, it does not require pullups. 1, 3, 5, 7, 9, 11, 13, 15 P1.0 - P1.7. General purpose I/O Port 1. 40, 38, 36, 34, 32, 30, 28, 26 P2.0 - P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address bus. 19 P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on board UART. This pin should NOT be connected directly to a PC COM port. 21 P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on board UART. This pin should NOT be connected directly to a PC COM port. P3.2 INT0 . General purpose I/O port pin 3.2. Also serves as the active low External Interrupt 0. This pin is also connected to the INTP output of the DS1283 Real Time Clock. 25 P3.3 INT1 . General purpose I/O port pin 3.3. Also serves as the active low External Interrupt 1. 31 P3.6 WR . General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation. 33 P3.7 RD . General purpose I/O port pin. Also serves as the read strobe for Expanded bus operation.
DS2252T MEMORY MAP IN NON-PARTITIONABLE MODE (PM = 1) Figure 2 DS2252T MEMORY MAP IN PARTITIONABLE (PM = 0) Figure 3 NV RAM PROGRAM NV RAM DATA PROGRAM MEMORY DATA MEMORY (MOVX) FFFFh -- 0000h -- -- 64K NV RAM PROGRAM NV RAM DATA PROGRAM MEMORY DATA MEMORY (MOVX) FFFFh -- 0000h -- PARTITION NOTE: PARTITIONABLE MODE IS NOT SUPPORTED ON THE 128KB VERSION OF THE DS2252T. LEGEND: = NV RAM MEMORY = EXPANDED BUS (PORTS 0 AND 2) = NOT AVAILABLE
DS2252T MEMORY MAP WITH (PES = 1) Figure 4 POWER MANAGEMENT The DS2252T monitors V CC to provide power-fail reset, early warning power-fail interrupt, and switchover to lithium backup. It uses an internal ba nd-gap reference in determining the switch points. These are called V PFW, VCCMIN, and V LI respectively. When V CC drops below V PFW, the DS2252T will perform an interrupt vector to locat ion 2Bh if the power-fail warning is enabled. Full processor operation continues regardless. When power falls further to V CCMIN, the DS2252T invokes a rese t state. No further code execution will be performed unless power rises back above V CCMIN. All decoded chip enables and the R/ W signal go to an inactive (logic 1) state. V CC is still the power source at this time. When V CC drops further to below V LI, internal circuitry will switch to the built-in lithium cell for power. The majority of internal circuits will be disabled and the remaining nonvol atile states will be retained. The Secure Microcontroller User’s Guide has more information on this topic. The trip points V CCMIN and VPFW are listed in the electrical specifications. NV RAM PROGRAM PROGRAM MEMORY DATA MEMORY (MOVX) FFFFh -- 0000h -- PARTITION = NOT ACCESSIBLE REAL-TIME CLOCK C000h -- B000h -- 4000h -- -- 64K -- 16K
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. Note 1: Storage temperature is defined as the temperature of the device when VCC = 0V and VLI = 0V. In this state the contents of SRAM are not battery-backed and are undefined. DC CHARACTERISTICS (VCC = 5V ±10%, TA = 0°C to +70°C.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Low Voltage V IL -0.3 +0.8 V 1 Input High Voltage V IH1 2.0 V CC+0.3 V 1 Input High Voltage (RST, XTAL1, PROG ) VIH2 3.5 V CC+0.3 V 1 Output Low Voltage at IOL = 1.6mA (Ports 1, 2, 3) VOL1 0.15 0.45 V 1 Output Low Voltage at IOL = 3.2mA (Ports 0, ALE) VOL2 0.15 0.45 V 1 Output High Voltage at IOH = -80µA (Ports 1, 2, 3) VOH1 2.4 4.8 V 1 Output High Voltage at IOH = -400µA (Ports 0, ALE) VOH2 2.4 4.8 V 1 Input Low Current VIN = 0.45V (Ports 1, 2, 3) IIL -50 µA Transition Current; 1 to 0 VIN = 2.0V (Ports 1, 2, 3) ITL -500 µA Input Leakage Current 0.45 < VIN < VCC (Port 0) IIL ±10 µA RST Pulldown Resistor R RE 40 150 kΩ Power-Fail Warning Voltage V PRW 4.25 4.37 4.50 V 1 Minimum Operating Voltage V CCMIN 4.00 4.12 4.25 V 1 Operating Current at 16MHz I CC 45 mA 4 Idle Mode Current at 12MHz I IDLE 7.0 mA 5 Stop Mode Current I STOP 80 µA 6 Pin Capacitance C IN 10 pF 7
DC CHARACTERISTICS (continued) (VCC = 5V ±10%, TA = 0°C to +70°C.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES With BAT = 3.0V 4.0 4.25 Reset Trip Point in Stop Mode With BAT = 3.3V 4.4 4.65 V 1 SDI Input High Voltage V IHS 2.0 V CC V 1, 2 SDI Input High Voltage V IHS 2.0 3.5 V 1, 2 SDI Pulldown Resistor R SDI 25 60 kΩ AC CHARACTERISTICS (VCC = 0V to 5V, TA = 0°C to +70°C.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES (4.5V < VCC < 5.5V) t SPR 2 SDI Pulse Reject (VCC = 0V, VBAT = 2.9V) 4 µs 10 (4.5V < VCC < 5.5V) t SPA 10 SDI Pulse Accept (VCC = 0V, VBAT = 2.9V) 50 µs 10
AC CHARACTERISTICS—EXPANDED BUS MODE TIMING SPECIFICATIONS (VCC = 5V ±10%, TA = 0°C to +70°C.) # PARAMETER SYMBOL MIN MAX UNITS 1 Oscillator Frequency 1/t CLK 1.0 16 (-16) MHz
2 ALE Pulse Width t ALPW 2tCLK - 40 ns
3 Address Valid to ALE Low t AVALL tCLK - 40 ns
4 Address Hold After ALE Low t AVAAV tCLK - 35 ns
14 RD Pulse Width tRDPW 6tCLK - 100 ns
15 WR Pulse Width tWRPW 6tCLK - 100 ns
At 12MHz 5t CLK - 165 16 RD Low to Valid Data In At 16MHz tRDLDV 5t CLK - 105 ns
17 Data Hold after RD High tRDHDV 0 ns
18 Data Float after RD High tRDHDZ 2t CLK - 70 ns
19 ALE Low to Valid Data In At 16MHz tALLVD
20 Valid Address to Valid Data
21 ALE Low to RD or WR Low tALLRDL 3tCLK - 50 3t CLK + 50 ns
22 Address Valid to RD or WR Low tAVRDL 4tCLK - 130 ns
23 Data Valid to WR Going Low tDVWRL tCLK - 60 ns
At 12MHz t DVWRH 7tCLK - 150 24 Data Valid to WR High At 16MHz 7t CLK - 90 ns
25 Data Valid after WR High tWRHDV tCLK - 50 ns
26 RD Low to Address Float tRDLAZ 0 ns
27 RD or WR High to ALE High tRDHALH tCLK - 40 t CLK + 50 ns
EXPANDED DATA MEMORY READ CYCLE
EXPANDED DATA MEMORY WRITE CYCLE
AC CHARACTERISTICS—EX TERNAL CLOCK DRIVE (VCC = 5V ±10%, TA = 0°C to +70°C.) # PARAMETER SYMBOL MIN MAX UNITS At 12MHz 20
28 External Clock High Time
29 External Clock Low Time
30 External Clock Rise Time
31 External Clock Fall Time
AC CHARACTERISTICS—PO WER CYCLE TIMING (VCC = 5V ±10%, TA = 0°C to +70°C.) # PARAMETER SYMBOL MIN MAX UNITS 32 Slew Rate from V CCMIN to 3.3V t F 130 µs
33 Crystal Startup Time t CSU (Note 8)
34 Power-On Reset Delay t POR 21,504 t CLK
AC CHARACTERISTICS—SERIAL PORT TIMING: MODE 0 (VCC = 5V ±10%, TA = 0°C to +70°C.) # PARAMETER SYMBOL MIN MAX UNITS
35 Serial Port Cl ock Cycle Time t SPCLK 12tCLK µs
36 Output Data Setup to Rising Clock Edge t DOCH 10tCLK - 133 ns
37 Output Data Hold after Rising Clock Edge t CHDO 2tCLK - 117 ns
38 Clock Rising Edge to Input Data Valid t CHDV 10t CLK - 133 ns
39 Input Data Hold afte r Rising Clock Edge t CHDIV 0 ns
SERIAL PORT TIMING: MODE 0 NOTES: 1. All voltage referenced to ground. 2. SDI should be taken to a logic high when V CC = +5V, and to approximately 3V when VCC < 3V. 3. SDI is deglitched to prevent accidental de struction. The pulse must be longer than t SPR to pass the deglitcher, but SDI is not guaranteed unless it is longer than tSPA. 4. Maximum operating I CC is measured with all output pins disconnected; XTAL1 driven with t CLKR, tCLKF=10 ns, VIL = 0.5V; XTAL2 disconnected; RST = PORT0 = VCC. 5. Idle mode I IDLE is measured with all output pins disconnected; XTAL1 driven with t CLKR, tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; PORT0 = VCC, RST = VSS. 6. Stop mode I STOP is measured with all output pins disconnected; PORT0 = V CC; XTAL2 not connected; RST = XTAL1 = VSS. 7. Pin capacitance is measured w ith a test frequency—1 MHz, T A = +25°C. 8. Crystal startup time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit un til the first clock pulse is produced by the on-chip oscillator. The user should check with the crystal vendor for a worst-case specification on this time.
A 2.645 2.655 B 2.379 2.389 C 0.995 1.005 D 0.395 0.405 E 0.245 0.255 F 0.050 BSC G 0.075 0.085 H 0.245 0.255 I 0.950 BSC J 0.120 0.130 K 1.320 1.330 L 1.445 1.455 M 0.057 0.067 N - 0.300 O - 0.165 P 0.047 0.054
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2006 Maxim Integrated Products • Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. DATA SHEET REVISION SUMMARY The following represent the key differences between 12/13/95 and 08/16/96 version of the DS2252T data sheet. Please review this summary carefully. 1. Change V CC slew rate specification to reference 3.3V instead of VLI. 2. Add minimum value to PCB thickness. The following represent the key differences between 08/16/96 and 05/28/97 version of the DS2252T data sheet. Please review this summary carefully. 1. AC characteristics for battery-b acked SDI pulse specification added. The following represent the key differences between 05/28/97 and 11/08/99 version of the DS2252T data sheet. Please review this summary carefully. (PCN I80903) 1. Correct Absolute Maximum Ratings to re flect changes to DS5002FP microprocessor. 2. Add note clarifying that SRAM contents are not defined under storage temperature conditions. The following represent the key differences between 11/08/99 and 01/18/00 version of the DS2252T data sheet. Please review this summary carefully. 1. Data sheet conversion from Interleaf to Word. The following represent the key differences between 01/18/00 and 06/13/06 version of the DS2252T data sheet. Please review this summary carefully. 1. Updated reference in Features (Crashproof Operation) to 10-year NV RAM data life to include room temperature caveat. 2. Added RoHS-compliant packages to Ordering Information table. 3. Replaced references to “Secure Microcontrolle r Data Book” with “Secure Microcontroller User’s Guide.”