DS2252T-128-16

DS2252T_1 DALLAS | Alldatasheet

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Technical content

Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. DS2252T Secure Microcontroller Module DS2252T 121395 1/14

FEATURES

• 8051 compatible microcontroller for secure/sensitive

applications

– 32K, 64K, or 128K bytes of nonvolatile SRAM for program and/or data storage – In–system programming via on–chip serial port – Capable of modifying its own program or data memory in the end system

• Firmware Security Features: – Memory stored in encrypted form – Encryption using on–chip 64–bit key – Automatic true random key generator – SDI Self Destruct Input – Improved security over previous generations – Protects memory contents from piracy
• Crashproof Operation – Maintains all nonvolatile resources for over 10 years in the absence of power – Power–fail Reset – Early Warning Power–fail Interrupt – Watchdog Timer – Precision reference for power monitor
• Fully 8051 Compatible – 128 bytes scratchpad RAM – Two timer/counters – On–chip serial port – 32 parallel I/O port pins
• Permanently powered real time clock PACKAGE OUTLINE 40-Pin SIMM 12 0 2 1 4 0

DESCRIPTION

The DS2252T is an 8051 compatible microcontroller based on nonvolatile RAM technology. It is designed for systems that need to protect memory contents from dis- closure. This includes key data, sensitive algorithms, and proprietary information of all types. Like other mem- bers of the Secure Microcontroller family, it provides full compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NVRAM instead of ROM, the user can program, then reprogram the micro- controller while in–system. This allows frequent chang- ing of sensitive processes with minimal effort. The DS2252T provides an array of mechanisms to prevent an attacker from examining the memory. It is designed to resist all levels of threat including observation, analy- sis, and physical attack. As a result, a massive effort would be required to obtain any information about memory contents. Furthermore, the “Soft” nature of the DS2252T allows frequent modification of secure information. This minimizes that value of any informa- tion that is obtained.

Using a security system based on the DS5002FP, the DS2252T protects the memory contents from disclo- sure. It loads program memory via its serial port and encrypts it in real–time prior to storing it in SRAM. Once encrypted, the RAM contents and the program flow are unintelligible. The real data exists only inside the pro- cessor chip after being decrypted. Any attempt to dis- cover the on–chip data, encryption keys, etc., results in its destruction. Extensive use of nonvolatile lithium backed technology create a microcontroller that retains data for over 10 years at room temperature, but which can be erased instantly if tampered with. The DS2252T even interfaces directly to external tamper protection hardware. The DS2252T provides a permanently powered real time lock with interrupts for time stamp and date. It keeps time to one hundredth of a second using its on– board 32 KHz crystal. Like other Secure Microcontrollers in the family, the DS2252T provides crashproof operation in portable systems or systems with unreliable power. These fea- tures include the ability to save the operating state, Power–fail Reset, Power–fail Interrupt, and Watchdog Timer. All nonvolatile memory and resources are main- tained for over 10 years at room temperature in the absence of power. A user loads programs into the DS2252T via its on–chip Serial Bootstrap Loader. This function supervises the loading of software into NVRAM, validates it, then becomes transparent to the user. It also manages the loading of new encryption keys automatically. Software is stored in on–board CMOS SRAM. Using its internal Partitioning, the DS2252T can divide a common RAM into user selectable program and data segments. This Partition can be selected at program loading time, but can be modified anytime later. The microcontroller will decode memory access to the SRAM, access memory via its Byte–wide bus and write–protect the memory por- tion designated as program (ROM). A detailed summary of the security features is provided in the User’s Guide section of the Secure Microcontrol- ler data book. An overview is also available in the DS5002FP data sheet.

ORDERING INFORMATION

PART NUMBER RAM SIZE MAX CRYSTAL SPEED TIMEKEEPING? DS2252T–32–16 32K bytes 16 MHz Yes DS2252T–64–16 64K bytes 16 MHz Yes DS2252T–128–16 128K bytes 16 MHz Yes Operating information is contained in the User’s Guide section of the Secure Microcontroller Data Book. This data sheet provides ordering information, pinout, and electrical specifications.

DS2252T BLOCK DIAGRAM Figure 1 ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ P0.0–0.7 P1.0–1.7 P2.0–2.7 P3.0–3.7 RST ALE XTAL1 XTAL2 GND PROG SDI VCC DS5002FP ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏ VCCO CE1 R/W CE2 BYTE–WIDE DATA BUS BYTE–WIDE ADDRESS BUS +3V 32K OR 128K SRAM DS1283 REAL TIME CLOCK DS2252T 32K SRAM (–64 only) PE1 P3.2 INTP

1 P1.0 11 P1.5 21 P3.1 TXD 31 P3.6 WR 2V CC 12 P0.4 22 ALE 32 P2.4 3 P1.1 13 P1.6 23 P3.2 INT0 33 P3.7 RD 4 P0.0 14 P0.5 24 PROG 34 P2.3 5 P1.2 15 P1.7 25 P3.3 INT1 35 XTAL2 6 P0.1 16 P0.6 26 P2.7 36 P2.2 7 P1.3 17 RST 27 P3.4 T0 37 XTAL1 8 P0.2 18 P0.7 28 P2.6 38 P2.1 9 P1.4 19 P3.0 RXD 29 P3.5 T1 39 GND 10 P0.3 20 SDI 30 P2.5 40 P2.0 PIN DESCRIPTION PIN DESCRIPTION 4, 6, 8, 10, 12, 14, 16, 18 It requires external pull–ups. Port 0 is also the multiplexed Expanded Address/Data bus. When used in this mode, it does not require pull–ups. 1, 3, 5, 7, 9, 11, 13, 15 P1.0 – P1.7. General purpose I/O Port 1. 40, 38, 36, 34, 32, 30, 28, 26 P2.0 – P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address bus. 19 P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on board UART. This pin should NOT be connected directly to a PC COM port. 21 P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on board UART. This pin should NOT be connected directly to a PC COM port. 23 P3.2 INT0. General purpose I/O port pin 3.2. Also serves as the active low External Interrupt 0. This pin is also connected to the INTP output of the DS1283 Real Time Clock. 25 P3.3 INT1. General purpose I/O port pin 3.3. Also serves as the active low External Interrupt 1. 31 P3.6 WR. General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation. 33 P3.7 RD. General purpose I/O port pin. Also serves as the read strobe for Expanded bus operation. 17 RST – Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally, can be left unconnected if not used. An RC power–on reset circuit is not needed and is NOT recommended. 22 ALE – Address Latch Enable. Used to de–multiplex the multiplexed Expanded Address/Data bus on Port 0. This pin is normally connected to the clock input on a ’373 type transparent latch.

DS2252T MEMORY MAP IN NON–PARTITIONABLE MODE (PM=1) Figure 2 ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ DATA MEMORY (MOVX) 64K NVRAM DATA ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ ÉÉÉÉÉÉ PROGRAM MEMORY NVRAM PROGRAM FFFFh 0000h DS2252T MEMORY MAP IN PARTITIONABLE MODE (PM=0) Figure 3 ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ FFFFh 0000h ÉÉ ÉÉ = NVRAM MEMORY LEGEND: ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ NVRAM DATA ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ ÉÉÉÉÉ NVRAM PROGRAM PARTITION ÎÎ ÎÎ PROGRAM MEMORY EXPANDED BUS (PORTS 0 AND 2) NOT AVAILABLE DATA MEMORY (MOVX) NOTE: PARTITIONABLE MODE IS NOT SUPPORTED ON THE 128KB VERSION OF THE DS2252T.

DS2252T MEMORY MAP WITH (PES=1) Figure 4 ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ DATA MEMORY (MOVX) 64K 16K REAL–TIME CLOCK ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎ PROGRAM MEMORY NVRAM PROGRAM FFFFh C000h 8000h 4000h 0000h PARTITION ÎÎ ÎÎ NOT ACCESSIBLE POWER MANAGEMENT The DS2252T monitors VCC to provide Power–fail Reset, early warning Power–fail Interrupt, and switch over to lithium backup. It uses an internal band–gap ref- erence in determining the switch points. These are called VPFW , VCCMIN , and VLI respectively. When VCC drops below VPFW , the DS2252T will perform an inter- rupt vector to location 2Bh if the power fail warning was enabled. Full processor operation continues regard- less. When power falls further to VCCMIN , the DS2252T invokes a reset state. No further code execution will be performed unless power rises back above VCCMIN . All decoded chip enables and the R/W signal go to an inac- tive (logic 1) state. VCC is still the power source at this time. When VCC drops further to below VLI, internal cir- cuitry will switch to the built–in lithium cell for power. The majority of internal circuits will be disabled and the remaining nonvolatile states will be retained. The User’s Guide has more information on this topic. The trip points V CCMIN and VPFW are listed in the electrical spec- ifications.

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground –0.3V to +7.0V Operating Temperature 0 °C to 70°C Storage Temperature –40 °C to +70°C Soldering Temperature 260 °C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC CHARACTERISTICS (tA=0°C to 70°C; VCC =5V ± 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Low Voltage VIL –0.3 +0.8 V 1 Input High Voltage VIH1 2.0 VCC +0.3 V 1 Input High Voltage (RST, XTAL1, PROG ) VIH2 3.5 VCC +0.3 V 1 Output Low Voltage @ I OL =1.6 mA (Ports 1, 2, 3) VOL1 0.15 0.45 V 1 Output Low Voltage @ I OL =3.2 mA (Ports 0, ALE) VOL2 0.15 0.45 V 1 Output High Voltage @ I OH =–80 µA (Ports 1, 2, 3) VOH1 2.4 4.8 V 1 Output High Voltage @ IOH =–400 µA (Ports 0, ALE) VOH2 2.4 4.8 V 1 Input Low Current VIN=0.45V (Ports 1, 2, 3) IIL –50 µA Transition Current; 1 to 0 VIN=2.0V (Ports 1, 2, 3) ITL –500 µA Input Leakage Current 0.45<VIN<VCC (Port 0) IIL ±10 µA RST Pulldown Resistor R RE 40 150 KΩ Power Fail Warning Voltage VPRW 4.25 4.37 4.50 V 1 Minimum Operating Voltage VCCMIN 4.00 4.12 4.25 V 1 Operating Current @ 16 MHz ICC 45 mA 4 Idle Mode Current @ 12 MHz IIDLE 7.0 mA 5 Stop Mode current ISTOP 80 µA 6 Pin Capacitance C IN 10 pF 7 Reset Trip Point in Stop Mode w/BAT=3.0V w/BAT=3.3V 4.0 4.4 4.25 4.65 V 1 SDI Input Low Voltage VILS 0.4 V 1 SDI Input High Voltage VIHS 2.0 VCC V 1, 2 SDI Input High Voltage VIHS 2.0 3.5 V 1, 2 SDI Pull–Down Resistor R SDI 25 60 KΩ

AC CHARACTERISTICS (tA = 0°C to70°C; VCC =0V to 5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES SDI Pulse Reject tSPR 2 µs 3 SDI Pulse Accept tSPA 10 µs 3 AC CHARACTERISTICS EXPANDED BUS MODE TIMING SPECIFICATIONS (tA = 0°C to70°C; VCC = 5V + 10%) # PARAMETER SYMBOL MIN MAX UNITS 1 Oscillator Frequency 1/tCLK 1.0 16 (–16) MHz

2 ALE Pulse Width tALPW 2tCLK –40 ns

3 Address Valid to ALE Low tAVALL tCLK –40 ns

4 Address Hold After ALE Low tAVAAV tCLK –35 ns

14 RD Pulse Width tRDPW 6tCLK –100 ns

15 WR Pulse Width tWRPW 6tCLK –100 ns

16 RD Low to Valid Data In @12 MHz

@16 MHz tRDLDV 5tCLK –165 5tCLK –105 ns ns

17 Data Hold after RD High tRDHDV 0 ns

18 Data Float after RD High tRDHDZ 2tCLK –70 ns

19 ALE Low to Valid Data In @12 MHz

@16 MHz tALLVD 8tCLK –150 8tCLK –90 ns ns 20 Valid Addr. to Valid Data In @12 MHz @16 MHz tAVDV 9tCLK –165 9tCLK –105 ns ns

21 ALE Low to RD or WR Low tALLRDL 3tCLK –50 3tCLK +50 ns

22 Address Valid to RD or WR Low tAVRDL 4tCLK –130 ns

23 Data Valid to WR Going Low tDVWRL tCLK –60 ns

24 Data Valid to WR High @12 MHz

@16 MHz tDVWRH 7tCLK –150 7tCLK –90 ns ns

25 Data Valid after WR High tWRHDV tCLK –50 ns

26 RD Low to Address Float tRDLAZ 0 ns

27 RD or WR High to ALE High tRDHALH tCLK –40 tCLK +50 ns

EXPANDED DATA MEMORY READ CYCLE 21 14 ALE PORT 0 PORT 2 P2.7–P2.0 OR A15–A8 FROM DPH A15–A8 FROM PCH DATA IN INSTR IN A7–A0 (PCL) A7–A0 (Rn OR DPL) RD EXPANDED DATA MEMORY WRITE CYCLE 3 4 24 ALE PORT 0 PORT 2 WR DATA OUTA7–A0 (Rn OR DPL) A7–A0 (PCL) INSTR IN P2.7–P2.0 OR A15–A8 FROM DPH A15–A8 FROM PCH

AC CHARACTERISTICS (cont’d) EXTERNAL CLOCK DRIVE (tA = 0°C to70°C; VCC = 5V + 10%) # PARAMETER SYMBOL MIN MAX UNITS

28 External Clock High Time @12 MHz

@16 MHz tCLKHPW 20 ns ns

29 External Clock Low Time @12 MHz

@16 MHz tCLKLPW 20 ns ns

30 External Clock Rise Time @12 MHz

@16 MHz tCLKR 20 ns ns

31 External Clock Fall Time @12 MHz

@16 MHz tCLKF 20 ns ns EXTERNAL CLOCK TIMING AC CHARACTERISTICS (cont’d) POWER CYCLING TIMING (tA = 0°C to70°C; VCC = 5V + 10%) # PARAMETER SYMBOL MIN MAX UNITS

32 Slew Rate from VCCMIN to VLI tF 130 µs

33 Crystal Start up Time tCSU (note 8)

34 Power On Reset Delay tPOR 21504 tCLK

AC CHARACTERISTICS (cont’d) SERIAL PORT TIMING – MODE 0 (tA = 0°C to70°C; VCC = 5V + 10%) # PARAMETER SYMBOL MIN MAX UNITS

35 Serial Port Clock Cycle Time tSPCLK 12tCLK µs

36 Output Data Setup to Rising Clock Edge tDOCH 10tCLK –133 ns

37 Output Data Hold after Rising Clock EdgetCHDO 2tCLK –117 ns

38 Clock Rising Edge to Input Data Valid tCHDV 10tCLK –133 ns

39 Input Data Hold after Rising Clock EdgetCHDIV 0 ns

SERIAL PORT TIMING – MODE 0 INSTRUCTION 01 2 3 4 5 6 7 8 ALE CLOCK DATA OUT INPUT DATA 01 2 3 4 5 6 7 SET TI SET RI VALID VALIDVALIDVALIDVALIDVALIDVALID CLEAR RI WRITE TO SBUF REGISTER NOTES: 1. All voltage referenced to ground. 2. SDI should be taken to a logic high when VCC =+5V, and to approximately 3V when VCC <3V. 3. SDI is deglitched to prevent accidental destruction. The pulse must be longer than tSPR to pass the deglitch- er, but SDI is not guaranteed unless it is longer than tSPA . 4. Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR , tCLKF =10 ns, VIL = 0.5V; XTAL2 disconnected; RST = PORT0 = VCC . 5. Idle mode IIDLE is measured with all output pins disconnected; XTAL1 driven with tCLKR , tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; PORT0 = VCC , RST = VSS . 6. Stop mode ISTOP is measured with all output pins disconnected; PORT0 = VCC ; XTAL2 not connected; RST = XTAL1 = VSS . 7. Pin capacitance is measured with a test frequency – 1 MHz, tA = 25°C. 8. Crystal start–up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on–chip oscillator. The user should check with the crystal vendor for a worst case specification on this time.

F (SIDE A) (SIDE B) A C G CL D E I I K L H M J O N P (SIDE B) U1B U1A U3 U2 DS2252T 121395 14/14 PACKAGE DRAWING PKG 40–PIN DIM MIN MAX A 2.645 2.655 B 2.379 2.389 C 0.995 1.005 D 0.395 0.405 E 0.245 0.255 F 0.050 BSC G 0.075 0.085 H 0.245 0.255 I 0.950 BSC J 0.120 0.130 K 1.320 1.330 L 1.445 1.455 M 0.057 0.067 N – 0.300 O – 0.165 P – 0.054