DS2251T-128-16

DS2251 DALLAS | Alldatasheet

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Technical content

FEATURES

/elevenoclock 8051-compatible microcontroller adapts to its task - 32K, 64K, or 128K bytes of nonvolatile SRAM for program and/or data storage - In-system programming via on-chip serial port - Capable of modifying its own program or data memory in the end system - Provides separate Byte-wide bus for peripherals - Performs CRC-16 check of NV RAM memory /elevenoclock High-reliability operation - Maintains all nonvolatile resources for over 10 years in the absence of power - Power-fail reset - Early Warning Power-fail Interrupt - Watchdog Timer - Lithium backed memory remembers system state - Precision reference for power monitor /elevenoclock Fully 8051-compatible - 128 bytes scratchpad RAM - Two timer/counters - On-chip serial port - 32 parallel I/O port pins /elevenoclock Permanently powered real time clock PIN ASSIGNMENT

DESCRIPTION

The DS2251T 128k Soft Microcontroller Module is an 8051-compatible microcontroller module based on nonvolatile RAM technology. It is designed for systems that need large quantities of nonvolatile memory. Like other members of the Secure Microcontroller family, it provides full compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the user can program, then reprogram the microcontroller while in-system. The application software can even change its own operation. This allows frequent software upgrades, adaptive programs, customized systems, etc. In addition, by using NV RAM, the DS2251T is ideal for data logging applications. The powerful real time clock includes interrupts for time stamp and date. It keeps time to one-hundredth of seconds using its onboard 32 kHz crystal. DS2251(T) 128k Soft Microcontroller Module www.dalsemi.com 72 1 72-Pin SIMM

The DS2251T provides the benefits of NV RAM without using I/O resources. Between 32 kbytes and 128 kbytes of onboard NV RAM are available. A non-multiplexed Byte-wide address and data bus is used for memory access. This bus, which is available at the connector, can perform all memory access and also provide decoded chip enables for off-board memory mapped peripherals. This leaves the 32 I/O port pins free for application use. The DS2251T provides high-reliability operation in portable systems or systems with unreliable power. These features include the ability to save the operating state, Power-fail Reset, Power-fail Interrupt, and Watchdog Timer. All nonvolatile memory and resources are maintained for over 10 years at room temperature in the absence of power. A user loads programs into the DS2251T via its on-chip serial Bootstrap loader. This function supervises the loading of software into NV RAM, validates it, then becomes transparent to the user. Software is stored in onboard CMOS SRAM. Using its internal Partitioning, the DS2251T can divide a common RAM into user-selectable program and data segments. This Partition can be selected at program loading time, but can be modified anytime later. The microprocessor will decode memory access to the SRAM, access memory via its Byte-wide bus and write-protect the memory portion designated as program (ROM).

ORDERING INFORMATION

PART NUMBER RAM SIZE MAX CRYSTAL SPEED TIMEKEEPING? DS2251T-32-16 32 kbytes 16 MHz Yes DS2251T-64-16 64 kbytes 16 MHz Yes DS2251T-128-16 128 kbytes 16 MHz Yes Operating information is contained in the User’s Guide section of the Secure Microcontroller Data Book. This data sheet provides ordering information, pinout, and electrical specifications.

DS2251(T) BLOCK DIAGRAM Figure 1

1 P1.0 19 XTAL2 37 P0.2 55 INTB 2 P1.1 20 GND 38 P0.1 56 BD0 3 P1.2 21 P2.0 39 P0.0 57 BD1 4 P1.3 22 P2.1 40 V CC 58 BD2 5 P1.4 23 P2.2 41 BA0 59 BD3 6 P1.5 24 P2.3 42 BA1 60 BD4 7 P1.6 25 P2.4 43 BA2 61 BD5 8 P1.7 26 P2.5 44 BA3 62 BD6 9 RST 27 P2.6 45 BA4 63 BD7 10 P3.0 RXD 28 P2.7 46 BA5 64 R/ W 11 P3.1 TXD 29 PSEN 47 BA6 65 PF 12 P3.2 INT0 30 ALE 48 BA7 66 PE3 13 P3.3 INT1 31 PROG 49 BA8 67 PE4 14 P3.4 T0 32 P0.7 50 BA9 68 INTP 15 P3.5 T1 33 P0.6 51 BA10 69 INTA 16 P3.6 WR 34 P0.5 52 BA11 70 SQW 17 P3.7 RD 35 P0.4 53 BA12 71 VRST 18 XTAL1 36 P0.3 54 BA13 72 BA15 PIN DESCRIPTION PIN DESCRIPTION It requires external pullups. Port 0 is also the multiplexed Expanded Address/Data bus. When used in this mode, it does not require pullups. 1-8 P1.0 - P1.7. General purpose I/O Port 1. 21-28 P2.0 - P2.7. General purpose I/O Port 2. Also serves as the MSB of the Expanded Address bus. 10 P3.0 RXD. General purpose I/O port pin 3.0. Also serves as the receive signal for the on- board UART. This pin should NOT be connected directly to a PC COM port. 11 P3.1 TXD. General purpose I/O port pin 3.1. Also serves as the transmit signal for the on- board UART. This pin should NOT be connected directly to a PC COM port. 12 P3.2 INT0 . General purpose I/O port pin 3.2. Also serves as the active low External Interrupt 0. 13 P3.3 INT1 . General purpose I/O port pin 3.3. Also serves as the active low External Interrupt 1.

16 P3.6 WR . General purpose I/O port pin. Also serves as the write strobe for Expanded bus operation. 17 P3.7 RD . General purpose I/O port pin. Also serves as the read strobe for Expanded bus operation. 9 RST - Active high reset input. A logic 1 applied to this pin will activate a reset state. This pin is pulled down internally, can be left unconnected if not used. An RC power-on reset circuit is not needed and is NOT recommended. 29 PSEN - Program Store Enable. This active low signal is used to enable an external program memory when using the Expanded bus. It is normally an output and should be unconnected if not used. 30 ALE - Address Latch Enable. Used to de-multiplex the multiplexed Expanded Address/Data bus on Port 0. This pin is normally connected to the clock input on a ‘373 type transparent latch. 19, 18 XTAL2, XTAL1. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output. 20 GND - Logic ground. 40 VCC - +5V. 72 BA15 - Monitor test point to reflect the logical value of A15. Not needed for memory access. 54-41 BA13 - 0. Byte-wide Address bus bits 13-0. This bus is combined with the non-multiplexed data bus (BD7-0) to access onboard NV SRAM and off-board peripherals. Peripheral decoding is performed using PE3 and PE4 . These are on 16k boundaries, so BA14 or BA15 are not needed. Read/write access is controlled by R/ W . BA13-0 connect directly to memory mapped peripherals. 63-56 BD7 - 0. Byte-wide Data bus bits 7-0. This 8-bit bi-directional bus is combined with the non-multiplexed address bus (BA14-0) to access on-board NV SRAM and off-board peripherals. 64 R/ W - Read/Write. This signal provides the write enable to the SRAMs on the Byte-wide bus. It is controlled by the memory map and Partition. The blocks selected as Program (ROM) will be write-protected. This signal is also used for the write enable to off-board peripherals. 66 PE3 - Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when the PES bit is set to a logic 1. PE3 is not lithium backed and can be connected to any type of peripheral function. 67 PE4 - Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when the PES bit is set to a logic 1. PE4 is not lithium backed and can be connected to any type of peripheral function. 31 PROG - Invokes the Bootstrap loader on a falling edge. This signal should be debounced so that only one edge is detected. If connected to ground, the micro will enter Bootstrap loading on power-up. This signal is pulled up internally.

71 VRST - This I/O pin (open-drain with internal pullup) indicates that the power supply (VCC)

has fallen below the V CCMIN level and the micro is in a reset state. When this occurs, the DS2251T will drive this pin to a logic 0. Because the micro is lithium backed, this signal is guaranteed even when V CC=0V. Because it is an I/O pin, it will also force a reset if pulled low externally. This allows multiple parts to synchronize their power-down resets. 65 PF - This output goes to a logic 0 to indicate that the micro has switched to lithium backup. It corresponds to V CC < VLI. Because the micro is lithium backed, this signal is guaranteed even when VCC=0V. 55 INTB - INTB from the real time clock. This output may be connected to a micro interrupt input. 68 INTP - INTP from the real time clock. This open-drain output requires a pullup and may be connected to a micro interrupt input. 69 INTA - INTA from the real time clock. This output may be connected to a micro interrupt input. 70 SQW - SQW output from the DS1283 Real Time Clock. Can be programmed to output an 1024 Hz square wave. INSTRUCTION SET The DS2251T executes an instruction set that is object code compatible with the industry standard 8051 microcontroller. As a result, software development packages such as assemblers and compilers that have been written for the 8051 are compatible with the DS2251T. A complete description of the instruction set and operation are provided in the User’s Guide section of the Secure Microcontroller Data Book. MEMORY ORGANIZATION Figure 2 illustrates the memory map accessed by the DS2251T. The entire 64k of program and 64k of data are available to the Byte-wide bus. This preserves the I/O ports for application use. The user controls the portion of memory that is actually mapped to the Byte-wide bus by selecting the Program Range and Data Range. Any area not mapped into the NV RAM is reached via the Expanded bus on Ports 0 and 2. An alternate configuration allows dynamic Partitioning of a 64k space as shown in Figure 3. Selecting PES=1 provides access to the real time clock on the DS2251T and enables PE3 and PE4 for peripheral access as shown in Figure 4. These selections are made using Special Function Registers. The memory map and its controls are covered in detail in the User’s Guide section of the Secure Microcontroller Data Book.

DS2251T MEMORY MAP IN NON-PARTITIONABLE MODE (PM=1) Figure 2 DS2251T MEMORY MAP IN PARTITIONABLE MODE (PM=0) Figure 3

DS2251T MEMORY MAP WITH (PES=1) Figure 4 POWER MANAGEMENT The DS2251T monitors VCC to provide Power-fail Reset, early warning Power-fail Interrupt, and switch- over to lithium backup. It uses an internal band-gap reference in determining the switch points. These are called V PFW, VCCMIN, and V LI respectively. When V CC drops below V PFW, the DS2251T will perform an interrupt vector to location 2Bh if the power-fail warning is enabled. Full processor operation continues regardless. When power falls further to V CCMIN, the DS2251T invokes a reset state. No further code execution will be performed unless power rises back above V CCMIN. All decoded chip enables and the R/ W signal go to an inactive (logic 1) state. The VRST signal will be driven to a logic 0. V CC is still the power source at this time. When VCC drops further to below VLI, internal circuitry will switch to the built- in lithium cell for power. The majority of internal circuits will be disabled and the remaining nonvolatile states will be retained. PF will be driven to a logic 0. The User’s Guide has more information on this topic. The trip points VCCMIN and VPFW are listed in the electrical specifications.

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to (V CC + 0.5V) Voltage on VCC Relative to Ground -0.3V to +6.0V Operating Temperature -40°C to +85°C Storage Temperature 2 -55°C to +125°C Soldering Temperature 260°C for 10 seconds 1This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. 2Storage temperature is defined as the temperature of the device when V CC=0V and VLI=0V. In this state the contents of SRAM are not battery-backed and are undefined. DC CHARACTERISTICS (tA=0˚C to70˚C; VCC=5V ± 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Low Voltage V IL -0.3 +0.8 V 1 Input High Voltage V IH1 2.0 V CC+0.3 V 1 Input High Voltage RST, XTAL1 PROG VIH2 3.5 V CC+0.3 V 1 Output Low Voltage @ IOL=1.6 mA (Ports 1, 2, 3, PF ) VOL1 0.15 0.45 V 1, 7 Output Low Voltage @ IOL=3.2 mA (Ports 0, ALE, PSEN , BA13-0, BD7-0, R/ W , PE 3-4) VOL2 0.15 0.45 V 1 Output High Voltage @ IOH= -80 µA (Ports 1, 2, 3) VOH1 2.4 4.8 V 1 Output High Voltage @ IOH=-400 µA (Ports 0, ALE, PSEN , PF , BA13-0, BD7-0, R/ W , PE 3-4) VOH2 2.4 4.8 V 1 Input Low Current VIN = 0.45V (Ports 1, 2, 3) IIL -50 µA Transition Current; 1 to 0 VIN = 2.0V (Ports 1, 2, 3) ITL -500 µA Input Leakage Current 0.45 < VIN < VCC (Port 0) IIL ±10 µA RST Pulldown Resistor R RE 40 150 kΩ VRST Pullup Resistor RVR 4.7 kΩ PROG Pullup Resistor RPR 40 kΩ Power-Fail Warning Voltage V PFW 4.25 4.37 4.50 V 1 Minimum Operating Voltage V CCmin 4.00 4.12 4.25 V 1 Operating Current @ 16 MHz I CC 45 mA 2 Idle Mode Current @ 12 MHz I IDLE 7.0 mA 3 Stop Mode Current I STOP 80 µA 4

PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Pin Capacitance C IN 10 pF 5 Reset Trip Point in Stop Mode w/BAT=3.0V w/BAT=3.3V 4.0 4.4 4.25 4.65 AC CHARACTERISTICS: EXPANDED BUS MODE TIMING SPECIFICATIONS (tA=0˚C to70˚C; VCC=5V ± 10%) # PARAMETER SYMBOL MIN MAX UNITS 1 Oscillator Frequency 1/t CLK 1.0 16 (-16) MHz

2 ALE Pulse Width t ALPW 2tCLK -40 ns

3 Address Valid to ALE Low t AVALL tCLK -40 ns

4 Address Hold After ALE Low t AVAAV tCLK -35 ns

5 ALE Low to Valid Instr. In @ 12 MHz @ 16 MHz tALLVI 4tCLK -150 4tCLK -90 ns

6 ALE Low to PSEN Low tALLPSL tCLK -25 ns

7 PSEN Pulse Width tPSPW 3tCLK -35 ns

8 PSEN Low to Valid Instr. In @ 12 MHz @ 16 MHz tPSLVI 3tCLK -150 3tCLK -90 ns ns 9 Input Instr. Hold after PSEN Going High tPSIV 0n s 10 Input Instr. Float after PSEN Going High tPSIX tCLK -20 ns

11 Address Hold after PSEN Going High tPSAV tCLK -8 ns

12 Address Valid to Valid Instr. In @ 12 MHz @ 16 MHz tAVVI 5tCLK -150 5tCLK -90 ns ns

13 PSEN Low to Address Float tPSLAZ 0n s

14 RD Pulse Width tRDPW 6tCLK -100 ns

15 WR Pulse Width tWRPW 6tCLK -100 ns

16 RD Low to Valid Data In @ 12 MHz

@ 16 MHz tRDLDV 5tCLK -165 5tCLK -105 ns ns

17 Data Hold after RD High tRDHDV 0n s

18 Data Float after RD High tRDHDZ 2tCLK -70 ns

19 ALE Low to Valid Data In @ 12 MHz

@ 16 MHz tALLVD 8CLK -150 8tCLK -90 ns ns 20 Valid Addr. to Valid Data In @ 12 MHz @ 16 MHz tAVDV 9tCLK -165 9tCLK -105 ns ns

21 ALE Low to RD or WR Low tALLRDL 3tCLK -50 3t CLK +50 ns

22 Address Valid to RD or WR Low tAVRDL 4tCLK -130 ns

23 Data Valid to WR Going Low tDVWRL tCLK -60 ns

24 Data Valid to WR High @ 12 MHz tDVWRH 7tCLK -150 ns

# PARAMETER SYMBOL MIN MAX UNITS @ 16 MHz 7t CLK -90 ns

25 Data Valid after WR High tWRHDV tCLK -50 ns

26 RD Low to Address Float tRDLAZ 0n s

27 RD or WR High to ALE High tRDHALH tCLK -40 t CLK +50 ns

EXPANDED PROGRAM MEMORY READ CYCLE

EXPANDED DATA MEMORY READ CYCLE EXPANDED DATA MEMORY WRITE CYCLE

AC CHARACTERISTICS (cont'd) EXTERNAL CLOCK DRIVE (tA=0˚C to70˚C; VCC=5V ± 10%) # PARAMETER SYMBOL MIN MAX UNITS

28 External Clock High Time @ 12 MHz

@ 16 MHz tCLKHPW 20 ns ns

29 External Clock Low Time @ 12 MHz

@ 16 MHz tCLKLPW 20 ns ns

30 External Clock Rise Time @ 12 MHz

@ 16 MHz tCLKR 20 ns ns

31 External Clock Fall Time @ 12 MHz

@ 16 MHz tCLKF 20 ns ns EXTERNAL CLOCK TIMING AC CHARACTERISTICS (cont'd) POWER CYCLING TIMING (tA=0˚C to70˚C; VCC=5V ± 10%) # PARAMETER SYMBOL MIN MAX UNITS 32 Slew Rate from V CCMIN to 3.3V t F 130 µs

33 Crystal Startup Time t CSU (note 6)

34 Power-On Reset Delay t POR 21504 t CLK

AC CHARACTERISTICS (cont'd) SERIAL PORT TIMING - MODE 0 (tA=0˚C to70˚C; VCC=5V ± 10%) # PARAMETER SYMBOL MIN MAX UNITS

35 Serial Port Cycle Time t SPCLK 12tCLK µs

36 Output Data Setup to Rising Clock Edge t DOCH 10tCLK -133 ns

37 Output Data Hold after Rising Clock Edge t CHDO 2tCLK -117 ns

38 Clock Rising Edge to Input Data Valid t CHDV 10tCLK -133 ns

39 Input Data Hold after Rising Clock Edge t CHDIV 0n s

SERIAL PORT TIMING - MODE 0 AC CHARACTERISTICS (cont'd) PARALLEL PROGRAM LOAD TIMING (tA=0˚C to70˚C; VCC=5V ± 10%) # PARAMETER SYMBOL MIN MAX UNITS

41 Pulse Width of PE 3-4 tCEPW 4tCLK-35 ns

45 Byte-wide Address Hold after PE 3-4 High

46 Delay from Byte-wide Address Valid PE 3-4

47 Byte-wide Data Setup to PE 3-4 High During

MOVX (read) tDACEH 1tCLK+40 ns

48 Byte-wide Data Hold after PE 3-4 High

During MOVX (read) tCEHDV 10 ns

49 Byte-wide Address Valid to R/ W Active

During MOVX (write) tAVRWL 3tCLK-35 ns

50 Delay from R/ W Low to Valid Data Out

During MOVX (write) tRWLDV 20 ns

51 Valid Data Out Hold Time from PE 3-4 High tCEHDV 1tCLK-15 ns

52 Valid Data Out Hold Time from R/ W High tRWHDV 0n s

53 Write Pulse Width (R/ W Low Time) tRWLPW 6tCLK-20 ns

RPC AC CHARACTERISTICS - DBB READ (tA=0˚C to70˚C; VCC=5V ± 10%) # PARAMETER SYMBOL MIN MAX UNITS

54 CS , A0 Setup to RD tAR 0n s

55 CS , A0 Hold After RD tRA 0n s

56 RD Pulse Width tRR 160 ns

57 CS , A0 to Data Out Delay tAD 130 ns

58 RD to Data Out Delay tRD 0 130 ns

59 RD to Data Float Delay tRDZ 85 ns

RPC AC CHARACTERISTICS - DBB READ (tA=0˚C to70˚C; VCC=5V ± 10%) # PARAMETER SYMBOL MIN MAX UNITS

60 CS , A0 Setup to WR tAW 0n s

61A CS , Hold After WR tWA 0n s 61B A0, Hold After WR tWA 20 ns

62 WR Pulse Width tWW 20 ns

63 Data Setup to WR tDW 130 ns

64 Data Hold After WR tWD 20 ns

AC CHARACTERISTICS - DMA (tA=0˚C to70˚C; VCC=5V ± 10%) # PARAMETER SYMBOL MIN MAX UNITS

65 DACK to WR or RD tACC 0n s

66 RD or WR to DACK tCAC 0n s

67 DACK to Data Valid tACD 0 130 ns

68 RD or WR to DRQ Cleared tCRQ 110 ns

AC CHARACTERISTICS - PROG (tA=0˚C to70˚C; VCC=5V ± 10%) # PARAMETER SYMBOL MIN MAX UNITS

69 PROG Low to Active tPRA 48 CLKS

70 PROG High to Inactive tPRI 48 CLKS

RPC TIMING MODE 16 (cont'd) NOTES: 1. All voltages are referenced to ground. 2. Maximum operating I CC is measured with all output pins disconnected; XTAL1 driven with t CLKR, tCLKF=10 ns, VIL = 0.5V; XTAL2 disconnected; RST = PORT0 = VCC. 3. Idle mode IIDLE is measured with all output pins disconnected; XTAL1 driven with t CLKR, tCLKF = 10 ns, VIL = 0.5V; XTAL2 disconnected; PORT0 = VCC, RST = VSS. 4. Stop mode I STOP is measured with all output pins disconnected; PORT0 = V CC; XTAL2 not connected; RST = XTAL1 = VSS. 5. Pin capacitance is measured with a test frequency - 1 MHz, tA = 25°C. 6. Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the crystal vendor for a worst case specification on this time. PF pin operation is specified with VBAT ≥ 3.0V.

A 4.245 4.255 B 3.979 3.989 C 0.995 1.005 D 0.395 0.405 E 0.245 0.255 F 0.050 BSC G 0.075 0.085 H 0.245 0.255 I 1.750 BSC J 0.120 0.130 K 2.120 2.130 L 2.245 2.255 M 0.057 0.067 N - 0.275 O - 0.145 P 0.047 0.054

DATA SHEET REVISION SUMMARY The following represent the key differences between 12/13/95 and 08/13/96 version of the DS2251T data sheet. Please review this summary carefully. 1. Change VCC slew rate definition to reference 3.3V instead of VLI. 2. Add minimum value to PCB thickness. The following represent the key differences between 08/15/96 and 05/29/97 version of the DS2251T data sheet. Please review this summary carefully. 1. PF signal moved from VOL2 test specification to VOL1. (PCND73001) The following represent the key differences between 05/28/97 and 11/08/99 version of the DS2251T data sheet. Please review this summary carefully. (PCN I80903) 1. Correct Absolute Maximum Ratings to reflect changes to DS5001FP microprocessor. 2. Add note clarifying that SRAM contents are not defined under storage temperature conditions. The following represent the key differences between 11/08/99 and 01/18/00 version of the DS2251T data sheet. Please review this summary carefully. 1. Document converted from interleaf to Microsoft Word.