DS2227-100

DS2227 DALLAS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

FEATURES

/elevenoclock Flexibly organized as 128k x 32, 256k x 16, or 512k x 8 bits /elevenoclock Data retention >10 years in the absence of VCC /elevenoclock Nonvolatile circuitry transparent to and independent from host system /elevenoclock Automatic write protection circuitry safeguards against data loss /elevenoclock Separate chip enables allow access by byte, word, or long word /elevenoclock Fast access times: 70 ns, 100 ns, or 120 ns /elevenoclock Unlimited write cycles /elevenoclock Read cycle time equals write cycle time /elevenoclock Employs popular JEDEC standard 72-position SIMM connection scheme /elevenoclock Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time PIN ASSIGNMENT

DESCRIPTION

The DS2227 Flexible NV SRAM Stik is a self-contained 4,194,304-bit nonvolatile static RAM which can be flexibly organized as 128k x 32 bits, 256k x 16 bits, or 512k x 8 bits. The nonvolatile memory contains all necessary control circuitry and lithium energy sources to maintain data integrity in the absence of power for more than 10 years. The DS2227 employs the popular JEDEC standard 72-position SIMM connection scheme requiring no additional circuitry. OPERATION The DS2227 Flexible NV SRAM Stik is used like any standard static RAM. All nonvolatile circuitry is transparent to the user. The flexibility of the part is achieved by providing separate read, write, and chip DS2227 Flexible NV SRAM Stik www.dalsemi.com 72 1 SRAM SRAM SRAM SRAM 72-Pin SIP STIK

select pins for each of the four banks of onboard memories (see Figure 1). For operation as a 512k x 8 NV SRAM Stik, tie all data lines from each bank together (i.e., all D0s together, all D1s together, etc.). Read enables and write enables are also tied together. For operation as a 256k x 16 NV SRAM Stik, tie the data lines from two banks together. Chip enables, read enables, and write enables from these banks are also tied together. Connection to the DS2227 is made by using an industry-standard, 72-position SIMM socket DS9072-72V (AMP part number 821824-8). These SIMM sockets are also available in perpendicular, inclined, or parallel mount, depending on the height available. See the DS907x SipStik TM connectors available from Dallas Semiconductor. READ MODE The DS2227 executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 17 address inputs (A0 - A16) defines which byte of data is to be accessed. Valid data will be available to the eight data I/O pins within tACC (access time) after the last address input signal is stable, providing that CE and OE access times are also satisfied. If OE and CE times are not satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting parameter is either t CO for CE or t OE for OE rather than address access. WRITE MODE The DS2227 is in the write mode whenever both WE and CE signals are in the active (low) state after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus has been enabled ( CE and OE active) then WE will disable the outputs to tODW from its falling edge. DATA RETENTION MODE The DS2227 provides fully functional capability for V CC greater than 4.5 volts and guarantees write protection for VCC less than 4.25 volts. Data is maintained in the absence of V CC without any additional support circuitry. The DS2227 constantly monitors V CC. Should the supply voltage decay, the NV SRAM automatically write-protects itself, all inputs become “don’t care” and all outputs become high impedance. As V CC falls below approximately 3.0 volts, a power switching circuit connects a lithium energy source to RAM to retain data. During power-up, when V CC rises above approximately 3.0 volts, the power switching circuit connects the external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds 4.5 volts. The DS2227 checks lithium status to warn of potential data loss. Each time that V CC power is restored to the DS2227, the battery voltage is checked with a precision comparator. If the battery supply is less than 2.0 volts, the second memory access to the device is inhibited. Battery status can, therefore, be determined by a three-step process. First, a read cycle is performed to any location in memory, in order to save the contents of that location. A subsequent write cycle can then be executed to the same memory location, altering data. If the next read cycle fails to verify the written data, then the battery voltage is less than 2.0V and data is in danger of being corrupted. The DS2227 also provides battery redundancy. In many applications data integrity is paramount. The DS2227 provides two batteries for each SRAM and an internal isolation switch to select between them. During battery backup, the battery with the highest voltage is selected for use. If one battery fails, the other automatically takes over. The switch between batteries is transparent to the user.

PIN SIGNAL NAME PIN SIGNAL NAME 1V CC 38 4-D0 2 1-D0 39 4-D1 3 1-D1 40 4-D2 4 1-D2 41 4-D3 5 1-D3 42 4-D4 6 1-D4 43 4-D5 7 1-D5 44 4-D6 8 1-D6 45 4-D7 91 - D 7 4 6 N C

10 NC 47 4- CE

22 NC 59 A7

34 NC 71 NC

NOTE: Leave all pins marked as NC unconnected.

SCHEMATIC (1 CELL) Figure 1

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to +7.0V Operating Temperature 0°C to 70°C Storage Temperature -40° to +85°C * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power Supply Voltage V CC 4.5 5.0 5.5 V Input High Voltage V IH 2.2 V CC V Input Low Voltage V IL 0 +0.8 V DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 5V ± 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current I IL -1.0 +1.0 µA I/O Leakage Current I LO -5.0 +5.0 µA Output Current @ 2.4V I OH -1.0 mA Output Current @ 0.4V I OL 2.0 3.0 mA Operating Current I CC 60 280 mA Write Protection Voltage V TP 4.25 4.37 4.5 V CAPACITANCE (TA = 25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C IN 20 40 pF Output Capacitance C OUT 51 0 p F

AC ELECTRICAL CHARACTERISTICS DS2227-70 DS2227-100 DS2227-120 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES Read Cycle Time t RC 70 100 120 ns 10 Access Time t ACC 70 100 120 ns 10 OE to Output Valid tOE 35 50 60 ns 10 CE to Output Valid tCO 70 100 120 ns 10 OE or CE to Output Active tCOE 555 n s 1 0 Output High Z from Deselection tOD 25 35 40 ns 10 Output Hold from Address Change tOH 555 n s 1 0 Write Cycle Time t WC 70 100 120 ns 10 Write Pulse Width t WP 55 75 90 ns 3,10 Address Setup Time tAW 000 n s 1 0 Write Recovery Time tWR 20 20 20 ns 10 Output High Z from WE tODW 25 35 40 ns 10 Output Active from WE tOEW 5 5 5 ns 8,10 Data Setup Time t DS 30 40 50 ns 4,10 Data Hold Time from WE tDH 20 20 20 ns 4,5,10

SEE NOTES 2, 3, 4, 5, 6, 7 AND 8 WRITE CYCLE 2 SEE NOTES 2, 3, 4, 5, 6, 7 AND 8

POWER-UP/POWER-DOWN CONDITION POWER-DOWN/POWER-UP TIMING PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CE at VIH Before Power-down tPD 0µ s VCC Slew from 4.5V to 4.25V ( CE at VIH ) tF 300 µs VCC Slew from 0V to 4.5V ( CE at VIH ) tR 0µ s CE at VIH after Power-up tREC 2 80 125 ms (TA = 25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Data Retention t DR 10 years

NOTES: 1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE . 4. tDH, tDS are measured from the earlier of CE or WE going high. 5. tDH is measured from WE going high. If CE is used to terminate the write cycle then tDH = 20 ns. 6. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high impedance state in this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state in this period. 8. If the WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state in this period. 9. Each DS2227 is marked with a 4-digit date code AABB. AA designates the year of manufacture. BB designates the week of manufacture. The minimum expected t DR is defined as starting at the date of manufacture. 10. Timings are valid only when CE is tied low. DC TEST CONDITIONS Outputs Open Cycle = 200 ns All Voltages are Referenced to Ground AC TEST CONDITIONS Output Load: 100 pF + 1TTL gate Input Pulse Levels: 0 - 3.0 V Timing Measurements Reference Levels: Input - 1.5V Output - 1.5V Input Pulse Rise and Fall Times: 5 ns

ORDERING INFORMATION

NOTE: DIMENSIONS ARE SHOWN IN INCHES. 72-PINDIM MIN MAX A 4.245 4.255 B 3.979 3.989 C 0.845 0.855 D 0.395 0.405 E 0.245 0.255 F 0.050 BASIC G 0.075 0.085 H 0.245 0.255 I 1.750 BASIC J 0.120 0.130 K 2.120 2.130 L 2.245 2.255 M 0.057 0.067 N - 0.140 O - 0.140 P - 0.054