DS2064 DALLAS | Alldatasheet

Document overview

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Technical content

FEATURES

  • Low power CMOS design
  • Standby current 50 nA max at tA = 25°CV CC = 3.0V 100 nA max at tA = 25°CV CC = 5.5V 1 µA max at tA = 60°CV CC = 5.5V
  • Full operation for VCC = 4.5V to 5.5V
  • Data Retention Voltage = 5.5V to 2.0V
  • Access time equals 200 ns at 5.0V
  • Operating temperature range of –40°C to +85°C
  • Full static operation
  • TTL compatible inputs and outputs
  • Available in 28–pin DIP and 28–pin SOIC packages
  • Suitable for both battery operated and battery backup

applications

DS2064–200 28–PIN DIP (600 MIL) DS2064S–200 28–PIN SOIC (330 MIL) PIN DESCRIPTION A0–A12 – Address Inputs DQ0–DQ7 – Data Input/Output CE1 , CE2 – Chip Enable Inputs WE – Write Enable Input OE – Output Enable Input VCC – 5V Power Supply Input GND – Ground NC – No Connection

DESCRIPTION

The DS2064 is a 65536–bit low power, fully static ran- dom access memory organized as 8192 words by eight bits using CMOS technology. The device operates from a single power supply with a voltage input between 4.5V and 5.5V. The chip enable inputs (CE1 and CE2) are used for device selection and can be used in order to achieve the minimum standby current mode, which fa- cilitates both battery operate and battery backup appli- cations. The device provides fast access time of 200 ns and is most suitable for low power applications where battery operation or battery backup for nonvolatility are required. The DS2064 is a JEDEC–standard 8K x 8 SRAM and is pin–compatible with ROM and EPROM of similar density.

VCC Power Supply Voltage –0.3V to +7.0V VIN, VI/O Input, Input/Output Voltage –0.3 to VCC + 0.3V TSTG Storage Temperature –55°C to +125°C TOPR Operating Temperature –40°C to +85°C TSOLDER Soldering Temperature/Time 260°C for 10 seconds RECOMMENDED DC OPERATING CONDITIONS (tA = –40°C to +85°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power Supply Voltage VCC 4.5 5.0 5.5 V Input High Voltage VIH 2.0 VCC + 0.3 V Input Low Voltage VIL –0.3 0.8 V Data Retention Voltage VDR 2.0 5.5 V DC CHARACTERISTICS (tA = –40°C to +85°C; VCC =5V ± 10%) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage Current IIL 0V < VIN < VCC +0.1 µA I/O Leakage Current ILO CE1 =VIH,0V<VIO<VCC +0.5 µA Output High Current IOH VOH = 2.4V –1.0 mA Output Low Current IOL VOL = 0.4V 4.0 mA Standby Current ICCS1 CE1 = 2.0V 0.5 mA Standby Current ICCS2 CE1 >VCC –0.5V tA=60°C 1 µA Standby Current ICCS2 CE1 >VCC –0.5V tA=25°C 100 nA Operating Current ICCO CE1 =0.8V, 200 ns cycle 70 mA CAPACITANCE (tA = 25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C IN 5 10 pF Input/Output Capacitance C I/O 5 12 pF

AC CHARACTERISTICS, READ CYCLE (tA = –40°C to +85°C; VCC =5V ± 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Read Cycle Time tRC 200 ns Access Time tACC 200 ns OE to Output Valid tOE 100 ns CE to Output Valid tCO 200 ns CE or OE to Output Active tCOE 5 ns Output to High–Z from Deselection tOD 10 60 ns Output Hold from Address Change tOH 5 ns AC CHARACTERISTICS, WRITE CYCLE (tA = –40°C to +85°C; VCC =5V ± 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Write Cycle Time tWC 200 ns Write Pulse Width tWP 150 ns Address Setup Time tAW 0 ns Write Recovery Time tWR 10 ns Output High–Z from WE tODW 70 ns 7 Output Active from WE tOEW 5 ns 7 Data Setup Time tDS 80 ns Data Hold Time tDH 0 ns TIMING DIAGRAM: READ CYCLE tRC tACC VIH VIL VIH VIL VIH VIL tOH VIH tOD tOD VIH VOH VOL VOH VOL tCOE tCOE OUTPUT DATA VALIDD OUT OE ADDRESSES VIH VIH tOE VIL VIL CE tCO SEE NOTE 1

TIMING DIAGRAM: WRITE CYCLE 1 tWC VIH VIL VIH VIL VIH VIL ADDRESSES tAW DATA IN STABLE VIL VIL VIL VIL VIH VIH tWP tWR tODW tOEW tDS tDH VIH VIL VIH VIL CE WE D OUT D IN SEE NOTES 2, 3, 4, 5, 6 AND 7

TIMING DIAGRAM: WRITE CYCLE 2 tWC VIL VIH VIL VIH VIL VIH ADDRESSES CE WE D OUT D IN DATA IN STABLE tAW tWP tWR VIH VIL VIL VIH VIH VIL VIL tCOE tODW tDS tDH VIL VIH VIL VIH SEE NOTES 2, 3, 4, 5, 6 AND 7 TIMING DIAGRAM: DATA RETENTION – POWER UP, POWER DOWN DATA RETENTION MODE VCC - 0.2V VCC CE GND tCDR tR 2.7V VIH VIL SEE NOTE 8

DATA RETENTION CHARACTERISTICS (tA=–40°C to +85°C) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Data Retention Supply Voltage VDR CE1 > VCC – 0.5V 2.0 5.5 V Data Retention Current at 5.5V ICCR1 CE1 > VCC – 5.0V 0.1* 1 µA Data Retention Current at 2.0V ICCR2 CE1 > VCC – 5.0V 50* 750 nA Chip Deselect to Data RetentiontCDR 0 µs Recovery Time tR 2 ms * Typical values are at 25°C FUNCTION TABLE MODE CE1 CE2 OE WE A0 – A12 DQ – DQ7 POWER READ L H L H STABLE DATA OUT I CCO WRITE L H X L STABLE DATA IN I CCO DESELECT L H H H X HIGH–Z I CCO STANDBY H XXXX HIGH–Z I CCS STANDBY X L X X X HIGH–Z I CCS

NOTES: 1. WE is high for read cycles. 2. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDH and tDS are measured from the earlier of CE or WE going high. 5. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain in a high impedance state. 6. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state. 7. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state. 8. If the VIH level of CE is 2.0V during the period that VCC voltage is going down from 4.5V to 2.7V, ICCS1 current flows. DC TEST CONDITIONS Outputs Open All voltages are referenced to ground AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0V – 3.0V Timing Measurement Reference Levels Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5 ns

DS2064 28–PIN DIP C A B D H J K G E F DIM MIN MAX 28–PINPKG A IN. 1.440 1.460 MM 30.99 32.00 B IN. 0.540 0.560 MM 13.72 14.22 C IN. 0.140 0.160 MM 3.56 4.06 D IN. 0.590 0.625 MM 14.99 15.88 E IN. 0.015 0.040 MM 0.380 1.02 F IN. 0.110 0.135 MM 2.79 3.43 G IN. 0.090 0.110 MM 2.29 2.79 H IN. 0.625 0.675 MM 15.88 17.15 J IN. 0.008 0.012 MM 0.20 0.30 K IN. 0.015 0.021 MM 0.38 0.53

DS2064S 28–PIN SOIC PKG 28–PIN DIM MIN MAX A IN. MM 0.080 2.04 0.120 3.05 A1 IN. MM 0.002 0.05 0.014 0.35 b IN. MM 0.012 0.30 0.020 0.50 C IN MM 0.004 0.10 0.0125 0.32 D IN. MM 0.697 17.70 0.728 18.50 e IN. MM

0.050 BSC

1.27 BSC

E1 IN. MM 0.324 8.23 0.350 8.90 H IN MM 0.453 11.5 0.500 12.7 L IN MM 0.016 0.40 0.051 1.30 0° 10° The chamfer on the body is optional. If it is not present, a terminal 1 identifier must be positioned so that 1/2 or more of its area is contained in the hatched zone.