DS1994

DS1994 DALLAS | Alldatasheet

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/g167 4096 bits of Read/Write Nonvolatile Memory /g167 256-bit Scratchpad Ensures Integrity of Data Transfer /g167 Memory Partitioned into 256-bit Pages for Packetizing Data /g167 Data Integrity Assured with Strict Read/Write Protocols /g167 Contains Real-Time Clock/Calendar in Binary Format /g167 Interval Timer Can Automatically Accumulate Time When Power is Applied /g167 Programmable Cycle Counter can Accumulate the Number of System Power- On/Off Cycles /g167 Programmable Alarms Can Be Set to Generate Interrupts for Interval Timer, Real- Time Clock, and/or Cycle Counter /g167 Write-Protect Feature Provides Tamperproof Time Data /g167 Programmable Expiration Date That Limits Access to SRAM and Timekeeping /g167 Clock Accuracy is Better Than ±2 Minutes/ Month at 25°C /g167 Operating Temperature Range from -40°C to +70°C /g167 Over 10 Years of Data Retention COMMON iButton® FEATURES /g167 Unique, Factory-Lasered, and Tested 64-bit Registration Number (8-bit Family Code + 48-bit Serial Number + 8-bit CRC Tester) Assures Absolute Traceability Because No Two Parts Are Alike /g167 Multidrop Controller for MicroLAN /g167 Digital Identification and Information by Momentary Contact /g167 Chip-Based Data Carrier Compactly Stores Information /g167 Data Can Be Accessed While Affixed to Object /g167 Economically Communicates to Bus Master with a Single Digital Signal at 16.3kbps /g167 Standard 16mm Diameter and 1-Wire Protocol Ensure Compatibility with iButton Family /g167 Button Shape is Self-Aligning with Cup- Shaped Probes /g167 Durable Stainless Steel Case Engraved with Registration Number Withstands Harsh Environments /g167 Easily Affixed with Self-Stick Adhesive Backing, Latched by its Flange, or Locked with a Ring Pressed onto its Rim /g167 Presence Detector Acknowledges when Reader First Applies Voltage /g167 Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept for Use in Class I, Division 1, Group A, B, C and D Locations F5 MICROCAN IO GND 0.36 0.51 5.89 © 1993 YYWW REGISTERED RR 61 04 000000FBD804 16.25 17.35 All dimensions shown in millimeters.

ORDERING INFORMATION

4kb Plus Time Memory iButton www.iButton.com iButton and 1-Wire are registered trademarks of Dallas Semiconductor.

DS9096P Self-Stick Adhesive Pad DS9101 Multi-Purpose Clip DS9093RA Mounting Lock Ring DS9093F Snap-In Fob DS9092 iButton Probe iButton DESCRIPTION The DS1994 Memory iButton is a rugged read/write data carrier that acts as a localized database, easily accessible with minimal hardware . The nonvolatile memory and opti onal timekeeping capability offer a simple solution to storing and retrieving vital information pertaining to the object to which the iButton is attached. Data is transferred serially through the 1-Wi re protocol that requires only a single data lead and a ground return. The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command transfers the data to memory. This process ensures data integrity when modifying the memory. A 48-bit serial number is factory lasered into each DS1994 to provide a guaranteed unique identity that allows for absolute traceability. The durable MicroCan package is highly resistant to environmental hazards such as dirt, moisture, and shock. Its compact, coin-shaped profile is self-aligning with mating receptacles, allowing the DS1994 to be easily used by human operators. Accessories permit the DS1994 to be mounted on almost any surface including plastic key fobs, photo-ID badges, and PC boards. The DS1994 also includes time-keeping functions, a r eal-time clock/calendar, interval timer, cycle counter, and programmable interrupts, in addition to the nonvolatile me mory. The internal clock can be programmed to deny memory access based on absolute time/date, total elapsed time, or the number of accesses. These features allow the DS1994 to be us ed to create a stopwatch, alarm clock, time and date stamp, logbook, hour meter, calendar, system power cycle timer, interval timer, and event scheduler. OPERATION The DS1994 has four main data com ponents: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, 3) 4096-bit SRAM, and 4) timekeeping registers. The timekeeping section utilizes an on-chip oscillator that is connected to a 32.768kHz crystal. The SRAM and time -keeping registers reside in one contiguous address space referred to hereafter as memory. All data is read and written least significant bit first. The memory functions are not available until the ROM function protocol has been established. This protocol is described in the ROM functions flowchar t (Figure 9). The master must first provide one of four ROM function commands: 1) read ROM, 2) match ROM, 3) search ROM, or 4) skip ROM. After a ROM function sequence has been successfully execu ted, the memory functions are accessible and the master can then provide any one of the four memory function commands (Figure 6).

Figure 1. DS1994 BLOCK DIAGRAM

16 PAGES of

Each DS1994 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. the 8 bits of CRC should return the shift register to all zeros. Figure 2. 64-BIT LASERED ROM

Figure 3. 1-WIRE CRC CODE contains page 16, which has only 30 Bytes containing the timekeeping registers. transfers the data to memory. This process ensures data integrity when modifying the memory. clock, interval timer, and cycle counter to function. 1970 could be a reference point.

Figure 4. DS1994 MEMORY MAP represent the starting address for each page or register.

The interval timer is a 5-Byte binary counter. Wh en enabled, it is incremented 256 times per second. The least significant Byte is a count of fractional seconds. The interv al timer can accumulate 136 years of seconds before rolling over. The in terval timer has two modes of oper ation that are selected by the AUTO/MAN bit in the control register. In the auto mode, the interval timer begins counting after the data line has been high for a period of time determined by the DSEL bit in the control register. Similarly, the interval timer stops counting after the data line has been low for a period of time determined by the DSEL bit. In the manual mode, time accumulation is controlled by the STOP/START bit in the control register. NOTE: For auto mode operation, the high level on the data line must be greater than or equal to 2.1V. Cycle Counter The cycle counter is a 4-Byte binary counter. It incr ements after the falling edge of the data line if the appropriate data line timing has been met. This timing is selected by the DSEL bit in the control register. (See the Status/Control section). NOTE: For cycle counter operation, the high level on the data line must be greater than or equal to 2.1V. Alarm Registers The alarm registers for the real-time clock, interval timer, and cycle counter all operate in the same manner. When the value of a given counter equals the value in its associated alarm register, the appropriate flag bit is set in the status register. If the corresponding interrupt enable bit in the status register is set, an interrupt is ge nerated. If a counter and its associated alarm register are write protected when an alarm occurs, access to the device becomes limited. (See the Status/Control, Interrupts, and Programmable Expiration sections.) STATUS/CONTROL REGISTERS The status and control registers are the first two Bytes of page 16 (see Figure 4). Status Register 76543210 X X CCE ITE RTE CCF ITF RTF 0200h DON’T CARE BITS READ ONLY

0 RTF Real-time clock alarm flag

1 ITF Interval timer alarm flag

2 CCF Cycle counter alarm flag

When a given alarm occurs, the corr esponding alarm flag is set to a logic 1. The alarm flag is cleared by reading the status register.

3 RTE Real-time clock alarm flag

4 ITE Interval timer alarm flag

5 CCE Cycle counter alarm flag

Writing any of the interrupt enable bits to a logic 0 allows an interrupt condition to be generated when its corresponding alarm flag is set (see the Interrupts section). Control Register 76543210 DSEL STOP START AUTO MAN. OSC RO WPC WPI WPR 0201h

0 WPR Write protect real-time clock/alarms registers

1 WPI Write protect interval timer/alarms registers

2 WPC Write protect cycle counter/alarms registers

Setting a write protect bit to a logic 1 permanently write protects the corresponding counter and alarm registers, all write protect bits, a nd additional bits in the control regi ster. The write protect bits cannot be written in a normal manner (see the Write Protect/Programmable Expiration section).

3 RO Read only

If a programmable expiration occurs and the read onl y bit is set to a logic 1, then the DS1994 becomes read only. If a programmable expiration occurs and the read only bit is a logic 0, then only the 64-bit lasered ROM can be accessed (see the Write Protect/Programmable Expiration section).

4 OSC Oscillator enable

This bit controls the crystal oscillator. When set to a logic 1, the oscillator starts operation. When the oscillator bit is a logic 0, the oscillator stops.

5 AUTO/MAN Automatic/Manual Mode

When this bit is set to a logic 1, the interval timer is in automatic mode. In this mode, the interval timer is enabled by the data line. When this bit is set to a logic 0, the interval timer is in manual mode. In this mode, the interval timer is enabled by the STOP/START bit.

6 STOP/START Stop/Start (in manual mode)

If the interval timer is in manual m ode, the interval timer starts counting when this bit is set to a logic 0 and stops counting when set to a logic 1. If the interval timer is in automatic mode, this bit has no effect.

7 DSEL Delay Select Bit

the cycle counter. When this bit is set to a logic 0, the delay time is 3.5 /g177 0.5ms. The Memory Function Flowchart (Figure 6) describes the protocols necessary for accessing the memory. would point to the last Byte of a page. Byte flag. Bit 6 (OF) is the overflow flag. Bit 7 (AA) is the authorization accepted flag. Figure 5. ADDRESS REGISTERS overflow has not occurred, the partial Byte flag (PF) is set.

ending offset/data status Byte (E/S), followed by the scratchpad data beginning at the Byte offset (T4:T0). The user can read data until the end of the scratchpad, after which the data read is all logic 1’s. Copy Scratchpad [55h] This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad command, the user must provide a 3-Byte authorizati on pattern. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/ S, in that order). If the pattern matches, the AA (authorization accepted) flag is set and the copy begi ns. A logic 0 is transmitted after the data has been copied until the user issues a reset pulse. Any attempt to reset the part is ignored while the copy is in progress. Copy typically takes 30/g109s. The data to be copied is determined by the three address registers. The scratchpad data, from the beginning offset through the ending offset, is copied to memory, starting at the target address. Anywhere from 1 to 32 Bytes can be copied to memory with this command. Whole Bytes are copied even if only partially written. The AA flag is cleared only by executing a write scratchpad command. Read Memory [F0h] The read memory command can be used to read the entire memory. After issuing the command, the user must provide the 2-Byte target address. After the two Bytes, the user reads data beginning from the target address and can continue until the end of memory, at which point logic 1’s are read. It is important to realize that the target address registers contain the address provided. The ending offset/data status Byte is unaffected. The hardware of the DS1994 provides a means to a ccomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to simultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (Refer to Application Note 114 for the recommended file structure to be used with the 1-Wire environment.)

Figure 6. MEMORY FUNCTIONS FLOWCHART

Figure 6. MEMORY FUNCTIONS FLOWCHART (continued)

Example: Write two data Bytes to memory locations 0026h and 0027h (t he seventh and eighth Bytes of page 1). Read entire memory. MASTER MODE DATA (LSB FIRST) COMMENTS TX Reset Reset pulse (480/g109s–960/g109s) RX Presence Presence pulse TX CCh Issue skip ROM command TX 0Fh Issue write scratchpad command TX 26h TA1, beginning offset = 6 TX 00h TA2, address = 0026h TX <2 data Bytes> Write 2 By tes of data to scratchpad TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue skip ROM command TX AAh Issue read scratchpad command RX 26h Read TA1, beginning offset = 6 RX 00h Read TA2, address = 0026h RX 07h Read E/S, ending offset = 7, flags = 0 RX <2 data Bytes> Read sc ratchpad data and verify TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue skip ROM command TX 55h Issue copy scratchpad command TX 26h TX 00h TX 07h TA1 TA2 AUTHORIZATION CODE E/S TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue skip ROM command TX F0h Issue read memory command TX 00h TA1, beginning offset = 6 TX 00h TA2, address = 0000h RX <542 Bytes> Read entire memory TX Reset Reset pulse RX Presence Presence pulse, done

memory function commands are available. The ROM functions are always available. Figure 7. WRITE PROTECT CHART

• Becomes write 1 only, i.e., once written to a logic 1, cannot be written back to a logic 0.

configuration, transaction sequence, and 1-Wire signaling (signal types and timing). the bus is left low for more than 120/g109s, one or more of the devices on the bus can be reset.

Figure 8. HARDWARE CONFIGURATION operate. For more details, see the 1-Wire Signaling section. result in a mismatch of the CRC. sequence wait for a reset pulse. This command can be used with a single or multiple devices on the bus.

Figure 9. ROM FUNCTIONS FLOWCHART

6 Bytes

1 Byte

Skip ROM [CCh] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1- Wire bus or their 64-bit ROM codes. The search RO M command allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple three–step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, three-step routine on each bit of the ROM. After one complete pass, the bus master knows the contents of the RO M in one device. Additional passes can identify the remaining number of devices and their ROM codes. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive disc ussion of a search ROM, including an actual example. Search Interrupt [ECh] This ROM command works exactly as the normal ROM Search, but it identifies only devices with interrupts that have not yet been acknowledged. 1-WIRE SIGNALING The DS1994 requires strict protocols to ensure data integrity. The prot ocol consists of five types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, read data, and interrupt pulse. The bus master initiates all these signals except presence pulse and interrupt pulse. The initialization sequence required to begin any communi cation with the DS1994 is shown in Figure 10. A reset pulse followed by a presence pulse indicates th e DS1994 is ready to send or receive data given the correct ROM command and memory function command. The bus master transmits (Tx) a reset pulse RSTL, minimum 480 /g109s). The bus master then releases the line and goes into receive mode (Rx). The 1- Wire bus is pulled to a high state through the pullup resistor. After detecting the rising edge on the data line, the DS1994 waits (t PDH, 15/g109s to 60 /g109s) and then transmits the presence pulse (t PDL, 60/g109s to 240 /g109s). There are special conditions if interrupts are enabled for which the bus master must check the state of the 1-Wire bus after being in the Rx mode for 480/g109s. These conditions are discussed in the Interrupt section. READ/WRITE TIME SLOTS The definitions of write and read time slots are illustrated in Figure 11. The master driving the data line low initiates all time slots. The fa lling edge of the data line synchronizes the DS1994 to the master by triggering a delay circuit in the DS1994. During write time slots, the delay circuit determines when the DS1994 samples the data line. For a read data time sl ot, if a 0 is to be transmitted, the delay circuit determines how long the DS1994 holds the data line low overriding the 1 generated by the master. If the data bit is a 1, the iButton leaves the read data time slot unchanged.

Figure 11. READ/WRITE TIMING DIAGRAM (continued) alarm condition occurs while the device is disarmed, at first a type 2 interrupt is produced.

been acknowledged by the master, the DS1994 continues sending interrupt pulses. acknowledging the interrupt), the waveform of the type 1A interrupt is found. Figure 12. TYPE 1 INTERRUPT presence pulse, i. e., no falling edge. Interrupt condition occurs here.

Size See mechanical drawing Weight 3.3 grams (F5 package) Humidity 90% RH at 50 /g176C Altitude 10,000 feet Expected Service Life 10 years at 25 /g176C Safety Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept for use in Class I, Division 1, Group A, B, C, and D Locations ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground -0.5V to +7.0V Operating Temperature -40 /g176C to +70/g176C Storage Temperature -40 /g176C to +70/g176C * This is a stress rating only, and functional operati on of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (VPUP = 2.8V to 6.0V; -40°C to +70°C) PARAMETER SYMBOL MIN TYP MAX UNITS Logic 1 (Note 1) V IH 2.2 V Logic 0 (Note 1) V IL -0.3 +0.8 V Output Logic Low at 4mA (Note 1) VOL 0.4 V Output Logic High (Notes 1, 2) VOH VPUP V Input Load Current (Note 3) IL 5 /g109A CAPACITANCE (tA = 25°C) PARAMETER SYMBOL MIN TYP MAX UNITS I/O (1-Wire) (Notes 6, 8) C IN/OUT 100 800 pF AC ELECTRICAL CHARACTERISTICS (VPUP = 2.8V to 6.0V; -40°C to +70°C) PARAMETER SYMBOL MIN TYP MAX UNITS Time Slot tSLOT 60 120 /g109s Write 1 Low Time tLOW1 11 5 /g109s Write 0 Low Time tLOW0 60 120 /g109s Read Data Valid tRDV exactly 15 /g109s Release Time tRELEASE 01 5 4 5 /g109s Read Data Setup (Note 5) tSU 1 /g109s Interrupt tINT 960 4800 /g109s Recovery Time tREC 1 /g109s Reset Time High (Note 4) tRSTH 480 /g109s

Reset Time Low (Note 7) tRSTL 480 960 /g109s Presence Detect High tPDH 15 60 /g109s Presence Detect Low tPDL 60 240 /g109s Note 1: All voltages are referenced to ground. Note 2: VPUP = external pullup voltage. Note 3: Input load is to ground. Note 4: An additional reset or communication sequence cannot begin until the reset high time has expired. Note 5: Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1/g109s of this falling edge and remains valid for 14/g109s minimum. (15/g109s total from falling edge on 1-Wire bus.) Note 6: Capacitance on the data line could be 800pF when power is first applied. If a 5k/g87/g32resistor is used to pull up the data line to VPUP, 5/g109s after power has been applied, the parasite capacitance does not affect normal communications. Note 7: The reset low time (tRSTL) should be restricted to a maximum of 960/g109s to allow interrupt signaling; otherwise, it could mask or conceal interrupt pulses. Note 8: Guaranteed by design, not production tested.