DS1992L-F5

DS1992 DALLAS | Alldatasheet

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/g167 4096 bits of Read/Write Nonvolatile Memory (DS1993) /g167 1024 bits of Read/Write Nonvolatile Memory (DS1992) /g167 256-bit Scratchpad Ensures Integrity of Data Transfer /g167 Memory Partitioned into 256-bit Pages for Packetizing Data /g167 Data Integrity Assured with Strict Read/Write Protocols /g167 Operating Temperature Range from -40°C to +70°C /g167 Over 10 years of data retention COMMON iButton FEATURES /g167 Unique, Factory-Lasered and Tested 64-bit Registration Number (8-bit Family Code + 48-bit Serial Number + 8-bit CRC Tester) Assures Absolute Traceability Because No Two Parts are Alike /g167 Multidrop Controller for MicroLAN /g167 Digital Identification and Information by Momentary Contact /g167 Chip-Based Data Carrier Compactly Stores Information /g167 Data Can be Accesse d While Affixed to Object /g167 Economically Communicates to Bus Master with a Single Digital Signal at 16.3kbps /g167 Standard 16mm Diameter and 1-Wire® Protocol Ensure Compatibility with iButton® Family /g167 Button Shape is Self-Aligning with Cup- Shaped Probes /g167 Durable Stainless Steel Case Engraved with Registration Number Withstands Harsh Environments /g167 Easily Affixed with Self-Stick Adhesive Backing, Latched by its Flange, or Locked with a Ring Pressed onto its Rim /g167 Presence Detector Acknowledges When Reader First Applies Voltage /g167 Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept for use in Class I, Division 1, Group A, B, C and D Locations F5 MICROCAN IO GND 0.36 0.51 5.89 © 1993 YYWW REGISTERED RR DD 06 000000FBD804 16.25 17.35 All dimensions shown in millimeters.

ORDERING INFORMATION

DS9096P Self-Stick Adhesive Pad DS9101 Multipurpose Clip DS9093RA Mounting Lock Ring DS9093F Snap-In Fob DS9092 iButton Probe DS1992/DS1993 1kb/4kb Memory iButton www.iButton.com 1-Wire and iButton are registered trademarks of Dallas Semiconductor.

The DS1992/DS1993 memory iButtons (hereafter referred to as DS199_) are rugged read/write data carriers that act as a localized database, eas ily accessible with minimal hardware. The nonvolatile memory and optional timekeeping capability offer a simple solution to storing and retrieving vital information pertaining to the object to which the iBu tton is attached. Data is transferred serially through the 1-Wire protocol that requires only a single data lead and a ground return. The scratchpad is an additional page that acts as a buffer when writing to memory. Data is first written to the scratchpad where it can be read back. After the data has been verified, a copy scratchpad command transfers the data to memory. This process ensures data integrity when modifying the memory. A 48-bit serial number is factory lasered into each DS199_ to provide a guaranteed unique identity that allows for absolute traceability. The durable MicroCan package is highly resistant to environmental hazards such as dirt, moisture, and shock. Its compact coin-shaped profile is self-aligning with mating receptacles, allowing the DS199_ to be easily used by human operators. Accessories permit the DS199_ to be mounted on almost any surface including plastic key fobs, photo–ID badges, and PC boards. Applications include access control, work-in-progress tracking, electronic travelers, storage of calibration constants, and debit tokens. OPERATION The DS199_ have three main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad, and 3) 1024-bit (DS1992) or 4096-bit (DS1993) SRAM. All data is read and written least significant bit first. The memory functions are not available until the ROM function protocol has been established. This protocol is described in the ROM functions flow ch art (Figure 9). The master must first provide one of four ROM function commands: 1) read ROM, 2) match ROM, 3) search ROM, or 4) skip ROM. After a ROM function sequence has been successfully execu ted, the memory functions are accessible and the master can then provide any one of the four memory function commands (Figure 6). PARASITE POWER The block diagram (Figure 1) shows the parasite-power ed circuitry. This circuitry steals power whenever the data input is high. The data line provides suffic ient power as long as the specified timing and voltage requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input, lithium is conserved, and 2) if the lithium is exhausted for any reason, the ROM can still be read normally. 64-bit LASERED ROM Each DS199_ contain a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. (See Figure 2.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 3. The polynomial is X + X5 + X4 + 1. Additional information about the Dallas 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards. The shift register bits are initialized to zero. Then starting with the least significant bit of the family code, 1 bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC should return the shift register to all zeros.

Figure 1. DS199_ BLOCK DIAGRAM

16 PAGES of 256-

4 PAGES of 256-

Figure 2. 64-BIT LASERED ROM Figure 3. 1-WIRE CRC CODE

contain pages 0 through 15 that make up the 4096-bit SRAM. transfers the data to memory. This process ensures data integrity when modifying the memory. The Memory Function Flow Chart (Figure 6) describes the protocols necessary for accessing the memory. would point to the last Byte of a page. Byte flag. Bit 6 (OF) is the overflow flag. Bit 7 (AA) is the authorization accepted flag. Figure 5. ADDRESS REGISTERS overflow has not occurred, the partial Byte flag (PF) is set. ending offset/data status Byte (E/S) followed by the scratchpad data beginning at the Byte offset (T4: T0). The user can read data until the end of the scratchpad, after which the data read is all logic 1’s.

Copy Scratchpad [55h] This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad command, the user must provide a 3-by te authorization pattern. This pa ttern must exactly match the data contained in the three address registers (TA1, TA2, E/ S, in that order). If the pattern matches, the AA (Authorization Accepted) flag is set and the copy be gins. A logic 0 is transmitted after the data has been copied until the user issues a reset pulse. Any attempt to reset the part is ignored while the copy is in progress. Copy typically takes 30/g109s. The data to be copied is determined by the three address registers. The scratchpad data from the beginning offset through the ending offset is copied to memory, starting at the target address. Anywhere from 1 to 32 Bytes can be copied to memory with this command. Whole Bytes are copied even if only partially written. The AA flag is cleared only by executing a write scratchpad command. Read Memory [F0h] The read memory command can be used to read the entire memory. After issuing the command, the user must provide the 2-Byte target address. After the two Bytes, the user reads data beginning from the target address and may continue until the end of memory, at which point logic 1’s are read. It is important to realize that the target address registers contains th e address provided. The ending offset/data status Byte is unaffected. The hardware of the DS1992/DS1993 provides a means to accomplish error-free writing to the memory section. To safeguard reading data in the 1-Wire environment and to s imultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. Such a packet would typically store a 16-bit CRC with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (See Application Note 114 for the recommended file structure to be used with the 1-Wire environment.)

Figure 6. MEMORY FUNCTIONS FLOW CHART

Figure 6. MEMORY FUNCTIONS FLOW CHART (Continued)

Example: Write two data Bytes to memory locations 0026h and 0027h (t he seventh and eighth Bytes of page 1). Read entire memory. MASTER MODE DATA (LSB FIRST) COMMENTS TX Reset Reset pulse (480/g109s to 960/g109s) RX Presence Presence pulse TX CCh Issue skip ROM command TX 0Fh Issue write scratchpad command TX 26h TA1, beginning offset = 6 TX 00h TA2, address = 0026h TX <2 data Bytes> Write 2 By tes of data to scratchpad TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue skip ROM command TX Aah Issue read scratchpad command RX 26h Read TA1, beginning offset = 6 RX 00h Read TA2, address = 0026h RX 07h Read E/S, ending offset = 7, flags = 0 RX <2 data Bytes> Read sc ratchpad data and verify TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue skip ROM command TX 55h Issue copy scratchpad command TX 26h TX 00h TX 07h TA1 TA2 AUTHORIZATION CODE E/S TX Reset Reset pulse RX Presence Presence pulse TX CCh Issue skip ROM command TX F0h Issue read memory command TX 00h TA1, beginning offset = 6 TX 00h TA2, address = 0000h RX <128 Bytes (DS1992)> <512 Bytes (DS1993)> Read entire memory TX Reset Reset pulse RX Presence Presence pulse, done

from responding in real-time. the bus is left low for more than 120/g109s, one or more of the devices on the bus may be reset. Figure 8. HARDWARE CONFIGURATION

slave(s). The presence pulse lets the bus master know that the DS199_ is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. ROM FUNCTION COMMANDS Once the bus master has detected a presence, it ca n issue one of the four ROM function commands. All ROM function commands are 8 bits long. A list of these commands follows (see the flow chart in Figure 9). Read ROM [33h] This command allows the bus master to read the DS199_’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command should only be used if there is a single DS199_ on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant famil y code and 48-bit serial number usually result in a mismatch of the CRC. Match ROM [55h] The match ROM command, followed by a 64-bit ROM se quence, allows the bus master to address a specific DS199_ on a multidrop bus. Only the DS199_ th at exactly matches the 64-bit ROM sequence will respond to the following memory function comma nd. All slaves that do not match the 64-bit ROM sequence wait for a reset pulse. This command can be used with single or multiple devices on the bus. Skip ROM [CCh] This command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued followi ng the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultane ously (open-drain pulldowns produce a wired-AND result). Search ROM [F0h] When a system is initially brought up, the bus mast er may not know the number of devices on the 1-Wire bus or their 64-bit ROM codes. The search ROM co mmand allows the bus master to use a process of elimination to identify the 64-bit ROM codes of all slave devices on the bus. The search ROM process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master performs this simple, 3-step routine on each bit of the ROM. After one complete pass, the bus master knows the 64-bit ROM code of one device. Additional passes will identify the ROM codes of the remaining de vices. See Chapter 5 of the Book of DS19xx iButton Standards for a comprehensive discussion of a search ROM, including an actual example. 1-WIRE SIGNALING The DS199_ require strict protocols to ensure data integrity. The prot ocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, and read data. The bus master initiates all these signals except presence pulse. The initialization sequence required to begin any communication with the DS199_ is shown in Figure 10. A reset pulse followed by a presence pulse indicates the DS199_ is ready to send or receive data given the correct ROM command and memory function command. The bus master transmits (Tx) a reset pulse (t RSTL, minimum 480/g109s). The bus master then releases the line and goes into receive mode (Rx). The 1-Wire bus is pulled to a high state through the pullup resistor. After detecting the rising edge on the data line, the DS199_ waits (t PDH, 15/g109s to 60/g109s) and then transmits the presence pulse (tPDL, 60/g109s to 240/g109s).

Figure 9. ROM FUNCTIONS FLOW CHART

6 Bytes

1 Byte

Figure 11. READ/WRITE TIMING DIAGRAM (continued)

Size See mechanical drawing Weight 3.3 grams (F5 package) Expected Service Life 10 years at +25 /g176C Safety Meets UL#913 (4th Edit.); Intrinsically Safe Apparatus, Approved under Entity Concept for use in Class I, Division 1, Group A, B, C and D Locations ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground -0.5V to +7.0V Operating Temperature Range -40 /g176C to +70/g176C Storage Temperature Range -40 /g176C to +70/g176C * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (VPUP = 2.8V to 6.0V; -40°C to +70°C.) PARAMETER SYMBOL MIN TYP MAX UNITS Logic 1 (Notes 1, 2) V IH 2.2 V Logic 0 (Note 1) V IL -0.3 +0.8 V Output Logic Low at 4mA (Note 1) VOL 0.4 V Output Logic High (Notes 1, 3) VOH VPUP V Input Load Current (Note 4) IL 5 /g109A CAPACITANCE (T A = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS I/O (1-Wire) (Notes 5, 6) C IN/OUT 100 800 pF AC ELECTRICAL CHARACTERISTICS (VPUP = 2.8V to 6.0V; -40°C to +70°C.) PARAMETER SYMBOL MIN TYP MAX UNITS Time Slot tSLOT 60 120 /g109s Write 1 Low Time tLOW1 11 5 /g109s Write 0 Low Time tLOW0 60 120 /g109s Read Data Valid tRDV exactly 15 /g109s Release Time tRELEASE 01 5 4 5 /g109s Read Data Setup (Note 7) tSU 1 /g109s Recovery Time tREC 1 /g109s Reset Time High (Note 8) tRSTH 480 /g109s Reset Time Low (Note 9) tRSTL 480 960 /g109s Presence Detect High tPDH 15 60 /g109s Presence Detect Low tPDL 60 240 /g109s

Note 1: All voltages are referenced to ground. Note 2: VIH is a function of the external pullup resistor and the VCC power supply. Note 3: VPUP = external pullup voltage. Note 4: Input load is to ground. Note 5: Capacitance on the data line could be 800pF when power is first applied. If a 5k/g87/g32resistor is used to pull up the data line to VPUP, 5/g109s after power has been applied, the parasite capacitance does not affect normal communications. Note 6: Guaranteed by design, not production tested. Note 7: Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1/g109s of this falling edge, and remains valid for 14/g109s minimum. (15/g109s total from falling edge on 1-Wire bus.) Note 8: An additional reset or communication sequence cannot begin until the reset high time has expired. Note 9: The reset low time (tRSTL) should be restricted to a maximum of 960/g109s, to allow interrupt signaling; otherwise it could mask or conceal interrupt pulses.