DS1706T

DS1705 DALLAS | Alldatasheet

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Technical content

Copyright 1995 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. DS1705/DS1706 3.3 and 5.0 Volt MicroMonitor DSDS1705/DS1706 011296 1/10

FEATURES

• Halts and restarts an out–of–control microprocessor
• Holds microprocessor in check during power tran- sients
• Automatically restarts microprocessor after power failure
• Monitors pushbutton for external override
• Accurate 5%, 10% or 20% resets for 3.3 systems and 5% or 10% resets for 5.0 volt systems
• Eliminates the need for discrete components
• 3.3 volt 20% tolerance for use with 3.0 volt systems
• Pin compatible with the MAXIM MAX705/MAX706 in 8–pin DIP and 8–pin SOIC
• 8–pin DIP, 8–pin SOIC and 8–pin µ–SOP packages
• Industrial temperature range –40°C to +85°C PIN ASSIGNMENT WDS RST (*RST) ST NMI PBRST VCC GND IN PBRST VCC GND IN WDS RST (*RST) ST NMI 8–PIN DIP (300 MIL) 8–PIN SOIC (150 MIL) PBRST VCC GND IN WDS RST ST NMI 8–PIN µ–SOP (118 MIL) See Mech. Drawings Section DS1705 and DS1706_/R/S/T (*DS1706L and DS1706P) PIN DESCRIPTION PBRST – Pushbutton Reset Input VCC – Power Supply GND – Ground IN – Input NMI – Non–maskable Interrupt ST – Strobe Input RST – Active Low Reset Output *RST – Active High Reset Output (DS1706P and DS1706L only) WDS – Watchdog Status Output

DESCRIPTION

The DS1705/DS1706 3.3 or 5.0 Volt MicroMonitor moni- tors three vital conditions for a microprocessor: power supply, software execution, and external override. A precision temperature compensated reference and comparator circuit monitors the status of VCC at the device and at an upstream point for maximum protec- tion. When the sense input detects an out–of–tolerance condition a non–maskable interrupt is generated. As the voltage at the device degrades an internal power fail signal is generated which forces the reset to an active state. When V CC returns to an in–tolerance condition, the reset signal is kept in the active state for a minimum of 130 ms to allow the power supply and processor to stabilize.

The second function the DS1705/DS1706 performs is pushbutton reset control. The DS1705/DS1706 debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum. The third function is a watchdog timer. The DS1705/DS1706 has an internal timer that forces the WDO signal to the active state if the strobe input is not driven low prior to time–out. OPERATION Power Monitor The DS1705/DS1706 detects out–of–tolerance power supply conditions and warns a processor–based sys- tem of impending power failure. When VCC falls below the minimum VCC tolerance, a comparator outputs the RST (or RST) signal. RST (or RST) is an excellent con- trol signal for a microprocessor, as processing is stopped at the last possible moment of valid VCC . On power–up, RST (or RST) are kept active for a minimum of 130 ms to allow the power supply and processor to stabilize. Pushbutton Reset The DS1705/DS1706 provides an input pin for direct connection to a push–button reset (see Figure 2). The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such that a RST (or RST) signal of at least 130 ms minimum will be generated. The 130 ms delay commences as the push- button reset input is released from the low level. The push–button can be initiated by connecting the WDS or NMI outputs to the PBRST input as shown in Figure 3. Non–Maskable Interrupt The DS1705/DS1706 generates a non–maskable inter- rupt (NMI ) for early warning of a power failure. A preci- sion comparator monitors the voltage level at the IN pin relative to an on–chip reference generated by an inter- nal band gap. The IN pin is a high impedance input allowing for a user–defined sense point. An external resistor voltage divider network (Figure 5) is used to interface with high voltage signals. This sense point may be derived from a regulated supply or from a higher DC voltage level closer to the main system power input. Since the IN trip point V TP is 1.25 volts, the proper val- ues for R1 and R2 can be determined by the equation as shown in Figure 5. Proper operation of the DS1705/DS1706 requires that the voltage at the IN pin be limited to VCC . Therefore, the maximum allowable voltage at the supply being monitored (VMAX ) can also be derived as shown in Figure 5. A simple approach to solving the equation is to select a value for R2 high enough to keep power consumption low, and solve for R1. The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power supply sys- tem, maximizing the amount of time for system shut– down between NMI and RST (or RST). When the supply being monitored decays to the voltage sense point, the DS1705/DS1706 pulses the NMI out- put to the active state for a minimum 200 µs. The NMI power fail detection circuitry also has built–in hysteresis of 100 µV. The supply must be below the voltage sense point for approximately 5 µs before a low NMI will be generated. In this way, power supply noise is removed from the monitoring function, preventing false inter- rupts. During a power–up, any detected IN pin levels below VTP by the comparator are disabled from gener- ating an interrupt until VCC rises to VCCTP . As a result, any potential NMI pulse will not be initiated until VCC reaches VCCTP . Connecting NMI to PBRST would allow non–maskable interrupt to generate an automatic reset when an out– of–tolerance condition occurred in a monitored supply. An example is shown in Figure 3. Watchdog Timer The watchdog timer function forces WDS signals active when the ST input is not clocked within the 1 second time out period. Timeout of the watchdog starts when RST (or RST) becomes inactive. If a high–to–low transi- tion occurs on the ST input pin prior to time–out, the watchdog timer is reset and begins to time–out again. If the watchdog timer is allowed to time out, the WDS sig- nal is driven active (low) for a minimum of 130 ms. The ST input can be derived from many microprocessor out- puts. The typical signals used are the microprocessors address signals, data signals, or control signals. When the microprocessor functions normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to time–out. To guarantee that the watchdog timer does not time–out, a high–to–low transition must occur at or less than the minimum watchdog time–out of 1 second. A typical circuit example is shown in Figure 6.

MICROMONITOR BLOCK DIAGRAM Figure 1 T.C. REFERENCE DIGITAL SAMPLER DIGITAL SAMPLER DIGITAL DELAY WATCHDOG STATUS LATCH LEVEL SENSE AND DEBOUNCE IN VCC PBRST ST NMI RST WDS RST DS1706_/A/R/S/T DS1706L/DS1706P PUSH–BUTTON RESET Figure 2 GND IN ALE RST ST RST PBRST VCC DS1706P WDS NMI 8051 µP PUSH–BUTTON RESET CONTROLLED BY NMI AND WDS Figure 3 GND IN ALE ST RST PBRST VCC DS1706 WDS NMI µP RSTUPSTREAM SUPPLY VOLTAGE

TIMING DIAGRAM: PUSHBUTTON RESET Figure 4 RST PBRST RST VIH tRST VIL tPDLY tPB VOH VOL NON–MASKABLE INTERRUPT CIRCUIT EXAMPLE Figure 5 GND IN ST RST PBRST VCC DS1706 WDS NMI TO µP VSENSE V SENSE R1 R2 R2 x1 . 2 5 V MAX V SENSE V TP xV CC Example: V SENSE = 4.50 volts at the trip point VCC = 3.3 volts 10KΩ = R2 Therefore:4.50 1.25 x3 . 3 12.4 volts maximum

4.5 R1 10K

10K x1 . 2 5 R 1 26K

VIN > 1.25V NMI VOL VOH VTP(MAX)VTP(MAX) VTP VTP VTP(MIN)VTP(MIN) tIPD tIPD DS1705/DS1706 011296 5/10 WATCHDOG TIMER Figure 6 GND IN ST RST PBRST VCC DS1706 WDS NMI Z80 µP RST DECODER ADDRESS BUS MREQ TIMING DIAGRAM: STROBE INPUT Figure 7 INDETERMINATE STROBE INVALID STROBE MIN. MAX. VALID STROBE ST tTD RST WDS RESET INITIATED BY PUSHBUTTON TIMING DIAGRAM: NON–MASKABLE INTERRUPT Figure 8

TIMING DIAGRAM: POWER DOWN Figure 9 RST SLEWS WITH V CC WDS SLEWS WITH V CC VOL VOH VCCTP(MIN) VCCTP(MAX) VCCTP tRPD tF VCC RST (DS1705 AND DS1706_/R/S/T) RST (DS1706L AND DS1706P ONLY) WDS

TIMING DIAGRAM: POWER UP Figure 10 RST (DS1705 AND DS1706_/R/S/T) RST (DS1706L AND DS1706P ONLY) RST RST VOH VOL tRPU VCCTP(MAX) VCCTP VCCTP(MIN) VCC WDS

ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Pin Relative to Ground –0.5V to +7.0V Voltage on I/O Relative to Ground –0.5V to V CC + 0.5V Operating Temperature –40 °C to +85°C Storage Temperature –55 °C to +125°C Soldering Temperature 260 °C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (–40°C to +85°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage VCC 1.0 5.5 V 1 ST and PBRST Input High Level VIH 2.0 VCC –0.5 VCC +0.3 V 1, 3 1, 4 ST and PBRST Input Low Level VIL –0.03 +0.5 V 1 DC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCC =1.2V to 5.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES VCC Trip Point DS1705/DS1706L VCCTP 4.50 4.65 4.75 V 1 VCC Trip Point DS1706 VCCTP 4.25 4.40 4.50 V 1 VCC Trip Point DS1706T VCCTP 3.00 3.08 3.15 V 1 VCC Trip Point DS1706S VCCTP 2.85 2.93 3.00 V 1 VCC Trip Point DS1706P or R VCCTP 2.55 2.63 2.70 V 1 Input Leakage IIL –1.0 +1.0 µA 2 Output Current @ 2.4 volts IOH 350 µA 3 Output Current @ 0.4 volts IOL 10 mA 3 Output Voltage @ –500 µA VOH VCC +–0.3 VCC –0.1 V 3 Operating Current @ V CC < 5.5 volts ICC 60 µA 5 Operating Current @ V CC < 3.6 volts ICC 50 µA 5 IN Input Trip Point VTP 1.20 1.25 1.30 V 1 CAPACITANCE (tA=25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C IN 5 pF Output Capacitance C OUT 7 pF

AC ELECTRICAL CHARACTERISTICS (–40°C to +85°C; VCC =1.2V to 5.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES PBRST = VIL tPB 150 ns Reset Active Time tRST 130 205 285 ms ST Pulse Width tST 10 ns 6 VCC Detect to RST and RST tRPD 5 8 µs 9 VCC Slew Rate tF 20 µs VCC Detect to RST and RST tRPU 130 205 285 ms 7 VCC Slew Rate tR 0 ns PBRST Stable Low to RST and RST tPDLY 250 ns Watchdog Timeout tTD 1.0 1.6 2.2 s 8 VIN Detect to NMI tIPD 5 8 µs 9 NOTES: 1. All voltages are referenced to ground. 2. PBRST is internally pulled up to VCC with an internal impedance of 40KΩ typical and the ST input is internally pulled up to VCC with an internal impedance of 180KΩ typical. 3. VCC 2.4 volts 4. VCC < 2.4 volts 5. Measured with outputs open and all inputs at VCC or ground. 6. Must not exceed tTD minimum. 7. tR = 5 µs 9. Noise immunity – pulses < 2 µs at V CCTP minimum will not cause a reset.

8–PIN µ–SOP (118 MIL) 1234 8765 ABCD WWY A, B, C and D represents the device type and tolerance. ABCD 705_ – DS1705 706_ – DS1706 706L – DS1706L 706P – DS1706P 706R – DS1706R 706S – DS1706S 706T – DS1706T WWY represents the device manufacturing W ork W eek, Year.