DS1558 DALLAS | Alldatasheet
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Technical content
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FEATURES
/g167/g32Integrated real-time clock (RTC), power-fail control circuit, and NV RAM controller /g167/g32Clock registers are accessed identically to the static RAM; these registers are resident in the 16 top RAM locations /g167/g32Century register /g167/g32Greater than 10 years of timekeeping and data retention in the absence of power with small lithium coin cell(s) and low-leakage SRAM /g167/g32Precision power-on reset /g167/g32Programmable watchdog timer and RTC alarm /g167/g32BCD-coded year, month, date, day, hours, minutes, and seconds with automatic leap- year compensation valid up to the year 2100 /g167/g32Battery voltage-level indicator flag /g167/g32Power-fail write protection allows for /g17710% V CC power-supply tolerance /g167/g32Underwriters Laboratory (UL) recognized
ORDERING INFORMATION
CC (V) TOP MARK DS1558Y 48 TQFP 5 DS1558B DS1558W 48 TQFP 3.3 DS1558D PIN CONFIGURATION Package Dimension Information: www.maxim-ic.com/DallasPackInfo PIN DESCRIPTION A0–A18 - Address Input DQ0–DQ7 - Data Input/Outputs IRQ /FT - Interrupt, Frequency-Test Output (Open Drain) RST - Power-On Reset Output (Open Drain) CE - Chip-Enable Input CER - Chip-Enable RAM OE - Output-Enable Input OER - Output-Enable RAM WE - Write Enable VCC - Power-Supply Input VCCO - V CC Out to RAM GND - Ground N.C. - No Connection X1, X2 - Crystal Connection V BAT1 - +3V Battery Input VBAT2 - +3V Battery Input DS1558 Watchdog Clock with NV RAM Control www.maxim-ic.com A18 A16 A12 A14 N.C. VCCO VCC N.C. A17 GND RST NC N.C. DQ0 DQ1 DQ2 DQ6 VBAT1 WE IRQ/FT OE A10 CE GND VBAT2 A15 A13 OER A11 37CE R DQ7 DQ5 DQ4 DQ3 GND DS1558 X2 N.C. TQFP TOP VIEW
DESCRIPTION
The DS1558 is a full function, year 2000-compliant (Y 2KC), real-time clock/ calendar with an RTC alarm, watchdog timer, power-on reset, battery monitor, and NV SRAM controller. User access to all registers within the DS1558 is accomplished with a byte-wide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for day of month and leap year are made automatically. The DS1558 maps the RTC registers into the SRAM address space and constantly monitors A0A18. When any of the upper 16 address loca tions are accessed, the DS1558 inhibits CER and OER to the SRAM, and redirects reads and write s to the RTC registers within the DS1558. The DS1558 can be used with SRAMs up to 524,272 addresse s. Smaller SRAMs can be use d, provided that the unused upper address lines on the DS1558 are connected to VCC. The RTC registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external se t of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC information is always maintained. The DS1558 has interrupt ( IRQ /FT) and reset ( RST ) outputs that can be used to control CPU activity. The IRQ /FT interrupt output can be used to generate an external interrupt when the RTC register values match user-programmed alarm values. The interrupt is always available while the device is powered from the system supply, and it can be programmed to occu r when in the battery-backed state to serve as a system wake-up. The IRQ /FT output can also be used as a CPU watchdog timer. CPU activity is monitored and an interrupt or reset output are activated if the correct activity is not detected within
data security during unpredictable system operation brought on by low VCC levels. Figure 1. BLOCK DIAGRAM Note: Any unused upper address pins must be connected to VCC to properly address the RTC. or not a read or write cycle should be directed to the attached SRAM or to the RTC registers. DQ0–DQ7 – Data input/output pins for the RTC registers. requires an external pullup resistor. active. This pin is open drain and requires an external pullup resistor. CE – Chip-enable input that is used to access the RTC and the external SRAM.
CER Chip-enable RAM output. CE is passed through to CER , with an added propagation delay. When the signals on A0A18 match an RTC address, CER is held high, disabling the SRAM. If OE is also low, the RTC outputs data on DQ0DQ7. OE Output-enable input that is used to access the RTC and the external SRAM. OER Output-enable RAM output. OE is passed through to OER , with an added propagation delay. When the signals on A0A18 match an RTC address, CER is held high, disabling the SRAM. If CE is also low, the RTC outputs data on DQ0DQ7. WE Write-enable input that is used to write data to the RTC registers. VCC, GND DC power is provided to the device on these pins. V CC is the +5V input. When 5V (or 3.3V for the 3.3V version) is applied within normal limits, the device is fully accessible and data can be written and read. Reads and writes are inhibited when a 3V battery is connected to the device and V CC is V TP. However, the timekeeping function continues un affected by the lower input voltage. As V CC falls below VBAT, the RAM and RTC are switched over to the external power supply (nominal 3.0V DC) at VBAT. V CCO V CC output to RAM. While V CC is above V BAT, the external SRAM is powered by V CC. When VCC is below the battery level, the SRAM is powered by one of the VBAT inputs. N.C. No internal connection. X1, X2 Connections for a standard 32.768kHz quartz crys tal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (C L) of 6pF. For more information about crystal selection and cr ystal layout considerations, refer to Application Note 58 Crystal Considerations with Dalla s Real-Time Clocks. The DS1558 can al so be driven by an external 32.768kHz oscillator. In this configura tion, the X1 pin is connected to th e external oscillator signal and the X2 pin is floated. V BAT1, VBAT2 Battery inputs for any standard 3V lithium ce ll or other energy source. Battery voltage must be held between 2.5V and 3.7V for proper operation. UL recognized to ensure against reverse charging current when used with a lithium battery. If only one battery is used, it should be attached to V BAT1, and VBAT2 should be grounded. See Conditions of Acceptability at http://www.maxim-ic.com/TechSupport/QA/ntrl.htm
Table 1. OPERATING MODES (tOH), but then goes indeterminate until the next address access. transition on WE then disables the outputs tWEZ after WE goes active. The 5V device is fully accessible and data can be written and read only when V CC is greater than V PF. operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The battery lifetime is dependent on the RAM battery standby current and the DS1558 internal clock oscillator current. The total battery current is IOSC + ICCO. When VCC is above VPF, IBAT current is less than 50nA. The DS1558 has an internal circuit to prevent battery charging. No external protection components are required, and none should be used. The DS1558 has tw o battery pins that operate independently; the DS1558 selects the higher of the two inputs. If only one battery is used, the batte ry should be attached to VBAT1, and VBAT2 should be grounded. INTERNAL BATTERY MONITOR The DS1558 constantly monitors the ba ttery voltage of the internal ba ttery. The battery-low flag (BLF) bit of the flags register (B4 of 7FFF0h) is not writabl e and should always be a 0 when read. If a 1 is ever present, both battery inputs are below 1.8V and both the contents of the RTC and RAM are questionable. POWER-ON RESET A temperature-compensated comparator circuit monitors the level of V CC. When VCC falls to the power- fail trip point, the RST signal (open drain) is pulled low. When V CC returns to nominal levels, the RST signal continues to be pulled low for a period of 40ms to 200ms. The power-on reset function is independent of the RTC oscillator and thus is operational whether or not the oscillator is enabled.
Table 2 and the following paragraphs describe the operation of the RTC, alarm, and watchdog functions. Table 2. DS1558 REGISTER MAP monitoring the IRQ /FT pin for 512Hz. the recommended characteristics and following the recommended layout usually starts within 1 second.
When reading the RTC data, it is recommended to halt updates to the extern al set of double-buffered RTC registers. This puts the external registers into a sta tic state, allowing data to be read without register values changing during the read process. Normal update s to the internal registers continue while in this state. External updates are halted when a 1 is written into the read bit, B6 of the control register (7FFF8h). As long as a 1 remains in the control regist er read bit, updating is halted. After a halt is issued, the registers reflect the RTC count (day, date, and time) that was current at the moment the halt command is issued. Normal updates to the external set of registers resume within 1 second after the read bit is set to a 0 for a minimum of 500 /g109s. The read bit must be a 0 for a minimum of 500 /g109s to ensure the external registers are updated. SETTING THE CLOCK The MSB bit, B7, of the control register is the write bit. Setting the write bit to a 1, like the read bit, halts updates to the 7FFF8h7FFFFh registers. After setting the write bit to a 1, RTC registers can be loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to a 0 then transfers the values written to the internal RTC registers and allows normal operation to resume. CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is a dded by the crystal-frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast. Refer to Application Note 58 Crystal Considerations with Dallas Real-Time Clocks for detailed information. FREQUENCY TEST MODE The DS1558 frequency test mode uses the open-drain IRQ /FT output. With the oscillator running, the IRQ /FT output toggles at 512Hz when the FT bit is a 1, the alarm-flag enable bit (AE) is a 0, and the watchdog-enable bit (WDS) is a 1, or the watchdog register is reset (register 7FFF7h = 00h). The IRQ /FT output and the frequency test mode can be used as a measure of the actual frequency of the 32.768kHz RTC oscillator. The IRQ /FT pin is an open-drain output that requires a pullup resistor for proper operation. The FT bit is cleared to a 0 on power-up. USING THE CLOCK ALARM The alarm settings and control for the DS1558 reside within registers 7FFF2h7FFF5h. Register 7FFF6h contains two alarm-enable bits: alarm enable (AE) and alarm in backup enable (ABE). The AE and ABE bits must be set as described below for the IRQ /FT output to be activated for a matched alarm condition. The alarm can be programmed to activate on a specifi c day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the DS1558 is in the battery-backed state of operation to serve as a system wake-up. Alarm mask bits AM1AM4 control the alarm mode. Table 3 shows the possible settings. Configurations not listed in the table default to the once-per-second mode to notify the user of an incorrect alarm setting.
Figure 4. BACKUP MODE ALARM WAVEFORMS or the watchdog register (7FFF7h) is read or written. be initialized to a 0 if the watchdog function is enabled. All other bits are undefined.
ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground -0.3V to +6.0V Storage Temperature Range -55 /g176C to +125/g176C Soldering Temperature Range See IPC/JEDEC J-STD-020A *This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability. RECOMMENDED DC OPERATING CONDITIONS (VCC = 3.3V ±10% or 5V ±10%, TA = -40°C to +85°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 Voltage (All Inputs) VCC = +5V /g17710% V IH 2.2 V CC + 0.3V V 1 VCC = +3.3V /g17710% VIH 2.0 V CC + 0.3V V 1 Logic 0 Voltage (All Inputs) VCC = +5V /g17710% V IL -0.3 +0.8 1 VCC = +3.3V /g17710% VIL -0.3 +0.6 1 Battery Voltage V BAT 2.5 3.3 3.7 V
DC ELECTRICAL CHARACTERISTICS (VCC = +3.3V ±10% or +5V ±10%, TA = -40°C to +85°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current, +5V I CC 6 25 mA 2, 3 Active Supply Current, +3.3V I CC 4 15 mA 2, 3 TTL Standby, +5V (CE = VIH) ICC1 3 6 mA 2, 3 TTL Standby, +3.3V (CE = VIH) ICC1 2 6 mA 2, 3 CMOS Standby Current, +5V ( CE /g179/g32VCC - 0.2V) ICC2 2 6 mA 2, 3 CMOS Standby Current, +3.3V ( CE /g179/g32VCC - 0.2V) ICC2 1 2 mA 2, 3 Input Leakage Current (Any Input) IIL -1 +1 /g109A Output Leakage Current (Any Output) IOL -1 +1 /g109A Output Logic 1 Voltage (IOUT = -1.0mA) VOH 2.4 V 1 Output Logic 0 Voltage IOUT = 2.1mA, DQ0DQ7 Outputs VOL1 0.4 V IOUT = 7.0mA, IRQ /FT and RST Outputs VOL2 0.4 V 1, 5 Write Protection Voltage, +5V V PF 4.20 4.37 4.50 V 1 Write Protection Voltage, +3.3V V PF 2.75 2.88 2.97 V 1 Battery Switchover Voltage, +5V V SO V BAT V 1 Battery Switchover Voltage, +3.3V V SO V PF V 1, 4 Battery Current OSC On I OSC 0.3 0.5 µA 6,7 Battery Current OSC Off I BACKUP 100 nA 7 Output Voltage ICCO = 70mA, +5V V CC01 V CC1 - 0.3 V /g32 Output Voltage ICCO = 40mA, +3.3V V CC01 V CC1 - 0.3 V /g32 Output Voltage ICCO = 10µA V CC02 V BAT - 0.2 V BAT - 0.031 V /g32 10 CRYSTAL SPECIFICATIONS* PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Nominal Frequency F O 32.768 kHz Series Resistance ESR 45 k Ω Load Capacitance C L 6 pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58 Crystal Considerations for Dallas Real-Time Clocks for additional specifications.
Figure 5. READ CYCLE TIMING DIAGRAM
Figure 6. WRITE CYCLE TIMING, WRITE-ENABLE CONTROLLED
Figure 7. WRITE CYCLE TIMING, CHIP-ENABLE CONTROLLED
Figure 8. +5V POWER-UP/DOWN WAVEFORM TIMING
Figure 9. +3.3V POWER-UP/DOWN WAVEFORM TIMING
Output Load: 25pF Input Pulse Levels: 0V to +3V Timing Measurement Reference Levels: Input: +1.5V Output: +1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) Voltage referenced to ground. 2) Typical values are at +25 /g176C and nominal supplies. 3) Outputs are open. 4) Battery switchover occurs at the lowe r of either the battery voltage or VPF. 5) The IRQ /FT and RST outputs are open drain. 6) Using the recommended crystal on X1 and X2. 7) V CCO, CER , and OER pins open. 8) t AH1, tDH1 are measured from WE going high. 9) t AH2, tDH2 are measured from CE going high.