DS1553 DALLAS | Alldatasheet
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Technical content
1 of 19 REV: 022304 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. GENERAL DESCRIPTION The DS1553 is a full-function, year-2000-compliant (Y2KC) real-time clock/calendar (RTC) with an RTC alarm, watchdog timer, power-on reset, battery monitor, and 8k x 8 nonvolatile static RAM. User access to all registers within the DS1553 is accomplished with a bytewide interface as shown in Figure 1. The RTC registers contain century, year, leap year are made automatically.
ORDERING INFORMATION
*PowerCap required, must be ordered separately.
FEATURES
/g167/g32Integrated NV SRAM, RTC, Crystal, Power-Fail Control Circuit, and Lithium Energy Source /g167/g32Clock Registers are Accessed Identically to the Static RAM; These Registers are Resident in the 16 Top RAM Locations /g167/g32Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power /g167/g32Precision Power-On Reset /g167/g32Programmable Watchdog Timer and RTC Alarm /g167/g32BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid Up to the Year 2100 /g167/g32Battery Voltage Level Indicator Flag /g167/g32Power-Fail Write Protection Allows for /g17710% V CC Power-Supply Tolerance /g167/g32Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time PIN CONFIGURATIONS PART PIN-PACKAGE V CC (V) TOP MARK DS1553-100 28 EDIP 5.0 DS1553-100 DS1553-70 28 EDIP 5.0 DS1553-070 DS1553P-100 34 PowerCap® 5.0 DS1553P-100 DS1553P-70 34 PowerCap 5.0 DS1553P-70 DS1553W-120 28 EDIP 3.3 DS1553W-120 DS1553W-150 28 EDIP 3.3 DS1553W-150 DS1553WP-120 34 PowerCap 3.3 DS1553WP-120 DS1553WP-150 34 PowerCap 3.3 DS1553WP-150 DS9034PCX* — — DS9034PCX DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM www.maxim-ic.com PowerCap is a registered trademark of Dallas Semiconductor.
1 IRQ/FT
N.C. N.C. RST VCC WE OE CE DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 GND N.C. N.C. N.C. A12 A11 A10 34 N.C. X1 GND VBAT X2 34-Pin PowerCap Module Board (Uses DS9034PCX PowerCap) DS1553 28-Pin Encapsulated Package (700-mil Extended) VCC WE IRQ/FT A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 RST A12 DQ0 DQ1 DQ2 GND DS1553 TOP VIEW
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 2 of 19 PIN DESCRIPTION A0A12 - Address Input DQ0DQ7 - Data Input/Outputs IRQ /FT - Interrupt, Frequency Test Output (Open Drain) RST - Power-On Reset Output (Open Drain) CE - Chip Enable OE - Output Enable WE - Write Enable VCC - Power-Supply Input GND - Ground N.C. - No Connection DETAILED DESCRIPTION The RTC registers in the DS1553 are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assumin g the internal oscillator is turned on, the internal set of registers is continuously updated. This occurs re gardless of external registers settings to guarantee that accurate RTC information is always maintained. The DS1553 has interrupt ( IRQ /FT) and reset ( RST ) outputs that can be used to control CPU activity. The IRQ /FT interrupt output can be used to generate an external interrupt when the RTC register values match user-programmed alarm values. The interrupt is always available while the device is powered from the system supply, and it can be programmed to occu r when in the battery-backed state to serve as a system wakeup. Either the IRQ /FT or RST outputs can also be used as a CPU watchdog timer. CPU activity is monitored and an interrupt or reset output is activated if the correct activity is not detected within programmed limits. The DS1553 pow er-on reset can be used to detect a system power-down or failure and can hold the CPU in a safe reset state until normal power returns and stabilizes. The RST output is used for this function. The DS1553 also contains its own power-fail circuitry, which automatically deselects the device when the VCC supply enters an out-of-tolerance condition. This feature provides a high de gree of data security during unpredictable system operation brought on by low VCC levels. PACKAGES The DS1553 is available in a 28-pin DIP and a 34-pin PowerCap module. The 28-pin DIP module integrates the crystal, lithium energy source, and silicon in one package. The 34-pin PowerCap module board is designed with contacts for connection to a separate PowerCap (DS 9034PCX) that contains the crystal and battery. This design allows the Powe rCap to be mounted on top of the DS1553P after completion of the surface-mount process. Mountin g the PowerCap after the surface-mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap is keyed to prevent reverse insertion. Th e PowerCap module board and PowerCap are ordered separately and shipped in separate containers. The part number for the PowerCap is DS9034PCX.
Figure 1. Block Diagram Table 1. Operating Modes output data hold time (tOH) but will then go indeterminate until the next address access.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 4 of 19 transitioning low, the data bus can become active w ith read data defined by the address inputs. A low transition on WE will then disable the outputs tWEZ after WE goes active. DATA RETENTION MODE The 5V device is fully accessible, and data can be written and read only when V CC is greater than V PF. However, when VCC is below the power-fail point (VPF)the point at which write protection occursthe internal clock registers and SRAM are blocked from any access. When V CC falls below the battery switch point VSO (battery supply level), device power is switched from the VCC pin to the internal backup lithium battery. RTC operation and SRAM data are maintained from the battery until V CC is returned to nominal levels. The 3.3V device is fully accessible and da ta can be written and read only when V CC is greater than V PF. When VCC falls below V PF, access to the device is inhibited. If V PF is less than V SO, the device power is switched from V CC to the internal backup lithium battery when V CC drops below V PF. If V PF is greater than VSO, the device power is switched from V CC to the internal backup lithium battery when V CC drops below V SO. RTC operation and SRAM data are maintained from the battery until V CC is returned to nominal levels. All control, data, and address signals must be powered down when VCC is powered down. BATTERY LONGEVITY The DS1553 has a lithium power source that is design ed to provide energy for the clock activity and clock and RAM data retention when the V CC supply is not present. The capability of this internal power supply is sufficient to power the DS1553 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at +25 /g176C with the internal clock oscillator running in the absence of V CC. Each DS1553 is shipped from Dallas Semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. When V CC is first applied at a level greater than VPF, the lithium energy source is enabled for battery backup operation. INTERNAL BATTERY MONITOR The DS1553 constantly monitors the ba ttery voltage of the internal ba ttery. The Battery Low Flag (BLF) bit of the Flags register (B4 of 1FF0h) is not writeab le and should always be 0 when read. If a 1 is ever present, an exhausted lithium energy source is indicated, and both the contents of the RTC and RAM are questionable. POWER-ON RESET A temperature-compensated comparator circuit monitors the V CC level. When V CC falls to the power-fail trip point, the RST signal (open drain) is pulled low. When V CC returns to nominal levels, the RST signal continues to be pulled low for 40ms to 200ms. The power-on reset function is independent of the RTC oscillator and is therefore operational whether or not the oscillator is enabled.
Table 2 and the following paragraphs describe the operation of RTC, alarm, and watchdog functions. Table 2. Register Map state. External updates are halted when a 1 is written into the read bit, B6 of the Control register (1FF8h).
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 6 of 19 was issued. Normal updates to the external set of regi sters resume within 1 second after the read bit is set to 0 for a minimum of 500 /g109s. The read bit must be 0 for a minimum of 500 /g109s to ensure the external registers are updated. SETTING THE CLOCK The 8th bit, B7 of the Control register, is the write bit. Setting the write bit to 1, like the read bit, halts updates to the DS1553 (1FF8h1FFFh) registers. After setting the write bit to 1, RTC registers can be loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to 0 then transfers the values written to the internal RTC registers and allows normal operation to resume. CLOCK ACCURACY (DIP MODULE) The DS1553 is guaranteed to keep time accuracy to within /g1771 minute per month at +25 /g176C. The RTC is calibrated at the factory by Dalla s Semiconductor using nonvolatile tuning elements and does not require additional calibration. For this r eason, methods of field clock calib ration are not available and not necessary. The electrical environment also affects clock accuracy and caution should be taken to place the RTC in the lowest level EMI section of the PC board layout. For additional information, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks on our website at www.maxim-ic.com/appnoteindex.com. CLOCK ACCURACY (PowerCap MODULE) The DS1553 and DS9034PCX are each i ndividually tested for accuracy. Once mounted together, the module typically keeps time accuracy to within /g1771.53 minutes per month (35ppm) at +25°C. The electrical environment affects clock accuracy and caution should be taken to place the RTC in the lowest level EMI section of the PC board layout . For additional information, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks on our website at www.maxim- ic.com/appnoteindex.com. FREQUENCY TEST MODE The DS1553 frequency test mode uses the open-drain IRQ /FT output. With the oscillator running, the IRQ /FT output toggles at 512Hz when the FT bit is 1, the Alarm Flag Enable bit (AE) is 0, and the Watchdog Steering bit (WDS) is 1 or the Watchdog register is reset (Register 1FF7h = 00h). The IRQ /FT output and the frequency test mode can be used as a measure of the actual frequency of the 32.768kHz RTC oscillator. The IRQ /FT pin is an open-drain output that requires a pullup resistor for proper operation. The FT bit is cleared to 0 on power-up. USING THE CLOCK ALARM The alarm settings and control for the DS1553 reside within registers 1FF2h1FF5h. Register 1FF6h contains two alarm-enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE and ABE bits must be set as described below for the IRQ /FT output to be activated for a matched alarm condition. The alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the DS1553 is in the battery-backed state of operation to serve as a system wakeup. Alarm mask bits AM1AM4 control the alarm mode. Table 3 shows the possible settings. Configurations not listed in the table default to the once-per-second mode to notify the user of an incorrect alarm setting.
Figure 4. Backup Mode Alarm Waveforms Watchdog Flag (WF) is read or the Watchdog register (1FF7) is read or written. IRQ /FT output when the watchdog times out. activated, the watchdog function prevails and the frequency test function is denied.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 9 of 19 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.3V to +6.0V Storage Temperature Range -40 /g176C to +85/g176C Soldering Temperature 260°C for 10 seconds (DIP Package) (Note 8) See IPC/JEDEC Standard J-STD-020A for Surface Mount Devices This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. OPERATING RANGE Range Temperature V CC Commercial 0°C to +70°C 3.3V /g17710% or 5V /g17710% RECOMMENDED DC OPERATING CONDITIONS (Over the operating range) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 Voltage All Inputs VCC = 5V ±10% VIH 2.2 VCC x +0.3V V 1 VCC = 3.3V ±10% V IH 2.0 VCC x +0.3V V 1 Logic 0 Voltage All Inputs VCC = 5V ±10% VIL -0.3 +0.8 1 VCC = 3.3V ±10% V IL -0.3 +0.6 1 DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, over the operating range.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current I CC 15 50 mA 2, 3 TTL Standby Current (CE = VIH) ICC1 1 3 mA 2, 3 CMOS Standby Current (CE /g179 VCC - 0.2V) ICC2 1 3 mA 2, 3 Input Leakage Current (Any Input) I IL -1 +1 /g109A Output Leakage Current (Any Output) I OL -1 +1 /g109A Output Logic 1 Voltage (IOUT = -1.0mA) VOH 2.4 V 1 Output Logic 0 Voltage (IOUT = 2.1mA, DQ0-7 Outputs); VOL1 0.4 V 1 (IOUT = 7.0mA, IRQ/FT and RST Outputs) VOL2 0.4 V 1, 5 Write Protection Voltage V PF 4.20 4.50 V 1 Battery Switchover Voltage V SO V BAT V 1, 4
Figure 5. Read Cycle Timing Diagram
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 11 of 19 READ CYCLE, AC CHARACTERISTICS (VCC = 5.0V ± 10%, over the operating range.) 70ns ACCESS 100ns ACCESS PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Read Cycle Time t RC 70 100 ns Address Access Time t AA 70 100 ns CE to DQ Low-Z tCEL 5 5 ns CE Access Time tCEA 70 100 ns CE Data Off Time tCEZ 25 35 ns OE to DQ Low-Z tOEL 5 5 ns OE Access Time tOEA 35 55 ns OE Data Off Time tOEZ 25 35 ns Output Hold from Address t OH 5 5 ns READ CYCLE, AC CHARACTERISTICS (VCC = 3.3V ±10%, over the operating range.) 120ns ACCESS 150ns ACCESS PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Read Cycle Time t RC 120 150 ns Address Access Time t AA 120 150 ns CE to DQ Low-Z tCEL 5 5 ns CE Access Time tCEA 120 150 ns CE Data Off Time tCEZ 40 50 ns OE to DQ Low-Z tOEL 5 5 ns OE Access Time tOEA 100 130 ns OE Data Off Time tOEZ 35 35 ns Output Hold from Address t OH 5 5 ns WRITE CYCLE, AC CHARACTERISTICS (VCC = 5.0V ±10%, over the operating range.) 70ns ACCESS 100ns ACCESS PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES Write Cycle Time t WC 70 100 ns Address Access Time t AS 0 0 ns WE Pulse Width tWEW 50 70 ns CE Pulse Width tCEW 60 75 ns Data Setup Time t DS 30 40 ns Data Hold time t DH 0 0 ns Address Hold Time t AH 5 5 ns WE Data Off Time tWEZ 25 35 ns Write Recovery Time t WR 5 5 ns
Figure 8. Power-Up/Down Waveform Timing 5V Device
Figure 9. Power-Up/Down Waveform Timing 3.3V Device
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 15 of 19 AC TEST CONDITIONS Output Load: 100 pF + 1TTL Gate Input Pulse Levels: 0.0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) Voltage referenced to ground. 2) Typical values are at +25 /g176C and nominal supplies. 3) Outputs are open. 4) Battery switch over occurs at the lowe r of either the battery voltage or V PF. 5) The IRQ /FT and RST outputs are open drain. 6) Data retention time is at +25 /g176C. 7) Each DS1553 has a built-in switch that disconnects the lithium source until V CC is first applied by the user. The expected tDR is defined for DIP modules as a cumulative time in the absence of V CC starting from the time power is first applied by the user. 8) Real Time Clock Modules (DIP) can be successf ully processed through conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 /g176C. Post solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used. In addition, for the PowerCap: a. Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflow oriented with the label side up (live-bug). b. Hand soldering and touch-up: Do not touch or a pply the soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflow and use a solder wick to remove solder.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 16 of 19
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PKG 28-PIN DIM MIN MAX A IN. MM 1.470 37.34 1.490 37.85 B IN. MM 0.675 17.75 0.740 18.80 C IN. MM 0.315 8.51 0.335 9.02 D IN. MM 0.075 1.91 0.105 2.67 E IN. MM 0.015 0.38 0.030 0.76 F IN. MM 0.140 3.56 0.180 4.57 G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.590 14.99 0.630 16.00 J IN. MM 0.010 0.25 0.018 0.45 K IN. MM 0.015 0.43 0.025 0.58
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 17 of 19 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) DS1553P PKG INCHES DIM MIN NOM MAX A 0.920 0.925 0.930 B 0.980 0.985 0.990 C 0.080 D 0.052 0.055 0.058 E 0.048 0.050 0.052 F 0.015 0.020 0.025 G 0.025 0.027 0.030 NOTE: Dallas Semiconductor recommends that PowerCap Module bases experience one pass through solder reflo w oriented with the label side up (live-bug). Hand Soldering and Touch-Up: Do not touch or apply the soldering iron to leads for more than 3 seconds. To solder, apply flux to the pad, heat the lead frame pad and apply solder. To remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM 18 of 19 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) DS1553P WITH DS9034PCX ATTACHED PKG INCHES DIM MIN NOM MAX A 0.920 0.925 0.930 B 0.955 0.960 0.965 C 0.240 0.245 0.250 D 0.052 0.055 0.058 E 0.048 0.050 0.052 F 0.015 0.020 0.025 G 0.020 0.025 0.030
DS1553 64kB, Nonvolatile, Year-2000-Compliant Timekeeping RAM Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Ma xim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specification s without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2003 Maxim Integrated Products /g183 Printed USA 19 of 19 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) Recommended PowerCap Module Land Pattern INCHES PKG DIM MIN NOM MAX A 1.050 B 0.826 C 0.050 D 0.030 E 0.112