DS1481

DS1481 DALLAS | Alldatasheet

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Technical content

1–Wire Bus Master with Overdrive DS1481 PRELIMINARY 021798 1/10

FEATURES

• Provides a synchronous interface to Dallas Semicon- ductor 1–wire devices
• Compatible with low power parallel ports
• Can be cascaded with other DS1481’s
• Allows print spooler and other processes to run during 1–wire I/O
• Provides high speed communcation with overdrive capable devices
• Space saving 14–pin (150 mil), SOIC package PIN ASSIGNMENT D/CLK O2/BSY2 O1/BSY1 RES ENOENI VCC 1 I/O NC NC GNDNC 14–PIN SOIC (150 MIL) PIN DESCRIPTION VCC – Supply ENI – Enable In D/CLK – Data/Clock RES – Reset O1/BSY1 – Output 1/Busy 1 O2/BSY2 – Output 2/Busy 2 GND – Ground I1 – Input 1 I2 – Input 2 I/O – 1–wire I/O ENO – Enable Out NC – No Connect

DESCRIPTION

The DS1481 is a dedicated 1–wire timing generator. The device is normally used in conjunction with a paral- lel port controller to provide the necessary interface to the host processor. Busy signals allow the host proces- sor to perform other tasks while 1–wire “time–slots” are completed. The DS1481 also saves the state of D/CLK and RES allowing print spoolers to operate without affecting 1–wire communication. DS1481 based devices can be cascaded. The first device’s O1/BSY1 and O2/BSY2 connect to the PC printer port’s BUSY and SELECT OUT signals (pins 11 and 13 respectively). The next DS1481 connects its O1/BSY1 and O2/BSY2 to the first device’s I1 and I2 respectively. ENO of the first device connects to ENI of the second device. More DS1481’s can be stacked in a similar manner. The last devices I1 and I2 connect to BUSY and SELECT of the attached printer. The DS1481’s 3–volt operation insures compatibility with most low power parallel ports (i.e., portable com- puters).

When OD = 1, communication with the 1–wire device is exactly as described in the operation section above. The actual 1–wire timing for both modes of operation is described in Figures 4, 5 and 6. Note that when toggling the OD bit there is no change on the I/O line. PRINTER COEXISTENCE In order to coexist with parallel port printers, the DS1481 utilizes two input pins (I1 and I2) and two output pins (O1/BSY1 and O2/BSY2). When ENI is low these pins are used for transmitting data received on the I/O pin or for issuing an unmistakable busy signal. When ENI is inactive (high) O1/BSY1 and O2/BSY2 propagate the states of I1 and I2. If a printer is attached to a DS1481, I1 is connected to the printers BUSY signal (low only if printer is on line and busy), and I2 is connected to SELECT OUT (driven low if printer is off line), see Figure 2. If the attached printer is “powered up” and on line, the DS1481 uses SELECT OUT for communication regard- less of the state of the printers BUSY signal. If the printer is off line its BUSY signal is inactive (high) and this line is used by the DS1481 for host communication. If the attached printer is powered off, both SELECT OUT and BUSY will be low. This prevents meaningful com- munication with the DS1481 because it is unable to de– assert its busy signal (O1/BSY1 and O2/BSY2 low) or return a high sample of the I/O pin. To solve this problem, the DS1481 uses the busy signal issued during a reset to detect the presence of another DS1481 based device attached behind it on the parallel port. If this busy signal is not detected by the DS1481, it assumes that it is the last DS1481 based device on the port. If the DS1481 determines that it is the last device on the port it ignores the states of its I1 and I2 pins while ENI is low. It also leaves the ENO pin high to prevent sending line feed signals to the printer. This gives the last device the ability to control O1/BSY1 and O2/BSY2 without affecting stackability. EPP/ECP TRANSPARENT MODE When the DS1481 first powers up it is in a transparent mode in which the three signal lines (auto line feed, busy and select) that pass through the part are directly con- nected by transmission gates. This allows bi–direc- tional printers (or other parallel port peripherals) to com- municate in either the EPP or ECP mode of the PC parallel port. The DS1481 pin sets connected are as fol- lows: ENI ENO O1/BSY1 I1 O2/BSY2 I2 1–wire communication using the DS1481 is impossible in transparent mode. To toggle to normal mode four consecutive overdrive toggle commands must be issued. If this sequence has been issued and the ENI pin remains high for at least 10 ms the part will enter its normal mode of operation. Note that any other 1–wire time slot command issued during the sequence resets the sequence. The steps needed to return to transpar- ent mode are as described above with the exception that no additional wait is required at the end of the four overdrive toggles to enter transparent mode. While in transparent mode if the DS1481 detects that the ENO pin has been held low for more than 10 ms it turns off the transmission gate connecting ENI and ENO . This guarantees the host will have the ability to take the DS1481 out of transparent mode and perform 1–wire I/O operations.

DS1481 FUNCTIONAL BLOCK DIAGRAM Figure 1 DQ CLK Q DQ CLK Q LAST PART DETECTION 1–WIRE BUS OD 1–WIRE BUS MASTER I/O ENI D/CLK RES O1/BSY1 O2/BSY2 ENO

CONNECTION TO PC TYPE PARALLEL PORTS Figure 2 VCC ENI O1/BSY1 O2/BSY2 D/CLK RES NC I/O ENO NC NC GND P14 P11 P13 P14 P11 P13 TO PRINTER OR ANOTHER PARALLEL PORT RESIDENT DEVICE P18TO HOST DS9100 CONNECTION TO MICROCONTROLLERS Figure 3 VCC ENI O1/BSY1 O2/BSY2 D/CLK RES NC I/O ENO NC NC GND P1.0 P1.1 P1.2 P1.3 +5DS80C320 DS9100

TIMING DIAGRAM: HOST INTERFACE Figure 4 tBLB ENI D/CLK RES O1/BSY1 O2/BSY2 READ 0 (I/O) READ 1 (I/O) WRITE 1 (I/O) tSIO tSIO = 8 µs (TYPICAL), tBLB = 60 µs (MINIMUM) tSIO = 2 µs (MAXIMUM), tBLB = 6 µs (MINIMUM) (OD = 0) (OD = 1) VALID VALID READ O, READ 1, WRITE 1 BIT TIME SLOTS TIMING DIAGRAM: HOST INTERFACE Figure 5 tBLB ENI D/CLK RES O1/BSY1 O2/BSY2 WRITE 0 (I/O) tBLB = 60 µs (MINIMUM) tBLB = 6 µs (MINIMUM) (OD = 0) (OD = 1) VALID VALID WRITE 0 TIME SLOT

TIMING DIAGRAM: HOST INTERFACE Figure 6 tBLR ENI D/CLK RES O1/BSY1 O2/BSY2 RESET (I/O) tPDH = 2 µs (TYPICAL) tBLR = 960 µs (MINIMUM) tBLB = 96 µs (MINIMUM) (OD = 0) (OD = 1) VALID VALID 1–WIRE RESET TIMING DIAGRAM: HOST INTERFACE Figure 7 ENI D/CLK RES O1/BSY1 O2/BSY2 VALID VALID TOGGLE OVERDRIVE MODE

Vcc DC supply voltage. ENI I Chip enable, driven low to begin 1–wire I/O. O1/BSY1 O Driven low during time slot (to indicate a DS1481 busy condition). Set to state of I1 after time slot has finished. O1/BSY1 will go low after D/CLK goes low if sample of I/O communication was low. Returns to state of I1 when ENI goes back high (see Figure 1). O2/BSY2 O Driven low during time slot (to indicate a DS1481 busy condition). Set to state of I2 after time slot has finished. O2/BSY2 will go low after D/CLK goes low if sample of I/O communication was low. Returns to state of I2 when ENI goes back high (see Figure 1). D/CLK I Data/Clock pin. Used to specify type of time slot before communication begins. After the time slot has been completed this pin is driven low in order to solicit the result of the time slot. RES I Set low (before ENI is driven low) to specify that a reset pulse should be gener- ated on the I/O pin. GND System ground. I1 I Can be connected to the O1/BSY1 of another DS1481. May also be connected to parallel port printer’s BUSY signal. Internally pulled high via a weak resistor. I2 I Can be connected to the O2/BSY2 of another DS1481. Can also be connected to a parallel port printer SELECT OUT signal. Internally pulled high via a weak resistor. ENO O Set to ENI if not the last part on port. Open drain output with weak internal pull–up resistor. I/O I/O 1–wire I/O line. Bi–directional line with open drain output.

ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to ground –1.0V to +7.0V Operating temperature 0 C to 70C Storage temperature –55 C to +125C Soldering temperature 260 C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0C to 40C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Logic 1 VIH 2.4 VCC + 0.3 V 1 Logic 0 VIL –0.3 +0.8 V 1 Supply VCC 2.7 5.0 5.5 V 1 DC ELECTRICAL CHARACTERISTICS (0C to 40C; 2.7 ≤ VCC ≤ 5.5) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage IIL –1 +1 µA 5 Output Leakage ILO –1 +1 µA VOL @ ISINK = –2 mA 0.4 V I1 pull–up resistance ZI1 50 KΩ I2 pull–up resistance ZI2 50 KΩ ENI pull–up resistance ZENI 50 KΩ ENO pull–up resistance ZENO 50 KΩ D/CLK Pull–Up resistance ZDC 50K RES Pull–Up resistance ZR 50K Active Current ICC 500 µA 2 Available I/O Current II/O 40 mA 6

AC ELECTRICAL CHARACTERISTICS: HOST INTERFACE PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Sample Time (for bit time slot, OD = 0) (for bit time slot, OD = 1) tSIO 8 µs Recovery Time tREC 1 µs Data to Enable Hold tDE 40 µs Reset to Enable Hold tRE 40 ns Clock low time tCL 200 ns Clock low to O1, O2 valid tCOV 200 ns BSY1, BSY2 low time (for bit time slot, OD = 0) (OD = 1) tBLB 60 µs 3 BSY1, BSY2 low time (for reset time slot, OD = 0) (OD = 1) tBLR 960 µs 4 NOTES: 1. All voltages are referenced to ground. 2. Measured with outputs open and I1, I2 high. 3. Minimum time required for 1–wire bit time slot. 4. Minimum time required for 1–wire reset time slot. 5. Only pins without pull–ups. 6. Overdrive mode only.