DS14287+

DS14285_05 DALLAS | Alldatasheet

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FEATURES

ƒ Direct Replacement for IBM AT Computer Clock/Calendar ƒ Functionally Compatible with the DS1285/DS1287 ƒ Available as Chip (DS14285, DS14285S, or DS14285Q) or Stand-Alone Module with Embedded Lithium Battery and Crystal (DS14287) ƒ Automatic Backup Supply and Write Protection to Make External SRAM Nonvolatile ƒ Counts Seconds, Minutes, Hours, Days, Day of the Week, Date, Month, and Year with Leap Year Compensation Valid Up to 2100 ƒ Binary or BCD Representation of Time, Calendar, and Alarm ƒ 12- or 24-Hour Clock with AM and PM in 12-Hour Mode ƒ Daylight Saving Time Option ƒ Multiplex Bus for Pin Efficiency ƒ Interfaced with Software as 128 RAM Locations

14 Bytes of Clock and Control Registers

114 Bytes of General Purpose RAM

ƒ Programmable Square-Wave Output Signal ƒ Bus-Compatible Interrupt Signals (IRQ) ƒ Three Interrupts are Separately Software- Maskable and Testable Time-of-Day Alarm Once/Second to Once/Day Periodic Rates from 122µs to 500ms End of Clock Update Cycle ƒ Optional Industrial Temperature Version Available: DS14285 DIP, SO, and PLCC PIN CONFIGURATIONS DS14285/DS14287 Real-Time Clock with NV RAM Control Control www.maxim-ic.com PLCC AD0 AD1 AD2 AD3 AD4 AD5 CEI VBAT IRQ RESET DS GND N.C. R/W MOT VCCO VCC SQW CE0 AD6 N.C. AD7 GND CS AS N.C. 4 3 2 1 28 27 26 12 13 14 15 16 17 18 N.C. AD1 AD3 AD4 AD5 AD6 AD7 GND VCC SQW CEO CEI N.C. IRQ RESET DS N.C. R/W AS CS N.C. AD0 AD2 V CCO Encapsulated Package DS14287 DS14285 DIP/SO AD1 AD3 AD4 AD5 AD6 AD7 GND VCC CEI VBAT IRQ RESET DS GND R/W AS CS AD0 AD2 SQW CEO VCCO DS14285 TOP VIEW

ORDERING INFORMATION

PART TEMP RANGE VOLTAGE (V) PIN-PACKAGE TOP MARK* DS14285 0°C to +70°C 5.0 24 DIP (0.600″) DS14285 DS14285+ 0°C to +70°C 5.0 24 DIP (0.600″) DS14285 DS14285N -40°C to +85°C 5.0 24 DIP (0.600″) DS14285N DS14285N+ -40°C to +85°C 5.0 24 DIP (0.600″) DS14285N DS14285Q 0°C to +70°C 5.0 28 PLCC DS14285Q DS14285Q+ 0°C to +70°C 5.0 28 PLCC DS14285Q DS14285QN -40°C to +85°C 5.0 28 PLCC DS14285QN DS14285QN+ -40°C to +85°C 5.0 28 PLCC DS14285QN DS14285S 0°C to +70°C 5.0 24 SO (0.300″) DS14285S DS14285S+ 0°C to +70°C 5.0 24 SO (0.300″) DS14285S DS14285SN -40°C to +85°C 5.0 24 SO (0.300″) DS14285SN DS14285SN+ -40°C to +85°C 5.0 24 SO (0.300″) DS14285SN DS14285SN/T&R -40°C to +85°C 5.0 24 SO (0.300″)/Tape & Reel DS14285SN DS14285SN+T&R -40°C to +85°C 5.0 24 SO (0.300″)/Tape & Reel DS14285SN DS14285S/T&R 0°C to +70°C 5.0 24 SO (0.300″)/Tape & Reel DS14285S DS14285S+T&R 0°C to +70°C 5.0 24 SO (0.300″)/Tape & Reel DS14285S DS14287 0°C to +70°C 5.0 24 EDIP (0.740″) DS14287 DS14287+ 0°C to +70°C 5.0 24 EDIP (0.740″) DS14287 + Denotes a lead-free/RoHS-compliant device. * A “+” anywhere on the top mark denotes a lead-free/RoHS-compliant device. An “N” denotes an industrial temperature grade device. PIN DESCRIPTION AD0-AD7 - Multiplexed Address/Data Bus NC - No Connection MOT - Bus Type Select (DS14285Q only) CS - Chip Select AS - Address Strobe R/ W - Read/Write Input DS - Data Strobe RESET - Reset Input IRQ - Interrupt Request Output SQW - Square Wave Output VCC - +5V Supply GND - Ground V CCO - RAM Power Supply Output CEI - RAM Chip Enable In CEO - RAM Chip Enable Out X1, X2 - 32.768 kHz Crystal Connections VBAT - +3V Battery Input

The DS14285/DS14287 Real Time Cloc k with NVRAM Control provides the industry standard DS1287 clock function with the additiona l feature of providing nonvolatile control for an external SRAM. Functions include a nonvolatile time -of-day clock, alarm, 100-year ca lendar, programmable interrupt, square wave generator, and 114 bytes of nonvolat ile static RAM. For the DS14287 a lithium energy source, quartz crystal, and write pr otection circuitry are contained with in a 24-pin dual in-line package. The DS14285 requires an external quartz crystal connected to the X1 and X2 pins as well as an external energy source connected to the VBAT pin. A standard 32.768 kHz quartz crystal can be directly connected to the DS14285 via pins 1 and 2 (X1, X2). The crysta l selected for use should have a specified load capacitance (C L) of 6 pF. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations with Dallas Real-time Clocks.” The DS14285/DS14287 uses its backup energy source and ba ttery-backup controller to make a standard CMOS static RAM nonvolatile du ring power-fail conditions. Duri ng power fail, the DS14285/DS14287 automatically write-protects the external SRAM and provides a V CC output sourced from its internal battery. For the DS14287 the internal lithium cell is electri cally isolated from the clock and memory when shipped from the factory. This isolation is removed after the first application of V CC, allowing the lithium cell to provide data retention to the clock, internal RAM, V CCO and CEO on subsequent power-downs. Care must be taken after this isolation has been br oken to avoid inadvertently discharging the lithium cell through the VCCO and CEO pins. OPERATION The block diagram in Figure 1 shows the pin connec tions with the major internal functions of the DS14285/DS14287. The following paragraphs describe the function of each pin. SIGNAL DESCRIPTIONS GND, VCC - DC power is provided to the device on these pins. VCC is the +5 volt input. SQW (Square Wave Output) - The SQW pin can output a signal from one of 13 taps provided by the 15 internal divider stages of the real time clock. The frequency of the SQW pin can be changed by programming Register A as shown in Table 1. The SQW signal can be turned on and off using the SQWE bit in Register B. The SQW signal is not available when V CC is less than 4.25 volts typical. AD0-AD7 (Multiplexed Bi-directional Address/Data Bus) - Multiplexed buses save pins because address information and data information time-share the same signal paths. The addresses are present during the first portion of the bus cycle and the same pi ns and signal paths are used for data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the DS14285/DS14287 since the bus change from address to data occurs during the internal RAM access time. Addresses must be valid prior to the falling edge of AS/ALE, at which time the DS14285/DS14287 latches the address from AD0 to AD6. Valid write data must be present and held stable during the la tter portion of the DS or WR pulses. In a read cycle the DS14285/D S14287 outputs 8 bits of data during the latter portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance state as DS transitions low in the case of Motorola timing or as RD transitions high in the case of Intel timing.

MOT (Mode Select) - The MOT pin offers the flexibility to choose between to bus types. When connected to V CC, Motorola bus timing is selected. When c onnected to GND or left disconnected, Intel bus timing is selected. The pin has an intern al pull-down resistance of approximately 20 K Ω. This pin is on the DS14285Q only. AS (Address Strobe Input) - A positive going address strobe pulse serves to demultiplex the bus. The falling edge of AS/ALE causes the address to be latched within the DS14285/DS14287. DS (Data Strobe or Read Input) - For the DS14285Q the DS/ RD pin has two modes of operation depending on the level of the MOT pin. When the MOT pin is connected to V CC, Motorola bus timing is selected. In this mode DS is a positive pulse during th e latter portion of the bus cycle and is called Data Strobe. During read cycles, DS signifies the time th at the DS14285Q is to drive the bidirectional bus. In write cycles the trailing edge of DS causes the DS14285Q to latch the written data. When the MOT pin is connected to GND, Intel bus timing is selected. In this mode the DS pin is called Read( RD ). RD identifies the time period when the DS14285Q drives the bus with read data. The RD signal is the same definition as the Output Enable ( OE ) signal on a typical memory. The DS14285, DS14285S and DS14287 do not have a MOT pin and therefore operate only in Intel bus timing mode. W (Read/Write Input) - The R/ W pin also has two modes of operation. When the MOT pin is connected to V CC for Motorola timing, R/ W is at a level which indicates whether the current cycle is a read or write. A read cycle is indicated with a high level on R/ W while DS is high. A write cycle is indicated when R/ W is low during DS. When the MOT pin is connected to GND for Intel timing, the R/ W signal is an active low signal called WR . In this mode the R/ W pin has the same meaning as the Write Enable signal ( WE ) on generic RAMs. CS (Chip Select Input) - The Chip Select signal must be asserted low for a bus cycle in the DS14285/DS14287 to be accessed. CS must be kept in the active st ate during DS for Motorola timing and during RD and WR for Intel timing. Bus cycles whic h take place without asserting CS will latch addresses but no access will occur. When V CC is below 4.25 volts, th e DS14285/DS14287 internally inhibits access cycles by internally disabling the CS input. This action protects both the real time clock data and RAM data during power outages. IRQ (Interrupt Request Output) - The IRQ pin is an active low out put of the DS14285/DS14287 that can be used as an interrupt input to a processor. The IRQ output remains low as long as the status bit causing the interrupt is present and the correspo nding interrupt-enable bit is set. To clear the IRQ pin the processor program normally reads the C register. The RESET pin also clears pending interrupts. When no interrupt conditi ons are present, the IRQ level is in the high impedance state. Multiple interrupting devices can be connected to an IRQ bus. The IRQ bus is an open drain output and requires an external pull-up resistor.

RESET (Reset Input) - The RESET pin has no effect on the clock, calendar, or RAM. On power-up the RESET pin can be held low for a time in order to allo w the power supply to stabilize. The amount of time that RESET is held low is dependent on the application. However, if RESET is used on power-up, the time RESET is low should exceed 200 ms to make sure th at the internal timer that controls the DS14285/DS14287 on power-up has timed out. When RESET is low and V CC is above 4.25 volts, the following occurs: A. Periodic Interrupt Enable (PEI) bit is cleared to 0. B. Alarm Interrupt Enable (AIE) bit is cleared to 0. C. Update Ended Interrupt Flag (UF) bit is cleared to 0. D. Interrupt Request Status Fl ag (IRQF) bit is cleared to 0. E. Periodic Interrupt Flag (PF) bit is cleared to 0. F. The device is not accessible until RESET is returned high. G. Alarm Interrupt Flag (AF) bit is cleared to 0. H. IRQ pin is in the high impedance state. I. Square Wave Output Enable ( SQWE ) bit is cleared to 0. J. Update Ended Interrupt Enable (UIE) is cleared to 0. K. CEO is driven high. In a typical application RESET can be connected to VCC. This connection will allow the DS14287 to go in and out of power fail without affecting any of the control registers. CEI (External RAM Chip Enable Input, active low) - CEI should be driven low to enable the external RAM. CEI is internally pulled up with a 50kΩ resistor. CEO (External RAM Chip Enable Output, active low) - When VCC is greater than 4.25 volts (typical), CEO will reflect CEI provided the RESET is at a logic high. When V CC is less than 4.2 5 volts (typical), CEO will be forced to an inactive level regardless of CEI . VCCO (External RAM Power Supply Output) - VCCO provides the higher of V CC or V BAT through an internal switch to power an external RAM. DS14285 Only X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The inte rnal oscillator circuitry is designed for operation with a crysta l having a specified load capacitan ce (CL) of 6 pF. The crystal is connected directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal be guard–ringed with ground and that high frequency signal s be kept away from the crysta l area. For more information on crystal selection and crystal layo ut considerations, please consu lt Application Note 58, “Crystal Considerations with Dallas Real Time Clocks.” V BAT – Battery input for any standard 3-volt lithium cell or other energy source. See the Power-Up/Down section for considerations in selecting the size of the external energy source

Laboratories for UL listing. Figure 1. DS14285/DS14287 Block Diagram

POWER-DOWN/POWER-UP CONSIDERATIONS The real time clock function will c ontinue to operate and all of th e RAM, time, calendar, and alarm memory locations remain nonvolatile regardless of the level of the VCC input. When VCC is applied to the DS14285/DS14287 and reaches a level of greater than 4.25 volts (typical), the device becomes accessible after 200 ms, provided that the oscillator is running and the oscillator countdown chain is not in reset (see Register A). This time period allows the system to stabilize after power is applied. When V CC falls below 4.25 volts (typical), the chip select input is internally forced to an inactive level regardless of the value of CS at the input pin. The DS14285/DS14287 is, theref ore, write-protected. When the DS14285/DS14287 is in a write-protected state, all inputs are ignore d and all outputs are in a high impedance state. When VCC falls below a level of approximately 3 volts, the external V CC supply is switched off and an internal lithium energy source supplies power to the Real-time Clock and the RAM memory. An external SRAM can be made nonvolatile by using the V CCO and SRAM chip enable pins (see Figure 1). Nonvolatile control of the external SRAM is analogous to that of the real time clock registers. When VCC slews down during a power fail, CEO is driven to an inactive level regardless CEI . This write protection occurs when VCC is less than 4.25 volts (typical). During power up, when V CC reaches a level of greater than 4.25 volts (typical), CEO will reflect CEI after 200 ms. During power-valid operation, the CEI input is passed to the CEO output with a propagation delay of less than 10 ns. When V CC is above a level of approximately 3V, the external SRAM will be powered by V CC through the VCCO pin. When V CC is below a level of approximately 3V, th e external SRAM will be powered by the internal lithium cell through the V CCO pin. An internal comparator and switch determine whether V CCO is powered by VCC or the internal lithium cell. When the device is in battery backup m ode, the energy source connected to the V BAT pin in the case of the DS14285, or the internal lithium cell in the case of the DS14287 can power an external SRAM for an extended period of time. The amount of time that the lithium cell can supply power to the external SRAM is a function of the data retention current of the SRAM. The capacity of the lithium cell that is encapsulated within the DS14287 module is 130 mAh. If an SRAM with a data retention current of less than 1 µA is used and the oscillator cu rrent is 300 nA (typical ), the cumulative data retention time is calculated at more than 11 years.

1. Registers C and D are read-only.
2. Bit 7 of Register A is read-only.
3. The high order bit of the seconds byte is read-only.

The contents of four registers (A,B,C, and D) are described in the “Registers” section. Figure 2. DS14285/DS14287 Address Map

time and calendar reads are covered later in this text. create an interrupt every second. Table 1. Time, Calendar, and Alarm Data Modes

0 Seconds 0-59 00-3B 00-59

1 Seconds Alarm 0-59 00-3B 00-59

2 Minutes 0-59 00-3B 00-59

3 Minutes Alarm 0-59 00-3B 00-59

6 Day of the Week

7 Date of the Month 1-31 01-1F 01-31

8 Month 1-12 01-0C 01-12

9 Year 0-99 00-63 00-99

The DS14285/DS14287 has four control re gisters that are accessible at a ll times, even during the update cycle. REGISTER A MSB LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0 UIP - The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, the update transfer will soon occur. When UIP is a 0, the upd ate transfer will not occur for at least 244 µs. The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit is read-only and is not affected by RESET . Writing the SET bit in Register B to a 1 inhibits any update transfer and clears the UIP status bit. DV0, DV1, DV2 - These 3 bits are used to tu rn the oscillator on or off and to reset the countdown chain. A pattern of 010 is the only combination of bits that will turn the oscillator on and allow the RTC to keep time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update will occur at 500 ms after a pattern of 010 is written to DV0, DV1, and DV2. RS3, RS2, RS1, RS0 - These four rate-selection bi ts select one of the 13 ta ps on the 15-stage divider or disable the divider output. The tap selected can be used to generate an output s quare wave (SQW pin) and/or a periodic interrupt. The user can do one of the following: 1. Enable the interrupt with the PIE bit; 2. Enable the SQW output pin with the SQWE bit; 3. Enable both at the same time and the same rate; or 4. Enable neither. Table 2 lists the periodic in terrupt rates and the square wave frequencies that can be chosen with the RS bits. These 4 read/write bits are not affected by RESET .

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 SET PIE AIE UIE SQWE DM 24/12 DSE SET - When the SET bit is a 0, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize the time and calendar bytes w ithout an update occurring in the midst of initializing. Read cycles can be executed in a similar manner. SET is a r ead/write bit that is not modified by RESET or internal functions of the DS14285/DS14287. PIE - The periodic interrupt enable PIE bit is a read/w rite bit which allows the Periodic Interrupt Flag (PF) bit in Register C to drive the IRQ pin low. When the PIE bit is se t to 1, periodic interrupts are generated by driving the IRQ pin low at a rate specif ied by the RS3-RS0 bits of Register A. A 0 in the PIE bit blocks the IRQ output from being driven by a periodic inte rrupt, but the Periodic Flag (PF) bit is still set at the periodic rate. PI E is not modified by any intern al DS14285/DS14287 functions, but is cleared to 0 on RESET . AIE - The Alarm Interrupt Enable (AIE) bit is a read/wri te bit which, when set to a 1, permits the Alarm Flag (AF) bit in register C to assert IRQ . An alarm interrupt occurs for each second that the 3 time bytes equal the 3 alarm bytes including a “don’t care” alarm code of binary 11XXXXXX. When the AIE bit is set to 0, the AF bit does not initiate the IRQ signal. The RESET pin clears AIE to 0. The internal functions of the DS14285/DS14287 do not affect the AIE bit. UIE - The Update Ended Interrupt Enable (UIE) bit is a read/write that enables the Update End Flag (UF) bit in Register C to assert IRQ . The RESET pin going low or the SET bit going high clears to UIE bit. SQWE - When the Square Wave Enable (SQWE) bit is se t to a 1, a square wave signal at the frequency set by the rate-selection bits RS3 th rough RS0 is driven out on a SQW pin. When the SQWE bit is set to 0, the SQW pin is held low; the state of SQWE is cleared by the RESET pin. SQWE is a read/write bit. DM - The Data Mode (DM) bit indicates whether time and calendar information is in binary or BCD format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is not modified by internal functions or RESET . A one in DM signifies binary data while a 0 in DM specifies Binary Coded Decimal (BCD) data. 24/12 - The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24-hour mode and a 0 indicates the 12-hour mode. This bit is read/write and is not affected by internal functions of RESET . DSE - The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These special updates do not occur when th e DSE bit is a 0. This bit is not affected by internal functions or RESET .

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 IRQF PF AF UF 0 0 0 0 IRQF - The Interrupt Request Flag (IRQF) bit is set to a 1 when one or more of the following are true: PF = PIE = 1 AF = AIE = 1 UF = UIE = 1 That is, IRQF = PF • PIE + AF • AIE + UF • UIE. Any time the IRQF bit is a 1, the IRQ pin is driven low. All flag bits are cleared after Register C is read by the program or when the RESET pin is low. PF - The Periodic Interrupt Flag (PF) is a read-only bit which is set to a 1 when an edge is detected on the selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1 independent of the state of the PIE bit. When both PF and PIE are 1s, the IRQ signal is active and will set the IRQF bit. The PF bit is cleared by a RESET or a software read of Register C. AF - A 1 in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm time. If the AIE bit is also a 1, the IRQ pin will go low and a one will appear in the IRQF bit. A RESET or a read of Register C will clear AF. UF - The Update Ended Interrupt Flag (UF) bit is set af ter each update cycle. When the UIE bit is set to 1, the 1 in UF causes the IRQF bit to be a 1 which will assert the IRQ pin. UF is cleared by reading Register C or a RESET . BIT 0 THROUGH BIT 3 - These are unused bits of the status Regi ster C. These bits always read 0 and cannot be written. REGISTER D MSB LSB BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 VRT 0 0 0 0 0 0 0 VRT - The Valid RAM and Time (VRT) b it indicates the condition of the internal battery (the battery connected to the V BAT pin in the case of the DS14285S, DS 14285, and the DS14285Q). This bit is not writable and should always be a 1 when read. If a 0 is ever present, an exhausted internal lithium energy source is indicated and both the cont ents of the RTC data and RAM data are questionable. This bit is unaffected by RESET . BIT 6 THROUGH BIT 0 - The remaining bits of Register D are not usable. They cannot be written and, when read, they will always read 0.

available during the update cycle. the DS14285/DS14287 and an external SRAM is illustrated in Figure 3. Figure 3. External SRAM Interface to the DS14285/DS14287 RTC described in greater detail in other sections of this text.

examined when read to ensure that no interrupts are lost. output intervals, or await the next needed software function. through 6 keep the oscillator off. Figure 1. The first purpose of selecting a divider tap is to generate a square wave output signal on the program control with the square wave enable bit (SQWE).

Table 2. Periodic Interrupt Rate and Square-Wave Output Frequency The DS14285/DS14287 executes an update cycle once per second regardless of the SET bit in Register B. before leaving the interrupt routine. to read valid time/calendar data to exceed 244 µs. data is not read during the update cycle.

Figure 4. Update-Ended and Periodic Interrupt Relationship

Soldering Temperature: Surface Mount:…………………………….See IPC/JEDEC Standard J-STD-020 This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. OPERATING RANGE RANGE TEMPERATURE V CC Commercial 0°C to +70°C 5V ±10% Industrial -40°C to +85°C 5V ±10% RECOMMENDED DC OPERATING CONDITIONS (Over the operating range) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power-Supply Voltage V CC 4.5 5.0 5.5 V 1 Battery Voltage V BAT 2.5 3.6 V 1 Input Logic 1 V IH 2.2 VCC +

0.3 V 1

Input Logic 0 V IL -0.3 +0.8 V 1 DC ELECTRICAL CHARACTERISTICS (Over the operating range) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power Supply Current I CC1 7 15 mA 2 Oscillator Current I OSC 300 500 nA Input Leakage I IL -1.0 +1.0 µA 3 I/O Leakage I LO -1.0 +1.0 µA 5 MOT Input Current I MOT -1.0 +500 µA 3 CEI Input Current I CEI -1.0 +200 µA 4 CEI to CEO Impedance ZCE 60 Ω 11 Output at 2.4V I OH -1.0 mA 1, 6 Output at 0.4V I OL 4.0 mA 1 Write-Protect Voltage V TP 4.0 4.25 4.5 V VCCO1 VCC - 0.3V 7 VCCO Voltage VCCO2 VBAT - 0.3V V CAPACITANCE (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C IN 5 pF Output Capacitance C OUT 7 pF

AC ELECTRICAL CHARACTERISTICS (Over the operating range) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Cycle t CYC 225 DC ns Pulse Width, DS/E Low or RD/ WR High PWEL 115 ns Pulse Width, DS/E Low or RD/ WR Low PWEH 80 ns Input Rise and Fall Time t R, tF 30 ns R/ W Hold Time tRWH 10 ns R/ W Setup Time Before DS/E tRWS 10 ns Chip Select Setup Time Before DS, WR , or RD tCS 20 ns Chip Select Hold Time t CH 0 ns Read Data Hold Time t DHR 10 50 ns Write Data Hold Time t DHW 0 ns Muxed Address Valid Time to AS/ALE Fall tASL 30 ns Muxed Address Hold Time t AHL 10 ns Delay Time DS/E to AS/ALE Rise t ASD 20 ns Pulse Width AS/ALE High PW ASH 60 ns Delay Time, AS/ALE to DS/E Rise t ASED 35 ns Output Data Delay Time From DS/E or RD tDDR 10 75 ns 9 Data Setup Time t DSW 60 ns Reset Pulse Width tRWL 5 µs IRQ Release from DS tIRDS 2 µs IRQ Release from RESET tIRR 2 µs AC TEST CONDITIONS Input Pulse Level: 0 to 3.0V Input Rise/Fall Times: 5ns Input and Output Timing Reference Levels: 1.5V

Figure 5. Output Load

DS14285/DS14287 BUS TIMING FOR INTEL INTERFACE WRITE CYCLE

DS14285/DS14287 BUS TIMING FOR INTEL INTERFACE READ CYCLE DS14285/DS14287 IRQ RELEASE DELAY TIMING

POWER-DOWN/POWER-UP TIMING POWER-DOWN/POWER-UP TIMING PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CS at VIH before Power-Down tPD 0 µs VCC slew from 4.5V to 0V ( CS at VIH) tF 300 µs VCC slew from 0V to 4.5V ( CS at VIH) tR 100 µs CS at VIH after Power-Up tREC 20 200 ms Chip-Enable Propagation Delay to External SRAM tCED 10 ns (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Data Retention for DS14287 t DR 10 years 10 NOTE: The RTC keeps time to an accuracy of +1 minute per month during data retention time for the period of tDR. WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode.

NOTES: 1) All voltages are referenced to ground. 2) All outputs are open. 3) The MOT pin has an internal pulldown of 20k Ω. 4) The CEI pin has an internal pullup of 50kΩ. 5) Applies to the AD0–AD7 pins, the IRQ pin, and the SQW pin when each is in the high impedance state. 6) The IRQ pin is open drain. The interrupt and the internal clock continue to run regardless of the level of VCC. However, it is important to insure that the pullup resistor us ed with the interrupt pin is never pulled up to a value which is greater than V CC + 0.3V. As VCC falls below approximately 3.0 volts, a power switching circuit turns the lithium energy source on to maintain the clock and timer data functionality. 7) I CCO = 100mA, VCC > VBAT. 8) I CCO = 100µA, VCC < VBAT. 9) Measured with a load as shown in Figure 5. 10) Expected data retention is based on using an external SRAM with a data retention current of less than 1µA at +25°C. 11) Z CE is an average input-to-output impedance as the input is swept from ground to VCCI and less than 4mA is forced through ZCE. 12) Real-Time Clock Modules such as the DS14287 can be successfully processed through conventional wave-soldering techniques as l ong as temperature exposure to th e lithium energy source contained within does not exceed +85 °C. Post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used.

PACKAGE INFORMATION

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) DS14285 24-PIN DIP PKG 24-PIN DIM MIN MAX A IN. MM 1.245 31.62 1.270 32.25 B IN. MM 0.530 13.46 0.550 13.97 C IN. MM 0.140 3.56 0.160 4.06 D IN. MM 0.600 15.24 0.625 15.88 E IN. MM 0.015 0.380 0.050 1.27 F IN. MM 0.120 3.05 0.145 3.68 G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.625 15.88 0.675 17.15 J IN. MM 0.008 0.20 0.012 0.30 K IN. MM 0.015 0.38 0.022 0.56 DS14285 24-PIN SO PKG 24-PIN DIM MIN MAX A IN. MM 0.602 15.29 0.612 15.54 B IN. MM 0.290 7.37 0.300 7.65 C IN. MM 0.089 2.26 0.095 2.41 E IN. MM 0.004 0.102 0.012 0.30 F IN. MM 0.094 2.38 0.105 2.68 G IN. MM

0.050 BSC

1.27 BSC

H IN. MM 0.398 10.11 0.416 10.57 J IN. MM 0.009 0.229 0.013 0.33 K IN. MM 0.013 0.33 0.019 0.48 L IN. MM 0.016 0.406 0.040 1.02 phi 0° 8 °

PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) DS14285Q 28-PIN PLCC PKG 28-PIN DIM MIN MAX A 0.165 0.180 A1 0.090 0.120 A2 0.020 - B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 D 0.485 0.495 D1 0.450 0.456 D2 0.390 0.430 E 0.485 0.495 E1 0.450 0.456 E2 0.390 0.430 L1 0.060 - N 28 - e1 0.050 BSC CH1 0.042 0.048

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products • Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) DS14287 REAL-TIME CLOCK PLUS RAM PKG 24-PIN DIM MIN MAX A IN. MM 1.320 33.53 1.335 33.91 B IN. MM 0.720 18.29 0.740 18.80 C IN. MM 0.345 8.76 0.370 9.40 D IN. MM 0.100 2.54 0.130 3.30 E IN. MM 0.015 0.38 0.030 0.76 F IN. MM 0.110 2.79 0.140 3.56 G IN. MM 0.090 2.29 0.110 2.79 H IN. MM 0.590 14.99 0.630 16.00 J IN. MM 0.008 0.20 0.012 0.30 K IN. MM 0.015 0.38 0.021 0.53 NOTE: PINS 2, 3, 16, AND 20 ARE MISSING BY DESIGN.