DS1302_05 DALLAS | Alldatasheet
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1 of 16 REV: 110805 Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
FEATURES
Real-Time Clock Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the Week, and Year with Leap-Year Compensation Valid Up to 2100 31 x 8 RAM for Scratchpad Data Storage Serial I/O for Minimum Pin Count 2.0V to 5.5V Full Operation Uses Less than 300nA at 2.0V Single-Byte or Multiple-Byte (Burst Mode) Data Transfer for Read or Write of Clock or RAM Data 8-Pin DIP or Optional 8-Pin SO for Surface Mount Simple 3-Wire Interface TTL-Compatible (VCC = 5V) Optional Industrial Temperature Range: -40°C to +85°C DS1202 Compatible Underwriters Laboratory (UL) Recognized PIN CONFIGURATIONS
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE TOP MARK* DS1302 0°C to +70°C 8 PDIP (300 mils) DS1302 DS1302+ 0°C to +70°C 8 PDIP (300 mils) DS1302 DS1302N -40°C to +85°C 8 PDIP (300 mils) DS1302 DS1302N+ -40°C to +85°C 8 PDIP (300 mils) DS1302 DS1302S 0°C to +70°C 8 SO (208 mils) DS1302S DS1302S+ 0°C to +70°C 8 SO (208 mils) DS1302S DS1302SN -40°C to +85°C 8 SO (208 mils) DS1302S DS1302SN+ -40°C to +85°C 8 SO (208 mils) DS1302S DS1302Z 0°C to +70°C 8 SO (150 mils) DS1302Z DS1302Z+ 0°C to +70°C 8 SO (150 mils) DS1302Z DS1302ZN -40°C to +85°C 8 SO (150 mils) DS1302ZN DS1302ZN+ -40°C to +85°C 8 SO (150 mils) DS1302ZN DS1302S-16 0°C to +70°C 16 SO (300 mils) DS1302S16 DS1302SN-16 -40°C to +85°C 16 SO (300 mils) DS1302SN16 + Denotes a lead-free/RoHS-compliant device. *An N anywhere on the top mark indicates an industrial temperature grade device. A + anywhere on the top mark indicates a lead-free device. DS1302 Trickle-Charge Timekeeping Chip www.maxim-ic.com VCC1 SCLK I/O CE VCC2 GND DIP (300 mils) DS1302 VCC2 GND VCC1 SCLK I/O CE SO (208 mils/150 mils) DS1302 VCC2 GND I/O N.C. N.C. CE SO (300 mils) VCC1 N.C. SCLK N.C. N.C. N.C. N.C. N.C. DS1302 TOP VIEW
DS1302 Trickle-Charge Timekeeping Chip 2 of 16 DETAILED DESCRIPTION The DS1302 trickle-charge timekeeping chip contains a real-time clock/cale ndar and 31 bytes of static RAM. It communicates with a microprocessor via a simple serial inte rface. The real-time clock/ca lendar provides seconds, minutes, hours, day, date, month, and y ear information. The end of the mont h date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. Interfacing the DS1302 with a microprocessor is simplifi ed by using synchronous serial communication. Only three wires are required to communicate with the clock/RAM: CE, I/O (data line), and SCLK (serial clock). Data can be transferred to and from the clock/RAM 1 byte at a time or in a burst of up to 31 bytes. The DS1302 is designed to operate on very low power and retain data and clock information on less than 1µW. The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the DS1202, the DS1302 has the additional features of dual power pins for primary and backup power supplies, programmable trickle charger for V CC1, and seven additional bytes of scratchpad memory. OPERATION Figure 1 shows the main elements of the serial timekeeper: sh ift register, control logic, oscillator, real-time clock, and RAM. TYPICAL OPERATING CIRCUIT DS1302 CPU VCC V CC2 SCLK CE GND X2 X1 VCC I/O V CC1
Figure 1. Block Diagram
DS1302 Trickle-Charge Timekeeping Chip 4 of 16 PIN DESCRIPTION PIN 8 16 NAME FUNCTION 1 1 V CC2 Primary Power-Supply Pin in Dual Supply Configuration. VCC1 is connected to a backup source to maintain the time and date in the absence of primary power. The DS1302 operates from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 + 0.2V, VCC2 powers the DS1302. When VCC2 is less than VCC1, VCC1 powers the DS1302. 2 3 X1 3 5 X2 Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pF. For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. The DS1302 can also be driven by an external 32.768kHz oscillator. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. 4 8 GND Ground 5 9 CE Input. CE signal must be asserted high during a read or a write. This pin has an internal 40kΩ (typ) pulldown resistor to ground. Note: Previous data sheet revisions referred to CE as RST. The functionality of the pin has not changed. 6 12 I/O Input/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wire interface. This pin has an internal 40kΩ (typ) pulldown resistor to ground. 7 14 SCLK Input. SCLK is used to synchronize data movement on the serial interface. This pin has an internal 40kΩ (typ) pulldown resistor to ground. 8 16 V CC1 Low-Power Operation in Single Supply and Battery-Operated Systems and Low- Power Battery Backup. In systems using the trickle charger, the rechargeable energy source is connected to this pin. UL recognized to ensure against reverse charging current when used with a lithium battery. 2, 4, 6, 7, 10, 11, 13, N.C. No Connection
DS1302 Trickle-Charge Timekeeping Chip 7 of 16 The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, seco ndary (user) buffers are used to prevent errors when the internal registers update. When reading the time and dat e registers, the user buffe rs are synchronized to the internal registers the rising edge of CE. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the falling edge of CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second. The DS1302 can be run in either 12-hour or 24-hour mode. Bit 7 of the hours register is defined as the 12- or 24- hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours ). The hours data must be re-initialized whenever the 12/24 bit is changed. CLOCK HALT FLAG Bit 7 of the seconds register is defined as the clock halt (CH) flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When this bit is written to logic 0, the clock will start. The initial power-on state is not defined. WRITE-PROTECT BIT Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 to 6) are forced to 0 and always read 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write-protect bit prevents a write operation to any other register. The init ial power-on state is not defined. Therefore, the WP bit should be cleared before attempting to write to the device. TRICKLE-CHARGE REGISTER This register controls the trickle-c harge characteristics of the DS1302. The simplified schematic of Figure 6 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accide ntal enabling, only a pattern of 1010 en ables the trickle charger. All other patterns will disable the trickle charger . The DS1302 powers up with the trickle charger disabled. The diode select (DS) bits (bits 2 and 3) select whether one diode or two diodes are connected between V CC2 and VCC1. If DS is 01, one diode is selected or if DS is 10, two diodes are sele cted. If DS is 00 or 11, the trickle charger is disabled independently of TCS. The RS bits (bits 0 and 1) select the resistor that is connected between V CC2 and VCC1. The resistor selected by the resistor select (RS) bits is as follows: RS BITS RESISTOR TYPICAL VALUE
00 None None
01 R1 2kΩ
10 R2 4kΩ
11 R3 8kΩ
If RS is 00, the trickle charger is disabled independently of TCS. Diode and resistor selection is determined by the user ac cording to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a system power su pply of 5V is applied to V CC2 and a super cap is connected to V CC1. Also assume that the trickle charger has been enabled with one diode and resistor R1 between V CC2 and V CC1. The maximum current IMAX would therefore be calculated as follows: IMAX = (5.0V – diode drop) / R1 ≈ (5.0V – 0.7V) / 2kΩ ≈ 2.2mA As the super cap charges, the voltage drop between V CC2 and V CC1 decreases and therefore the charge current decreases.
registers can be consecutively read or written (see Table 2) starting with bit 0 of address 0. re-read the registers in case of an update of the main registers during a read. The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space. read or written (see Table 2) starting with bit 0 of address 0. A register data format summary is shown in Table 2. layout consideration, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks. Figure 5. Data Transfer Summary NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST.
Table 2. Register Address/Definition Figure 6. Programmable Trickle Charger
1 OF 2
1 OF 3
DS1302 Trickle-Charge Timekeeping Chip 10 of 16 ABSOLUTE MAXIMUM RATINGS Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating s only, and functional operation of the device at these or any other conditions beyond those i ndicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC1, VCC2 VCC1, VCC2 (Notes 2, 10) 2.0 3.3 5.5 V Logic 1 Input V IH (Note 2) 2.0 VCC + 0.3 V VCC = 2.0V -0.3 +0.3 Logic 0 Input V IL VCC = 5V (Note 2) -0.3 +0.8 V DC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Leakage I LI (Notes 5, 13) 85 500 µA I/O Leakage I LO (Notes 5, 13) 85 500 µA Logic 1 Output (IOH = -0.4mA) V CC = 2.0V 1.6 Logic 1 Output (IOH = -1.0mA) VOH VCC = 5V (Note 2) 2.4 V Logic 0 Output (IOL = 1.5mA) V CC = 2.0V 0.4 Logic 0 Output (IOL = 4.0mA) VOL VCC = 5V (Note 2) 0.4 V VCC1 = 2.0V 0.4 Active Supply Current (Oscillator Enabled) ICC1A VCC1 = 5V CH = 0 (Notes 4, 11) 1.2 mA VCC1 = 2.0V 0.2 0.3 Timekeeping Current (Oscillator Enabled) ICC1T VCC1 = 5V CH = 0 (Notes 3, 11,13) 0.45 1 µA VCC1 = 2.0V 1 100 VCC1 = 5V 1 100 Standby Current (Oscillator Disabled) ICC1S IND CH = 1 (Notes 9, 11, 13) 5 200 nA VCC2 = 2.0V 0.425 Active Supply Current (Oscillator Enabled) ICC2A VCC2 = 5V CH = 0 (Notes 4, 12) 1.28 mA VCC2 = 2.0V 25.3 Timekeeping Current (Oscillator Enabled) ICC2T VCC2 = 5V CH = 0 (Notes 3, 12) 81 µA VCC2 = 2.0V CH = 1 (Notes 9, 12) 25 Standby Current (Oscillator Disabled) ICC2S VCC2 = 5V 80 µA R1 2 R2 4 Trickle-Charge Resistors R3 8 kΩ Trickle-Charge Diode Voltage Drop VTD 0.7 V
DS1302 Trickle-Charge Timekeeping Chip 11 of 16 CAPACITANCE (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS Input Capacitance C I 10 pF I/O Capacitance C I/O 15 pF AC ELECTRICAL CHARACTERISTICS (TA = 0°C to +70°C or TA = -40°C to +85°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC = 2.0V 200 Data to CLK Setup t DC VCC = 5V (Note 6) 50 ns VCC = 2.0V 280 CLK to Data Hold t CDH VCC = 5V (Note 6) 70 ns VCC = 2.0V 800 CLK to Data Delay t CDD VCC = 5V (Notes 6, 7, 8) 200 ns VCC = 2.0V 1000 CLK Low Time t CL VCC = 5V (Note 6) 250 ns VCC = 2.0V 1000 CLK High Time t CH VCC = 5V (Note 6) 250 ns VCC = 2.0V 0.5 CLK Frequency t CLK VCC = 5V (Note 6) DC 2.0 MHz VCC = 2.0V 2000 CLK Rise and Fall t R, tF VCC = 5V 500 ns VCC = 2.0V 4 CE to CLK Setup t CC VCC = 5V (Note 6) 1 µs VCC = 2.0V 240 CLK to CE Hold t CCH VCC = 5V (Note 6) 60 ns VCC = 2.0V 4 CE Inactive Time t CWH VCC = 5V (Note 6) 1 µs VCC = 2.0V 280 CE to I/O High Impedance t CDZ VCC = 5V (Note 6) 70 ns VCC = 2.0V 280 SCLK to I/O High Impedance t CCZ VCC = 5V (Note 6) 70 ns Note 1: Limits at -40°C are guaranteed by design and are not production tested. Note 2: All voltages are referenced to ground. Note 3: ICC1T and ICC2T are specified with I/O open, CE and SCLK set to a logic 0. Note 4: ICC1A and ICC2A are specified with the I/O pin open, CE high, SCLK = 2MHz at VCC = 5V; SCLK = 500kHz, VCC = 2.0V. Note 5: CE, SCLK, and I/O all have 40kΩ pulldown resistors to ground. Note 6: Measured at VIH = 2.0V or VIL = 0.8V and 10ns maximum rise and fall time. Note 7: Measured at VOH = 2.4V or VOL = 0.4V. Note 8: Load capacitance = 50pF. Note 9: ICC1S and ICC2S are specified with CE, I/O, and SCLK open. Note 10: VCC = VCC2, when VCC2 > VCC1 + 0.2V; VCC = VCC1, when VCC1 > VCC2. Note 11: VCC2 = 0V. Note 12: VCC1 = 0V. Note 13: Typical values are at +25°C.
Figure 7. Timing Diagram: Read Data Transfer Figure 8. Timing Diagram: Write Data Transfer
8 DIP 110 40
8 SO (150 mils) 170 40
8 SO (208 mils) 113 31
16 SO (300 mils) 105 22
DS1302 Trickle-Charge Timekeeping Chip 13 of 16
PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect t he most current specifications . For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
DS1302 Trickle-Charge Timekeeping Chip 14 of 16 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
DS1302 Trickle-Charge Timekeeping Chip 15 of 16 PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products • Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation. PACKAGE INFORMATION (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.)