DS1225Y DALLAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 8
Technical content
FEATURES
- 10 years minimum data retention in the absence of external power
- Data is automatically protected during power loss
- Directly replaces 8K x 8 volatile static RAM or EE- PROM
- Unlimited write cycles
- Low-power CMOS
- JEDEC standard 28–pin DIP package
- Read and write access times as fast as 150 ns
- Full ±10% operating range
- Optional industrial temperature range of –40°C to +85°C, designated IND PIN ASSIGNMENT 14 15 28NC A12 DQ0 DQ1 DQ2 GND VCC NC A11 A10 DQ7 DQ6 DQ5 DQ4 DQ3 WE OE CE 28–PIN ENCAPSULATED PACKAGE
720 MIL EXTENDED
A0–A12 – Address Inputs DQ0–DQ7 – Data In/Data Out CE – Chip Enable WE – Write Enable OE – Output Enable VCC – Power (+5V) GND – Ground NC – No Connect
DESCRIPTION
The DS1225Y 64K Nonvolatile SRAM is a 65,536–bit, fully static, nonvolatile RAM organized as 8192 words by 8 bits. Each NV SRAM has a self–contained lithium energy source and control circuitry which constantly monitors VCC for an out–of–tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is uncon- ditionally enabled to prevent data corruption. The NV SRAM can be used in place of existing 8K x 8 SRAMs directly conforming to the popular bytewide 28–pin DIP standard. The DS1225Y also matches the pinout of the
2764 EPROM or the 2864 EEPROM, allowing direct
substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for micro- processor interfacing.
The DS1225Y executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 13 address inputs (A0–A12) de- fines which of the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output driv- ers within tACC (Access Time) after the last address in- put signal is stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later occurring signal and the limiting parameter is either t CO for CE or tOE for OE rather than address ac- cess. WRITE MODE The DS1225Y executes a write cycle whenever the WE and CE signals are active (low) after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time (tWR ) before another cycle can be initi- ated. The OE control signal should be kept inactive (high) during write cycles to avoid bus contention. How- ever, if the output drivers are enabled (CE and OE ac- tive) then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1225Y provides full functional capability for VCC greater than 4.5 volts and write protects at 4.25 nominal. Data is maintained in the absence of V CC without any additional support circuitry. The DS1225Y constantly monitors VCC . Should the supply voltage decay, the NV SRAM automatically write protects itself, all inputs be- come “don’t care,” and all outputs become high imped- ance. As VCC falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power–up, when VCC rises above approximately 3.0 volts, the power switching circuit connects external VCC to RAM and dis- connects the lithium energy source. Normal RAM oper- ation can resume after VCC exceeds 4.5 volts.
ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground –0.3V to +7.0V Operating Temperature 0 °C to 70°C; –40°C to +85°C for IND parts Storage Temperature –40 °C to +70°C; –40°C to +85°C for IND parts Soldering Temperature 260 °C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (tA: See Note 10) PARAMETER SYM MIN TYP MAX UNITS NOTES Power Supply Voltage VCC 4.5 5.0 5.5 V Input Logic 1 VIH 2.2 VCC V Input Logic 0 VIL 0.0 +0.8 V DC ELECTRICAL CHARACTERISTICS (tA: See Note 10; VCC = 5V ± 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current IIL –1.0 +1.0 µA I/O Leakage Current CE > VIH < VCC IIO –1.0 +1.0 µA Output Current @ 2.4V IOH –1.0 mA Output Current @ 0.4V IOL 2.0 mA Standby Current CE = 2.2V ICCS1 5 10 mA Standby Current CE = VCC –0.5V ICCS2 3 5 mA Operating Current tCYC =200 ns (Commercial) ICCO1 75 mA Operating Current tCYC =200 ns (Industrial) ICCO1 85 mA Write Protection Voltage VTP 4.25 V 10
AC ELECTRICAL CHARACTERISTICS (tA: See Note 10; VCC =5.0V ± 10%) PARAMETER SYMBOL DS1225Y-150 DS1225Y-170 DS1225Y-200 UNITS NOTESPARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES Read Cycle Time tRC 150 170 200 ns Access Time tACC 150 170 200 ns OE to Output Valid tOE 70 80 100 ns CE to Output Valid tCO 150 170 200 ns OE or CE to Output Active tCOE 5 5 5 ns 5 Output High Z from De- selection tOD 35 35 35 ns 5 Output Hold from Ad- dress Change tOH 5 5 5 ns Write Cycle Time tWC 150 170 200 ns Write Pulse Width tWP 100 120 150 ns 3 Address Setup Time tAW 0 0 0 ns Write Recovery Time tWR1 tWR2 ns ns Output High Z from WE tODW 35 35 35 ns 5 Output Active from WE tOEW 5 5 5 ns 5 Data Setup Time tDS 60 70 80 ns 4 Data Hold Time tDH1 tDH2 ns ns CAPACITANCE (tA = 25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C IN 10 pF Input/Output Capacitance C I/O 10 pF
SEE NOTE 2, 3, 4, 6, 7, 8 AND 12 ADDRESSES WRITE CYCLE 2 CE WE D OUT D IN tWC VIH VIL VIH VIL VIH VIL tAW tWP VIL VIL VIL VIL VIH VIH VIL VIH tWR2 tCOE tODW DATA IN STABLE V IH VIL VIH VIL tDS tDH2 SEE NOTE 2, 3, 4, 6, 7, 8 AND 13
POWER–DOWN/POWER–UP CONDITION 3.2V DATA RETENTION TIME CE VCC tF tPD tR tREC tDR LEAKAGE CURRENT IL SUPPLIED FROM LITHIUM CELL VTP SEE NOTE 11 POWER–DOWN/POWER–UP TIMING PARAMETER SYM MIN MAX UNITS NOTES CE at VIH before Power–Down tPD 0 µs 11 VCC Slew from VTP to 0V tF 100 µs VCC Slew from 0V to VTP tR 0 µs CE at VIH after Power–Up tREC 2 ms (tA = 25°C) PARAMETER SYM MIN MAX UNITS NOTES Expected Data Retention Time tDR 10 years 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. WE is high for a read cycle. 2. OE = VIH or VIL. If OE = VIH during a write cycle, the output buffers remain in a high impedance state. 3. tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going low to the earlier of CE or WE going high. 4. tDS is measured from the earlier of CE or WE going high. 5. These parameters are sampled with a 5 pF load and are not 100% tested. 6. If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle 1, the output buffers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period.
- If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9. Each DS1225Y is marked with a 4–digit date code AABB. AA designates the year of manufacture. BB designates the week of manufacture. The expected tDR is defined as starting at the date of manufacture. 10. All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial prod- ucts, this range is 0°Ct o 7 0°C. For industrial products (IND), this range is –40°C to +85°C. 11. In a power down condition the voltage on any pin may not exceed the voltage on VCC . 12. tWR1 , tDH1 are measured from WE going high. 13. tWR2 , tDH2 are measured from CE going high. 14. DS1225Y modules are recognized by Underwriters Laboratory (U.L. ) under file E99151 (R). DC TEST CONDITIONS Outputs open. All voltages are referenced to ground. AC TEST CONDITIONS Output Load: 100pF + 1TTL Gate Input Pulse Levels: 0–3.0V Timing Measurement Reference Levels Input:1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns
ORDERING INFORMATION
DS1225 TTP– SSS – III Operating Temperature Range Blank: 0°Ct o 7 0°C IND: –40°C to +85°C Access 150: 170: 200: Speed 150 ns 170 ns 200 ns Package Type Blank: 28–pin 600 mil DIP VCC Tolerance Y: 10%
DS1225Y NONVOLATILE SRAM, 28–PIN 720 MIL EXTENDED MODULE A DIM MIN MAX A IN. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM 1.520 38.61 1.540 39.12 0.695 17.65 0.720 18.29 0.395 10.03 0.415 10.54 0.100 2.54 0.130 3.30 0.017 0.43 0.030 0.76 0.120 3.05 0.160 4.06 0.090 2.29 0.110 2.79 0.590 14.99 0.630 16.00 0.008 0.20 0.012 0.30 0.015 0.38 0.021 0.53 C F GKD H B E J 28–PINPKG