DS1216B

DS1216 DALLAS | Alldatasheet

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Technical content

FEATURES

/g167 Keeps track of hundredths of seconds, seconds, minutes, hours, days, date of the month, months, and years /g167 Converts standard 2k x 8 up to 512k x 8 CMOS static RAMs into nonvolatile memory /g167 Embedded lithium energy cell maintains watch information and retains RAM data /g167 Watch function is transparent to RAM operation /g167 Month and year determine the number of days in each month; leap-year compensation valid up to 2100 /g167 Lithium energy source is electrically disconnected to retain freshness until power is applied for the first time /g167 Proven gas-tight socket contacts /g167 Full /g17710% operating range /g167 Operating temperature range: 0/g176C to +70/g176C /g167 Accuracy is better than /g1771 minute/month @ +25/g176C

ORDERING INFORMATION

DS1216B, DS1216C, DS1216D, DS1216E, DS1216F, DS1216H (See Figure 2 for letter suffix marking identification.) PIN DESCRIPTION RST - RESET DQ0 - Data Input/Output 0 [RAM] A2 - Address Bit 2 (Read/Write [ROM]) A0 - Address Bit 0 (Data Input [ROM]) GND - Ground CE - Conditioned Chip Enable OE - Output Enable WE - Write Enable Vcc - Switched V CC for 28-/32-Pin RAM VCCB - Switched V CC for 24-Pin RAM VCCD - Switched V CC for 28-Ppin RAM PART RAM/ROM RAM DENSITY PCB MODIFICATION REQUIRED FOR DENSITY UPGRADE? DS1216B RAM 16k/64k No/Yes DS1216C RAM 64k/256k No DS1216D RAM 256k/1M No/Yes DS1216E ROM 64k/256k No DS1216F ROM 64k/256k/1M No DS1216H RAM 1M/4M No DS1216 SmartWatch RAM DS1216B/C/D/H SmartWatch ROM DS1216E/F www.maxim-ic.com DS1216B/C/D/E 28-Pin Intelligent Socket 2 27 WE 3 26 VCCB 4 25 5 24 [A2] 8 21 6 23 9 20 CE 7 22 OE [A0] 10 19 DQ0 11 18 12 17 13 16 GND 14 15 RST 1 28 V CC

DESCRIPTION

The DS1216 SmartWatch RAM and SmartWatch ROM Sockets are 600mil-wide DIP sockets with a built-in CMOS watch function, an NV RAM controller circuit, and an embedded lithium energy source. The sockets provide an NV RAM solution for memory sized from 2k x 8 to 512k x 8 with package sizes from 26 pins to 32 pins. When a socket is mated w ith a CMOS SRAM, it provides a complete solution to problems associated with memory volatility and uses a common energy source to maintain time and date. The SmartWatch ROM sockets use the embedded lithium source to maintain the time and date only. A key feature of the SmartWatch is that the watch function remains transparent to the RAM. The SmartWatch monitors V CC for an out-of-tolerance condition. When such a condition occurs, an internal lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent loss of watch and RAM data. Using the SmartWatch saves PC board space since the combination of SmartWatch and the mated RAM take up no more area than the memory alone. The SmartWatch uses the VCC, data I/O 0, CE , OE , and WE for RAM and watch control. All other pins are passed straight through to the socket receptacle. The SmartWatch provides timekeeping information including hundredths of seconds, seconds, minutes, hours, days, date, months, and years. The date at the end of the mont h is automatically adjusted for months with fewer than 31 days, including correction for leap years. The SmartWatch operates in either 24-hour or 12-hour format with an AM/PM indicator. OPERATION Communication with the SmartWatch RAM is established by pattern recognition on a serial bit stream of 64 bits that must be matched by executing 64 consec utive write cycles containing the proper data on DQ0. On the SmartWatch ROM, communication with the clock is established using A2 and A0, and either OE or CE. All accesses that occur prior to r ecognition of the 64-bit pattern are directed to memory. VCC WE OE CE [A2] 10 [A0] 12 17GND DQ0 RST DS1216D/E/F/H 32-Pin Intelligent Socket

After the pattern match, the next 64 reads and/or writes are directed to the clock, and the RAM is disabled. Once the pattern is established, the next 64 read/write cycles will be directed to the RTC registers. When power is cycled, 64 reads should be executed prior to any writes to ensure that the RTC registers are not written. A pattern match is ignored if the RST bit is zero and the RST pin goes low during the match sequence. A pattern match is also terminated if a read occurs during the 64-bit match sequence. PATTERN MATCH—RAM Data transfer to and from the timekeeping registers is accomplished with a serial bit stream under control of chip enable ( CE ), output enable ( OE ), and write enable ( WE ). Initially, a read cycle to any memory location using the CE and OE control of the SmartWatch starts the pattern recognition sequence by moving a pointer to the first bit of the 64-bit comp arison register. Next, 64 consecutive write cycles are executed using the CE and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the SmartWatch. Therefore, any address to the memory in the socket is acceptable. However, the write cycles generated to gain access to the SmartWatch are also writing data to a location in the mated RAM. The preferred way to manage this requirement is to set aside just one address location in RAM as a SmartWatch scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison regi ster pointer is reset. Pattern recognition continues for 64 write cycles as described above until all the bits in the comparison register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is enabled and data transfer to or from the timekeeping registers can pr oceed. The next 64 cycles will cause the SmartWatch to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern recognition sequence or data transfer sequence to the SmartWatch. PATTERN MATCH—ROM Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the proper data on address bit A0. The 64 write cycles are used only to gain access to the SmartWatch. Prior to executing the first of 64 write cycles, a read cy cle should be executed by holding A2 high. The read cycle will reset the comparison register pointer with in the SmartWatch, ensuring the pattern recognition starts with the first bit of the sequence. When the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, th e pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison regi ster pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above, until all the bits in the comparison register have been matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is enabled and data transfer to or from the timekeepin g registers can proceed. The next 64 cycles will cause the SmartWatch to either receive data on data in (A0) or transmit data on data out (DQ0), depending on the level of /WRITE READ (A2).

SMARTWATCH COMPARISON REGISTER DEFINITION Figure 1 Note: The pattern recognition in Hex is C5, 3A, 5C , C5, 3A, A3, 5C. The odds of this pattern accidentally duplicating and causing inadvertent en try to the SmartWatch are less than 1 in 10 19. This pattern is sent to the SmartWatch LSB to MSB. After power-up, the controller coul d be in the 64-bit clock register read/write sequence (from an incomplete access prior to power-down). Therefore, it is recommended that a 64-bit read be performed upon power-up to prevent accidental writes to the clock, and to prevent reading clock data when access to the RAM would otherwise be expected. NONVOLATILE CONTROLLER OPERATION The DS1216 SmartWatch performs circuit functions required to make a CMOS RAM nonvolatile. First, a switch is provided to direct power from the battery or VCC supply, depending on which voltage is greater. This switch has a voltage drop of less than 0.2V. Th e second function that the SmartWatch provides is power-fail detection, which occurs at V TP. The DS1216 constantly monitors the V CC supply. When V CC goes out of tolerance, a comparator outputs a power-fail signal to the chip-enable logic. The third function accomplishes write protection by holding the chip-e nable signal to the memory within 0.2V of V CC or battery. During nominal power-supply conditions, the memory chip-enable signal will track the chip- enable signal sent to the socket with a maximum propagation delay of 7ns for the 5V and 12ns for the 3.3V version. FRESHNESS SEAL Each DS1216 is shipped from Dallas Semiconductor w ith its lithium energy source disconnected, ensuring full energy capacity. When V CC is first applied at a level greater than the lithium energy source is enabled for battery-backup operation. 1 1 0001 0 1 0 0 1110 1 0 1 0 1000 1 1 0 1 0111 0 0 1 1 0001 0 1 0 0 1110 1 0 1 0 1000 1 1 0 1 0111 0 0 BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 HEX VALUE7 0

SMARTWATCH REGISTER INFORMATION The SmartWatch information is contained in eight registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the SmartWatch registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce errone ous results. These read/write registers are defined in Figure 3. Data contained in the SmartWatch registers is in binary-coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. AM–PM/12/24 MODE Bit 7 of the hours register is defined as the 12-hou r or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is th e AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). OSCILLATOR AND RESET BITS Bits 4 and 5 of the day register are used to control the RESET and oscillator functions. Bit 4 controls the RESET (pin 1). When the RESET bit is set to logic 1, the RESET input pin is ignored. When the RESET bit is set to logic 0, a low input on the RESET pin will cause the SmartWatch to abort data transfer without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These bits are shipped from the factory set to logic 1. ZERO BITS Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable. ADDITIONAL INFORMATION Refer to Application Note 52 for information about using regarding optional modifications and the phantom clock contained within the SmartWatch.

RESET AND MEMORY DENSITY OPTIONS Figure 2 The letter suffix of the SmartWatch is located on the PCB as shown above. The RESET pin on the controller has an intern al pullup resistor. To disable the RESET function, the trace between pin 1 on the socket and pin 13 on the controller can be cut. In this case, the socket will ignore the RESET input, preventing address transitions from rese tting the pattern match, even if the RST bit is enabled. On the DS1216B and DS1216D, the two V CC pins are connected together on the PCB. The switched V CC from the controller is connected to the two V CC pins that connect to the in serted RAM. No modifications are required if the lower density RAM is used. To use the higher density RAM, the trace by the lower density RAM V CC pin, identified by a hash mark labeled “U,” must be cut. The two square-metal pads, labeled “G,” must be shorted together. This disconnects switched V CC from the pin going to the inserted RAM, and connects it to the corresponding address input pin for the higher density RAM.

SMARTWATCH REGISTER DEFINITION Figure 3 0 0 10 DATE DATE 0 0 0 10 MONTH MONTH 0 10 MIN MINUTES 0.1 SEC 0.01 SEC 0 10 SEC SECONDS 12/24 0 10 A/P HR HOUR 0 0 OSC RST 0 DAY

10 YEAR YEAR

RANGE (BCD)REGISTER 7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0

ABSOLUTE MAXIMUM RATINGS* Voltage Range on any Pin Relative to Ground -0.3V to +7.0V for 5V Operating Temperature Range 0°C to +70°C Storage Temperature Range -40°C to +70°C Soldering Temperature Range See J-STD-020A Specification (Note 6) * This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0/g176C to +70/g176C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES VCC Pin 5V Supply V CC 4.5 5.0 5.5 V 1 Logic 1 V IH 2.2 V CC + 0.3 V 8 Logic 0 V IL -0.3 +0.8 V 8 DC ELECTRICAL CHARACTERISTICS (0/g176C to +70/g176C; VCC = 5.0 /g177 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES VCC Supply I CCI 5 mA 1, 2,3 VCC Supply Voltage (ICCO = 80mA) VCCO1(U) VCC - 0.2 V 1, 6 Input Leakage I IL -1.0 +1.0 /g109A 2,8,13 Output Logic 1 Voltage (IOUT = -1.0mA) VOH 2.4 V Output Logic 1 Voltage (IOUT = -1.0mA) VOL 0.4 V Write Protection Voltage V TP 4.25 4.5 V BACKUP POWER CHARACTERISTICS (0/g176C to +70/g176C; VCC < VTP) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CE Output VOH(L) VBAT - 0.2 V 1 VCC Supply Voltage (ICCO = 10µA) VCCO2(U) VBAT - 0.2 V 1, 6,14 RAM VCC (Battery) Voltage V BAT 2 3 3.6 V 1,15 Recovery at Power-Up t REC 2m s VCC Slew Rate fall t F 0 /g109s CE Pulse Width tCE 1.5 /g109s 5

CAPACITANCE (TA = +25/g176C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C IN 5p F Output Capacitance C OUT 7p F (TA = +25/g176C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Expected Data Retention t DR 10 Years 14 AC ELECTRICAL CHARACTERISTICS (0/g176C to 70/g176C; VCC = 4.5 to 5.5V) PARAMETER SYMBOL MIN TYPE MAX UNITS NOTES Read Cycle Time t RC 75 ns CE Access Time tCO 65 ns OE Access Time tOE 65 ns CE to Output Low-Z tCOE 6n s OE to Output Low-Z tOEE 6n s CE to Output High-Z tOD 30 ns OE to Output High-Z tODO 30 ns Address Setup Time (ROM) t AS 20 11 Address Hold Time (ROM) t AH 10 12 Read Recovery t RR 15 ns Write Cycle Time t WC 75 ns Write Pulse Width t WP 75 ns Write Recovery t WR 15 ns 9 Data Setup Time t DS 35 ns 10 Data Hold Time t DH 0n s 1 0 CE Pulse Width tCW 65 ns RESET Pulse Width tRST 75 ns CE Propagation Delay tPD 6n s 7 CE High to Power-Fail tPF 0n s

TIMING DIAGRAM: READ CYCLE TO SMARTWATCH TIMING DIAGRAM: WRITE CYCLE TO SMARTWATCH TIMING DIAGRAM: RESET FOR SMARTWATCH

TIMING DIAGRAM: POWER-DOWN TIMING DIAGRAM: POWER-UP Warning: Under no circumstances should negative undershoots of any amplitude be allowed when the device is in battery-backup mode. Water washing for flux removal will discharge internal lithium source because exposed voltage pins are present.

NOTES: 1) Pin locations are designated “U” when a parameter definition refers to the socket receptacle and “L” when a parameter definition refers to the socket pin. 2) No memory inserted in the socket. 3) Pin 26L can be connected to VCC or left disconnected at the PC board. 4) SmartWatch sockets can be successfully processed through some conventional wave-soldering techniques as long as temperature exposure to the lithium energy source contained within does not exceed +85 /g176C. However, post-solder cleaning with water washing techniques is not permissible. Discharge to the lithium energy source can result, even if deionized water is utilized. It is equally imperative that ultrasonic vibration is not used in order to avert damage to the quartz crystal resonator employed by the oscillator circuit. tCE max must be met to ensure data integrity on power loss. 6) VCCO1 is the maximum voltage drop from Vcc(L) to Vcc(U) while power is being supplied by Vcc(L). VCCO2 is the maximum voltage drop from VBAT to VCC(U) while the part is in battery backup. 7) Input pulse rise and fall times equal 10ns. 8) Applies to pins RST L, A2 L, A0 L, CE L, OE L, and WE L. 9) tWR is a functions of the latter occurring edge of WE or CE . 10) tDH and tDS are a function of the first occurring edge of WE or CE . 11) Tas is a function of the first occurring edge of OE or CE. 12) Tah is a function of the latter occurring edge of OE or CE 13) RST (Pin 1) has an internal pullup resistor. 14) Expected data retention is based on using an external SRAM with a data retention current of less than 0.5µA at +25°C. Expected data retention time (time while on battery) for a given RAM battery current can be calculated using the following formula: 0.045 / (current in amps) = data retention time in hours 15) The DS1216 products are shipped with the battery-backup power off. First power-up switches backup battery on to clock and RAM VCC pin upon power down.

MM 35.31 36.07 40.13 41.14 MM 17.53 18.29 17.53 18.29 MM 10.67 11.94 10.16 11.94 MM 0.89 1.65 0.89 1.65 MM 1.39 1.90 1.39 1.90 MM 3.04 4.06 3.04 4.06 MM 2.29 2.79 2.29 2.79 MM 14.99 16.00 14.99 16.00 MM 0.20 0.30 0.20 0.30 MM 0.38 0.53 0.38 0.53 MM 9.65 10.67 9.65 10.67 28-PIN 32-PIN