DS1215

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Technical content

Copyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. DS1215 Phantom Time Chip DS1215 032697 1/15

FEATURES

• Keeps track of hundredths of seconds, seconds, min- utes, hours, days, date of the month, months, and years
• Adjusts for months with fewer than 31 days
• Leap year automatically corrected up to 2100
• No address space required
• Provides nonvolatile controller functions for battery backup of RAM
• Supports redundant batteries for high–reliability

applications

• Uses a 32.768 KHz watch crystal
• Full ±10% operating range
• Operating temperature range 0°C to 70°C
• Space-saving, 16–pin DIP package and SOIC
• Optional industrial temperature range –40°C to +85°C (IND)

DESCRIPTION

The DS1215 Phantom Time Chip is a combination of a CMOS timekeeper and a nonvolatile memory controller. In the absence of power, an external battery maintains the timekeeping operation and provides power for a CMOS static RAM. The watch keeps track of hun- dredths of seconds, seconds, minutes, hours, day, date, month, and year information. The last day of the month is automatically adjusted for months with less than 31 days, including correction for leap year every four years. The watch operates in one of two formats: a 12–hour mode with an AM/PM indicator or a 24–hour mode. The nonvolatile controller supplies all the necessary support circuitry to convert a CMOS RAM to a nonvolatile memory. The DS1215 can be interfaced with either RAM or ROM without leaving gaps in memory. PIN ASSIGNMENT WE BAT1 GND D Q GND VCCI VCCO BAT2 RST OE CEI CEO ROM/RAM 16–PIN DIP (300 MIL) WE BAT1 GND D Q GND VCCI VCCO BAT2 RST OE CEI CEO ROM/RAM 16–PIN SOIC (300 MIL) PIN DESCRIPTION X1, X2 – 32.768 KHz Crystal Connections WE – Write Enable BAT1 – Battery 1 Input GND – Ground D – Data In Q – Data Out ROM/RAM – ROM/RAM Select CEO – Chip Enable Out CEI – Chip Enable Input OE – Output Enable RST – Reset BAT2 – Battery 2 Input VCCO – Switched Supply Output VCCI – +5 VDC Input NOTE: Both pins 5 and 8 must be grounded.

ORDERING INFORMATION

DS1215 16–pin DIP DS1215S 16–pin SOIC DS1215N 16–pin DIP (IND) DS1215SN 16–pin SOIC (IND)

The block diagram of Figure 1 illustrates the main ele- ments of the Time Chip. Communication with the Time Chip is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive write cycles containing the proper data on data in (D). All accesses which occur prior to recog- nition of the 64-bit pattern are directed to memory via the chip enable output pin (CEO). After recognition is established, the next 64 read or write cycles either extract or update data in the Time Chip and CEO remains high during this time, disabling the con- nected memory. Data transfer to and from the timekeeping function is ac- complished with a serial bit stream under control of chip enable input (CEI ), output enable (OE), and write en- able (WE). Initially, a read cycle using the CEI and OE control of the Time Chip starts the pattern recognition sequence by moving a pointer to the first bit of the 64 bit comparison register. Next, 64 consecutive write cycles are executed using the CEI and WE control of the Time Chip. These 64 write cycles are used only to gain ac- cess to the Time Chip. TIMING BLOCK DIAGRAM Figure 1 CLOCK/CALENDAR LOGIC UPDATE TIMEKEEPING REGISTER COMPARISON REGISTER INTERNAL V CC VCCOVCCI D Q DATA POWER-FAIL WRITE READ CEO ROM/RAM BAT 1 BAT 2 32.768 kHz CEI OE WE RST CONTROL LOGIC ACCESS ENABLE SEQUENCE DETECTOR I/O BUFFERS POWER–FAIL DETECT LOGIC

When the first write cycle is executed, it is compared to bit 1 of the 64–bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle oc- curs at any time during pattern recognition, the present sequence is aborted and the comparison register point- er is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched. (This bit pat- tern is shown in Figure 2.) With a correct match for 64 bits, the Time Chip is enabled and data transfer to or from the timekeeping registers may proceed. The next 64 cycles will cause the Time Chip to either receive data on D, or transmit data on Q, depending on the level of OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CEI cycles without interrupting the pattern recognition sequence or data transfer sequence to the Time Chip. A 32,768 Hz quartz crystal can be directly connected to the DS1215 via pins 1 and 2 (X1, X2). The crystal se- lected for use should have a specified load capacitance (CL) of 6 pF. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal Considerations with Dal- las Real Time Clocks”. TIME CHIP COMPARISON REGISTER DEFINITION Figure 2 76543210 11000101 00111010 10100011 01011100 11000101 00111010 10100011 01011100 BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6 BYTE 7 HEX VALUE NOTE: The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated and causing inadvertent entry to the Time Chip are less than 1 in 1019.

NONVOLATILE CONTROLLER OPERATION The operation of the nonvolatile controller circuits within the Time Chip is determined by the level of the ROM/RAM select pin. When ROM/RAM is connected to ground, the controller is set in the RAM mode and per- forms the circuit functions required to make static CMOS RAM and the timekeeping function nonvolatile. A switch is provided to direct power from the battery in- puts or VCCI to VCCO with a maximum voltage drop of 0.3 volts. The VCCO output pin is used to supply uninter- rupted power to CMOS SRAM. The DS1215 also per- forms redundant battery control for high reliability. On power–fail, the battery with the highest voltage is auto- matically switched to V CCO . If only one battery is used in the system, the unused battery input should be con- nected to ground. The DS1215 safeguards the Time Chip and RAM data by power–fail detection and write protection. Power–fail detection occurs when VCCI falls below VTP, which is equal to 1.26 x VBAT. The DS1215 constantly monitors the VCCI supply pin. When VCCI is less than VTP, a com- parator outputs a power–fail signal to the control logic. The power–fail signal forces the chip enable output (CEO ) to VCCI or VBAT –0.2 volts for external RAM write protection. During nominal supply conditions, CEO will track CEI with a maximum propagation delay of 20 ns. Internally, the DS1215 aborts any data transfer in prog- ress without changing any of the Time Chip registers and prevents future access until VCCI exceeds VTP. A typical RAM/Time Chip interface is illustrated in Figure 3. When the ROM/RAM pin is connected to VCCO , the con- troller is set in the ROM mode. Since ROM is a read– only device that retains data in the absence of power, battery backup and write protection is not required. As a result, the chip enable logic will force CEO low when power fails. However, the Time Chip does retain the same internal nonvolatility and write protection as de- scribed in the RAM mode. In addition, the chip enable output is set at a low level on power–fail as VCCI falls be- low the level of VBAT. A typical ROM/Time Chip interface is illustrated in Figure 4. TIME CHIP REGISTER INFORMATION Time Chip information is contained in 8 registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64–bit pattern recognition sequence has been completed. When updating the Time Chip regis- ters, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could pro- duce erroneous results. These read/write registers are defined in Figure 5. Data contained in the Time Chip registers is in binary coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping though all 8 registers, starting with bit 0 of register 0 and ending with bit 7 of register 7. AM–PM/12/24 MODE Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour mode is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour mode, bit 5 is the second 10–hour bit (20 –23 hours). OSCILLATOR AND RESET BITS Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the reset pin (Pin 13). When the reset bit is set to logic 1, the reset in- put pin is ignored. When the reset bit is set to logic 0, a low input on the reset pin will cause the Time Chip to abort data transfer without changing data in the time- keeping registers. Reset operates independently of all other inputs. Bit 5 controls the oscillator. When set to logic 0, the oscillator turns on and the watch becomes operational. ZERO BITS Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that will always read logic 0. When writing these locations, either a logic 1 or 0 is acceptable.

RAM/TIME CHIP INTERFACE Figure 3 CMOS STATIC RAM ADD DATA I/O WE OE CE DS1215 CEO OE WE CEI RST BAT 1 BAT 2 VCCO D Q VCCI ROM/ RAM BAT 1 BAT 2

32.768 KHz

+5 VDC A0 – AN D0 – D7 CE RST OR TIE TO GND FOR ONE–BATTERY OPERATION VCC ROM/TIME CHIP INTERFACE Figure 4 ROM ADD DATA I/O OE DS1215 D OE WE CEI RST BAT 1 BAT 2 CEO Q VCCI VCCO ROM/ RAM BAT 1 BAT 212 +5 VDC A0 – AN D0 – D7 CE RST OR TIE TO GND FOR ONE–BATTERY OPERATION CE VCC OE

TIME CHIP REGISTER DEFINITION Figure 5 7654 321 0

0.1 SEC 00–99

00–59 00–59 01–12 01–07 01–31 01–12 00–99 RANGE (BCD) REGISTER 12/24 0 10 HR 00 0 0 0 0 10 MONTH

10 YEAR YEAR

0.01 SEC

00–23

10 SEC SECONDS

10 MIN MINUTES

10 DATE DATE

ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground –0.3V to +7.0V Operating Temperature 0 °C to 70°C Storage Temperature –55 °C to +125°C Soldering Temperature 260 °C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage VCC 4.5 5.0 5.5 V 1 Logic 1 VIH 2.2 VCC +0.3 1 Logic 0 VIL –0.3 +0.8 V 1 VBAT1 or VBAT2 Battery Voltage VBAT 2.5 3.7 V 7 DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 4.5 to 5.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Current ICCI 5 mA 6 Supply Current VCCO = VCCI–0.3 ICCO1 80 mA 8 Input Leakage IIL –1.0 +1.0 µA 11 Output Leakage ILO –1.0 +1.0 µA Output @ 2.4V IOH –1.0 mA 2 Output @ 0.4V IOL 4.0 mA 2 DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC < 4.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES CEO Output VOH1 VCCI or VBAT –0.2 V 9 VBAT1 or VBAT2 Battery Current IBAT 1 µA 6 Battery Backup Current @ V CCO = VBAT –0.2V ICCO2 10 µA 10

AC ELECTRICAL CHARACTERISTICS ROM/RAM = GND (0°C to 70°C; VCC = 4.5 to 5.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Read Cycle Time tRC 120 ns CEI Access Time tCO 100 ns OE Access Time tOE 100 ns CEI to Output Low Z tCOE 10 ns OE to Output Low Z tOEE 10 ns CEI to Output High Z tOD 40 ns OE to Output High Z tODO 40 ns Read Recovery tRR 20 ns Write Cycle tWC 120 ns Write Pulse Width tWP 100 ns Write Recovery tWR 20 ns 4 Data Setup tDS 40 ns 5 Data Hold Time tDH 10 ns 5 CEI Pulse Width tCW 100 ns RST Pulse Width tRST 200 ns CEI Propagation Delay tPD 5 10 20 ns 2, 3 CEI High to Power–Fail tPF 0 ns AC ELECTRICAL CHARACTERISTICS ROM/RAM = GND (0°C to 70°C; VCC > 4.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Recovery at Power–Up tREC 2 ms VCC Slew Rate 4.5 – 3.0V tF 0 ms CAPACITANCE (tA = 25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C IN 5 10 pF Output Capacitance C OUT 5 10 pF

AC ELECTRICAL CHARACTERISTICS ROM/RAM = VCCO (0°C to 70°C; VCC = 5V ± 10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Read Cycle Time tRC 120 ns CEI Access Time tCO 100 ns OE Access Time tOE 100 ns CEI to Output in Low Z tCOE 10 ns OE to Output in Low Z tOEE 10 ns CEI to Output in High Z tOD 40 ns OE to Output in High Z tODO 40 ns Address Setup Time tAS 20 ns Address Hold Time tAH 10 ns Read Recovery tRR 20 ns Write Cycle Time tWC 120 ns CEI Pulse Width tCW 100 ns OE Pulse Width tOW 100 ns Write Recovery tWR 20 ns 4 Data Setup Time tDS 40 ns 5 Data Hold Time tDH 10 ns 5 RST Pulse Width tRST 200 ns CEI Propagation Delay tPD 5 10 20 ns 2, 3 CEI High to Power Fail tPF 0 ns AC ELECTRICAL CHARACTERISTICS ROM/RAM = VCCO (0°C to 70°C; VCC < 4.5V) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Recovery at Power–Up tREC 2 ms VCC Slew Rate 4.5 – 3.0V tF 0 ms

TIMING DIAGRAM: READ CYCLE TO TIME CHIP ROM/RAM = GND CEI OE Q WE = VIH OUTPUT DATA VALID tRC tOD tRR tCO tOE tCOE tODO tOEE ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ TIMING DIAGRAM: WRITE CYCLE TO TIME CHIP ROM/RAM = GND ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ WE CEI D OE = VIH DATA IN STABLE ÉÉÉÉÉ ÉÉÉÉÉ tDS tDH tDH tCW tWR tWR tWP tWC

TIMING DIAGRAM: READ CYCLE ROM/RAM = VCCO ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÉÉÉÉÉ ÉÉÉÉÉ OUTPUT DATA VALID tRC tCO tRR tOD tRR tRC tOE tAS tAS tOEE tCOE tODO tAH tAH CEI OE WE Q TIMING DIAGRAM: WRITE CYCLE ROM/RAM = VCCO ÇÇÇÇÇÇ ÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ DATA IN STABLE tWC tCW tWR tWR tWC tOW tAS tAS tAH tAH CEI OE WE D tDS tDS tDH tDH

TIMING DIAGRAM: POWER DOWN ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇ tCE tPD tCE tPF VBAT - 0.2V VIH VIL VIL VIH 4.5V tF CEI CEO CEO VCCI ROM/RAM = GND ROM/RAM = VCCO TIMING DIAGRAM: POWER UP ÇÇÇÇÇÇ ÇÇÇÇÇÇ 4.5V VIH VIL BAT - 0.2V tREC tPD VIL CEI CEO CEO VCCI ROM/RAM = GND ROM/RAM = VCCO TIMING DIAGRAM: RESET FOR TIME CHIP tRSTRST

NOTES: 1. All voltages are referenced to ground. 2. Measured with load shown in Figure 6. 3. Input pulse rise and fall times equal 10 ns. 4. t WR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. 5. tDH and tDS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode. 6. Measured without RAM connected. for 5% operation VBAT = 3.7V max. 8. ICC01 is the maximum average load current the DS1215 can supply to memory. 9. Applies to CEO with the ROM/RAM pin grounded. When the ROM/RAM pin is connected to VCCO , CEO will go to a low level as VCCI falls below VBAT. 10. ICC02 is the maximum average load current that the DS1215 can supply to memory in the battery backup mode. 11. Applies to all input pins except RST. RST is pulled internally to VCCI. OUTPUT LOAD Figure 6 +5V 50 pF 680Ω 1.1KΩ

C A B D H J K G E F DIM MIN MAX 16–PINPKG A IN. 0.740 0.780 MM B IN. 0.240 0.260 MM C IN. 0.120 0.140 MM D IN. 0.300 0.325 MM E IN. 0.015 0.040 MM F IN. 0.110 0.140 MM G IN. 0.090 0.110 MM H IN. 0.300 0.370 MM J IN. 0.008 0.012 MM K IN. 0.015 0.021 MM

DS1215S SERIAL TIMEKEEPER 16–PIN SOIC A FC E phi J GK L HB PKG 16–PIN DIM MIN MAX A IN. MM 0.402 10.21 0.412 10.46 B IN. MM 0.290 7.37 0.300 7.65 C IN. MM 0.089 2.26 0.095 2.41 E IN. MM 0.004 0.102 0.012 0.30 F IN. MM 0.094 2.38 0.105 2.68 G IN. MM

0.050 BSC

1.27 BSC

0.398 10.11 0.416 10.57 J IN MM 0.009 0.229 0.013 0.33 K IN. MM 0.013 0.33 0.019 0.48 L IN MM 0.016 0.40 0.040 1.02 PHI 0° 8°