DS1202

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DS1202, DS1202S Serial Timekeeping Chip DS1202, DS1202S Copyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. 032697 1/11

FEATURES

• Real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100
• 24 x 8 RAM for scratchpad data storage
• Serial I/O for minimum pin count
• 2.0–5.5 volt full operation
• Uses less than 300 nA at 2 volts
• Single–byte or multiple–byte (burst mode) data trans- fer for read or write of clock or RAM data
• 8–pin DIP or optional 16–pin SOIC for surface mount
• Simple 3–wire interface
• TTL–compatible (VCC = 5V)
• Optional industrial temperature range –40°C to +85°C (IND)

ORDERING INFORMATION

DS1202 8–pin DIP DS1202S 16–pin SOIC DS1202S–8 8–pin SOIC DS1202N 8–pin DIP (IND) DS1202SN 16–pin SOIC (IND) DS1202SN–8 8–pin SOIC (IND) PIN ASSIGNMENT NC NC NC NC NC GND VCC NC SCLK NC I/O NC NC RST 16–PIN SOIC 8–PIN DIP VCC SCLK I/O RST NC GND VCC SCLK I/O RST NC GND 8–PIN SOIC (208 mil) PIN DESCRIPTION NC – No Connection X1, X2 – 32.768 KHz Crystal Input GND – Ground RST – Reset I/O – Data Input/Output SCLK – Serial Clock V CC – Power Supply Pin

DESCRIPTION

The DS1202 Serial Timekeeping Chip contains a real time clock/calendar and 24 bytes of static RAM. It com- municates with a microprocessor via a simple serial in- terface. The real time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with less than 31 days, including corrections for leap year. The clock operates in either the 24–hour or 12–hour format with an AM/PM indicator. Interfacing the DS1202 with a microprocessor is simplified by using synchronous serial communication. Only three wires are required to communicate with the clock/RAM: (1) RST (Reset), (2) I/O (Data line), and (3) SCLK (Serial clock). Data can be transferred to and from the clock/ RAM one byte at a time or in a burst of up to 24 bytes. The DS1202 is designed to operate on very low power and retain data and clock information on less than 1 mi- crowatt.

DS1202, DS1202S 032697 2/11 OPERATION The main elements of the Serial Timekeeper are shown in Figure 1: shift register, control logic, oscillator, real time clock, and RAM. To initiate any transfer of data, RST is taken high and eight bits are loaded into the shift register providing both address and command informa- tion. Data is serially input on the rising edge of the SCLK. The first eight bits specify which of 32 bytes will be ac- cessed, whether a read or write cycle will take place, and whether a byte or burst mode transfer is to occur. After the first eight clock cycles have occurred which load the command word into the shift register, additional clocks will output data for a read or input data for a write. The number of clock pulses equals eight plus eight for byte mode or eight plus up to 192 for burst mode. COMMAND BYTE The command byte is shown in Figure 2. Each data transfer is initiated by a command byte. The MSB (Bit 7) must be a logic 1. If it is zero, further action will be termi- nated. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits one through five specify the designated registers to be input or output, and the LSB (Bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. The command byte is al- ways input starting with the LSB (bit 0). DS1202 BLOCK DIAGRAM Figure 1

32.768 KHz

CONTROL LOGIC ADDRESS BUS 24 X 8 RAM I/O SCLK RST ADDRESS/COMMAND BYTE Figure 2 7 6 RD W RAM CK

DS1202, DS1202S 032697 3/11 RESET AND CLOCK CONTROL All data transfers are initiated by driving the RST input high. The RST input serves two functions. First, RST turns on the control logic which allows access to the shift register for the address/command sequence. Second, the RST signal provides a method of terminating either single byte or multiple byte data transfer. A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on t he falling edge of clock. All data transfer terminates if the RST in- put is low and the I/O pin goes to a high impedance state. Data transfer is illustrated in Figure 3. DATA INPUT Following the eight SCLK cycles that input a write com- mand byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ig- nored should they inadvertently occur. Data is input starting with bit 0. Due to the inherent nature of the logic state machine, writing times containing an absolute value of “59” seconds should be avoided. DATA OUTPUT Following the eight SCLK cycles that input a read com- mand byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadver- tently occur so long as RST remains high. This opera- tion permits continuous burst mode read capability. Data is output starting with bit 0. BURST MODE Burst mode may be specified for either the clock/calen- dar or the RAM registers by addressing location 31 deci- mal (address/command bits one through five = logical one). As before, bit six specified clock or RAM and bit 0 specifies read or write. There is no data storage capac- ity at locations 8 through 31 in the Clock/Calendar Reg- isters or locations 24 through 31 in the RAM registers. When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 24 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 24 bytes are written or not. CLOCK/CALENDAR The clock/calendar is contained in eight write/read reg- isters as shown in Figure 4. Data contained in the clock/ calendar registers is in binary coded decimal format (BCD). CLOCK HALT FLAG Bit 7 of the seconds register is defined as the clock halt flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1202 is placed into a low–power standby mode with a current drain of not more than 100 nanoamps. When this bit is written to logic 0, the clock will start. AM–PM/12–24 MODE Bit 7 of the hours register is defined as the 12– or 24–hour mode select bit. When high, the 12–hour mode is selected. In the 12–hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24–hour mode, bit 5 is the second 10 hour bit (20–23 hours). WRITE PROTECT BIT Bit 7 of the control register is the write protect bit. The first seven bits (bits 0–6) are forced to zero and will al- ways read a zero when read. Before any write operation to the clock or RAM, bit 7 must be zero. When high, the write protect bit prevents a write operation to any other register. CLOCK/CALENDAR BURST MODE The clock/calendar command byte specifies burst mode operation. In this mode the eight clock/calendar registers can be consecutively read or written (see Fig- ure 4) starting with bit 0 of address 0. RAM The static RAM is 24 x 8 bytes addressed consecutively in the RAM address space. RAM BURST MODE The RAM command byte specifies burst mode opera- tion. In this mode, the 24 RAM registers can be consec- utively read or written (see Figure 4) starting with bit 0 of address 0.

DS1202, DS1202S 032697 4/11 REGISTER SUMMARY A register data format summary is shown in Figure 4. CRYSTAL SELECTION A 32.768 KHz crystal, can be directly connected to the DS1202 via pins 2 and 3 (X1, X2). The crystal selected for use should have a specified load capacitance (CL) of 6 pF. The crystal is connected directly to the X1 and X2 pins. There is no need for external capacitors or resis- tors. Note: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal be guard– ringed with ground and that high frequency signals be kept away from the crystal area. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal Consider- ations with Dallas Real Time Clocks”. DATA TRANSFER SUMMARY Figure 3 SCLK I/O RST 01 23456 701 234 56 7 R/W A0 A1 A2 A3 A4 1 ADDRESS COMMAND DATA INPUT/OUTPUT SINGLE BYTE TRANSFER SCLK I/O 01 23456 701 2 4 56 7 1 1111 1 ADDRESS COMMAND DATA I/O BYTE N BURST MODE TRANSFER RST R/W DATA I/O BYTE 1 R/C R/C FUNCTION BYTE N SCLK n CLOCK 8 72 RAM 24 200

DS1202, DS1202S 032697 5/11 REGISTER ADDRESS/DEFINITION Figure 4 7 6 RD W REGISTER ADDRESS REGISTER DEFINITION 1 0 0 0 0 1 RD0 W 1 0 0 0 1 0 RD0 1 0 0 0 1 1 RD0 W W 1 0 0 1 0 0 RD0 1 0 0 1 0 1 RD0 1 0 0 1 1 0 RD0 1 0 0 1 1 1 RD0 W W W W 1 1 1 1 1 1 RD0 W 1 0 0 0 0 0 RD1 1 1 0 1 1 1 RD1 1 1 1 1 1 1 RD1 W W W A. CLOCK B. RAM SEC MIN HR DATE MONTH DAY YEAR CONTROL CLOCK BURST CH SEC10 SEC 12/ HR HR0 0 10 DATE0 0 0 100 0 0 00

10 YEAR

00–59 00–59 01–12 01–28/29 01–12 01–07 0–99 RAM 0 RAM 23 RAM BURST RAM DATA 0 RAM DATA 23 MIN10 MIN 00–23 24 A/P 01–30 01–31 DATE M MONTH YEAR DAY0 FORCED TO ZERO

DS1202, DS1202S 032697 6/11 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground –0.3V to +7.0V Operating Temperature 0 °C to 70°C Storage Temperature –55 °C to +125°C Soldering Temperature 260 °C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS (0°C to 70°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Supply Voltage VCC 2.0 5.5 V 1 Logic 1 Input VIH 2.0 VCC +0.3 V 1 Logic 0 Input VIL V 1Logic 0 Input VIL VCC =5V –0.3 +0.8 V 1 DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 2.0 to 5.5V*) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage ILI +500 µA 6 I/O Leakage ILO +500 µA 6 Logic 1 Output VOH VCC =2V 1.6 V 2Logic 1 O utput VOH VCC =5V 2.4 V 2 Logic 0 Output VOL VCC =2V 0.4 V 3Logic 0 O utput VOL VCC =5V 0.4 V 3 Active Supply Current ICC VCC =2V 0.4 mA 5Active Supply C urrent ICC VCC =5V 1.2 m A 5 Timekeeping Current ICC1 VCC =2V 0.3 µA 4Time keeping C urrent ICC1 VCC =5V 1 µA 4 Leakage Current ICC2 VCC =2V 100 nA 10Leakage C urrent ICC2 VCC =5V 100 nA 10 *Unless otherwise noted. CAPACITANCE (tA = 25°C) PARAMETER SYMBOL CONDITION TYP MAX UNITS NOTES Input Capacitance C I 5 pF I/O Capacitance C I/O 10 pF Crystal Capacitance C X 6 pF

DS1202, DS1202S 032697 7/11 AC ELECTRICAL CHARACTERISTICS (0°C to 70°C; VCC = 2.0 to 5.5V*) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Data to CLK Setup tDC VCC =2V 200 ns 7D ata to CLK Setup tDC VCC =5V 50 ns 7 CLK to Data Hold tCDH VCC =2V 280 ns 7CLK to D ata H old tCDH VCC =5V 70 ns 7 CLK to Data Delay tCDD VCC =2V 800 ns 789CLK to D ata D elay tCDD VCC =5V 200 ns 7, 8, 9 CLK Low Time tCL VCC =2V 1000 ns 7CLK Low Time tCL VCC =5V 250 ns 7 CLK High Time tCH VCC =2V 1000 ns 71 2CLK High Time tCH VCC =5V 250 ns 7, 12 CLK Frequency fCLK VCC =2V 0.5 MHz 71 2CLK Frequency fCLK VCC =5V DC 2.0 MH z 7, 12 CLK Rise and Fall tR tF VCC =2V 2000 nsCLK Rise and Fall tR , tF VCC =5V 500 ns RST to CLK Setup tCC VCC =2V 4 µs 7RST to CLK Setup tCC VCC =5V 1 µs 7 CLK to RSTHold tCCH VCC =2V 1000 ns 7CLK to RST H old tCCH VCC =5V 250 ns 7 RST Inactive Time tCWH VCC =2V 4 µs 7RST Inactive Time tCWH VCC =5V 1 µs 7 RST to I/O High Z tCDZ VCC =2V 280 ns 7RST to I/O High Z tCDZ VCC =5V 70 ns 7 *Unless otherwise noted.

DS1202, DS1202S 032697 8/11 TIMING DIAGRAM: READ DATA TRANSFER Figure 5 tCC tCDZ tCDDtCDH tDC 01 7 RESET CLOCK DATA INPUT/ OUTPUT COMMAND BYTE TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6 tCC RESET CLOCK DATA INPUT/ OUTPUT 7 tCWH tCCH tCDH tDC tF tR tCH tCL COMMAND BYTE NOTES: 1. All voltages are referenced to ground. 2. Logic one voltages are specified at a source current of 1 mA at VCC =5V and 0.4 mA at VCC =2V, VOH =VCC for capacitive loads. 3. Logic zero voltages are specified at a sink current of 4 mA at VCC =5V and 1.5 mA at VCC =2V. 4. ICC1 is specified with I/O open, RST set to a logic 0, and clock halt flag=0 (oscillator enabled). 5. ICC is specified with the I/O pin open, RST high, SCLK=2 MHz at VCC =5V; SCLK=500 KHz, VCC =2V and clock halt flag=0 (oscillator enabled). 6. RST, SCLK, and I/O all have 40KΩ pull–down resistors to ground. 7. Measured at VIH=2.0V or VIL=0.8V and 10 ms maximum rise and fall time. 8. Measured at VOH =2.4V or VOL =0.4V. 9. Load capacitance = 50 pF.

DS1202, DS1202S 032697 9/11 10. ICC2 is specified with RST, I/O, and SCLK open. The clock halt flag must be set to logic one (oscillator disabled). 11. At power–up, RST must be at a logic 0 until VCC 2 volts. Also, SCLK must be at a logic 0 when RST is driven to a logic one state. 12. If tCH exceeds 100 ms with RST in a logic one state, then ICC may briefly exceed ICC specification. DS1202 SERIAL TIMEKEEPER 8–PIN DIP C A B H J K G E F A IN. 0.360 0.400 MM B IN. 0.240 0.260 MM C IN. 0.120 0.140 MM D IN. 0.300 0.325 MM E IN. 0.015 0.040 MM F IN. 0.110 0.140 MM G IN. 0.090 0.110 MM H IN. 0.320 0.370 MM J IN. 0.008 0.012 MM K IN. 0.015 0.021 MM 8–PINPKG D DIM MIN MAX

DS1202, DS1202S 032697 10/11 DS1202S SERIAL TIMEKEEPER 16–PIN SOIC DIM MIN MAX 16–PINPKG A IN. 0.500 0.511 MM 12.70 12.99 B IN. 0.290 0.300 MM 7.37 7.65 C IN. 0.089 0.095 MM 2.26 2.41 E IN. 0.004 0.012 MM 0.102 0.30 F IN. 0.094 0.105 MM 2.38 2.68 G IN. MM H IN. 0.398 0.416 MM 10.11 10.57 J IN. 0.009 0.013 MM 0.229 0.33 K IN. 0.013 0.019 MM 0.33 0.48 L IN 0.016 0.040 MM 0.406 1.20 phi 0 ° 8° A F C E phi J GK LHB

0.050 BSC

1.27 BSC

DS1202, DS1202S 032697 11/11 DS1202S8 8–PIN SOIC 200 MIL B J K G C E 0–8 deg. typ. DIM MIN MAX 8–PINPKG A IN. 0.203 0.213 MM 5.16 5.41 B IN. 0.203 0.213 MM 5.16 5.41 C IN. 0.070 0.074 MM 1.78 1.88 E IN. 0.004 0.010 MM 0.102 0.390 F IN. 0.074 0.84 MM 1.88 2.13 G IN. 0.050 BSC MM 1.27 BSC H IN. 0.302 0.318 MM 7.67 8.07 J IN. 0.006 0.010 MM 0.152 0.254 K IN. 0.013 0.020 MM 0.33 0.508 L IN. 0.19 0.030 MM 4.83 0.762 A H L F