DS1100 DALLAS | Alldatasheet

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Technical content

FEATURES

/g167 All-Silicon Timing Circuit /g167 Five Taps Equally Spaced /g167 5V Operation /g167 Delays are Stable and Precise /g167 Both Leading- and Trailing-Edge Accuracy /g167 Improved Replacement for DS1000 /g167 Low-Power CMOS /g167 TTL/CMOS-Compatible /g167 Vapor-Phase, IR, and Wave Solderable /g167 Custom Delays Available /g167 Fast-Turn Prototypes /g167 Delays Specified Over Both Commercial and Industrial Temperature Ranges PIN ASSIGNMENT PIN DESCRIPTION TAP 1 to TAP 5 - TAP Output Number VCC - +5V GND - Ground IN - Input

DESCRIPTION

The DS1100 series delay lines have five equally spa ced taps providing delays from 4ns to 500ns. These devices are offered in 8-pin DIPs and surface-mount packages to save PC board area. Low cost and superior reliability over hybrid te chnology is achieved by the combin ation of a 100% silicon delay line and industry-standard DIP and SO packaging. Th e DS1100 5-tap silicon delay line reproduces the input- logic state at the output after a fixed delay as specifie d by the extension of the part number after the dash. The DS1100 is designed to reproduce both leading and trailing edges with equal precision. Each tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to meet special needs. DS1100 5-Tap Economy Timing Element (Delay Line) www.maxim-ic.com VCC TAP 1 TAP 3 TAP 5 IN TAP 2 TAP 4 GND DS1100M DIP (300mil) DS1100Z SO (150mil) DS1100U µSOP

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.5V to +6.0V Operating Temperature Range -40°C to +85°C Storage Temperature Range -55°C to +125°C Soldering Temperature See IPC/JEDEC J-STD-020A Specification Short-Circuit Output Current 50mA for 1s *This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±5%, TA = -40°C to +85°C.) PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS NOTES Supply Voltage V CC 4.75 5.00 5.25 V 5 High-Level Input Voltage VIH 2.2 VCC + 0.3 V5 Low-Level Input Voltage VIL -0.3 0.8 V 5 Input-Leakage Current II 0.0V /g163 VI /g163 VCC -1.0 1.0 µA Active Current I CC VCC = Max; Freq = 1MHz 30 50 mA 6, 8 High-Level Output Current IOH VCC = Min; VOH = 4 -1 mA Low-Level Output Current IOL VCC = Min; VOL = 0.5 12 mA AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ±5%, TA = -40°C to +85°C.) PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS NOTES Input Pulse Width tWI 20% of Tap 5 tPLH ns 9 +25°C 5V -2 Table 1 +2 ns 1, 3, 4, 7 0°C to +70°C -3 Table 1 +3 ns 1, 2, 3, 4, 7 Input-to-Tap Delay Tolerance (Delays /g163 40ns) t PLH, tPHL -40°C to +85°C -4 Table 1 +4 ns 1, 2, 3, 4, 7 +25°C 5V -5 Table 1 +5 % 1, 3, 4, 7 0°C to +70°C -8 Table 1 +8 % 1, 2, 3, 4, 7 Input-to-Tap Delay Tolerance (Delays > 40ns) t PLH, tPHL -40°C to +85°C -13 Table 1 +13 % 1, 2, 3, 4, 7 Power-Up Time t PU 200 µs Input Period Period 2(t WI)n s 9 CAPACITANCE (TA = +25°C) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C IN 51 0 p F

temperature range, and a supply-voltage range of 4.75V to 5.25V. TAP1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2. 5) All voltages are referenced to ground. 6) Measured with outputs open. 7) See Test Conditions section at the end of this data sheet. 8) Frequencies higher than 1MHz result in higher ICC values. Figure 3. TEST CIRCUIT

Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse. tFALL (Input Fall Time): The elapsed time between the 80% and the 20% point on the trailing edge of the input pulse. tPLH (Time Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input pulse and the 1.5V point on the leading edge of any tap output pulse. tPHL (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input pulse and the 1.5V point on the trailing edge of any tap output pulse. TEST SETUP DESCRIPTION Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1100. The input waveform is produced by a precision-pulse generator under so ftware control. Time delays are measured by a time interval counter (20ps resolution) connected between the input and each tap. Each tap is selected and connected to the counter by a VH F switch control unit. All measurements are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus. TEST CONDITIONS INPUT : Ambient Temperature: +25°C ±3°C Supply Voltage (VCC): 5.0V ±0.1V Input Pulse: High = 3.0V ±0.1V Low = 0.0V ±0.1V Source Impedance: 50 /g87 max Rise and Fall Time: 3.0ns max (m easured between 0.6V and 2.4V) Pulse Width: 500ns (1µs for -500 version) Period: 1µs (2µs for -500 version) OUTPUT: Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on the rising and falling edge. NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions.

ORDERING INFORMATION

EXAMPLE: The DS1100Z-250 is a 250ns delay (input-to-tap 5) DS1100 in the SO package. DS1100 TOTAL TIME DELAY (ns): 20, 100, 125, 150, 175, 200, 250, 300, 500 PACKAGE TYPE: M = DIP Z = SO (150MIL) U = µSOP