DS1003

DS1003 DALLAS | Alldatasheet

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DALLAS 4-Tap Silicon Delay Line CONDUCT for RISC Applications FEATURES PIN ASSIGNMENT © All-silicon time delay i wt ~ 14] vee Four delayed clock phases from input wo fle tot] vars Input frequency independent noEls ta] nc © Precise tap-to-tap delays ne []4 aif] tape -_ w+ ~ 6D vec @ Leading and trailing edge precision wee[s lfsc Aes Fras ne[]s of] no © Preserves input symmetry maps] 5 6 [tare eno []7 al] taP4 nol] « 5 [taps © Output rise time minimizes ringing DS1003 14-PIN DIP DS 1008M &-PIN DIP

200 MIL (300 MIL

• Economical See Mech Drawings See Mesh Drawings , Section Section © 8- and 14-pin packages available in DIP and surface mount ; PIN DESCRIPTION TTLUCMOS-compatible TAP 1-—TAP 4 — TAP Output Number © Vapor phase, IR and wave solderable Voc — 45 Volts GND = Ground * Custom delays and pinouts available NC = No Connection © Fast tum prototypes IN — Input

DESCRIPTION

The DS1003 Delay Line has been specifically designed Since the DS1003 is not based on Phase Locked Loop to supply the four independent clock timing phases re- (PLL) technology, timing is input frequency-indepen- quired by some RISC microprocessors andiheirrelated dent. Each tap is capable of driving a minimum of four coprocessors. For optimum compatibility, the DS1003_- LSTTL or CMOS loads. Tap-to-tap timing accuracy is accepts TTL input levels and supplies CMOS and TTL __not affected by the addition of equal capacitive loads compatible output levels. The DS1003 is offered in 8- _(e.g. coprocessors). and 14-pin DIP packages. Low cost and superior reli- ability is achieved by the combination of a 100% silicon Dallas Semiconductor can customize standard prod- delay line and industry standard packaging. The ucts to meet special needs. For special requests and DS1003 series of delay lines provides precise tap-to- _rapid delivery, call (214) 371-4348, tap delays while preserving input waveform symmetry. 021798 177

£\\ LN L\\ L\\ PART NUMBER DELAY TABLE (tp) Table 1 PaRTNO. | —_| Dsi003-16 | Dsi003-20 | Dsi003.25 | Dst003-33 | DS1003-40 TAP 1-TAP4 | Delay 1+ | 16nstins | 14nsttns | 12ns+.75ns | 9ns+.75ns | 8ns+.75ns Delay 2 TAP 2- TAPS O2ns+ O.2ns+ O2ns+ O2ns+ O2ns+ (Note 10) ‘2ns ‘2ns ‘2ns ‘2ns ‘2ns PERIOD AND WIDTH TABLE Table 2 mare [wT wom [wax [wn [wom [wax | fos | see | are | = | tare] tem [= fosomae [ave] am [= | em | em | =] [osiorsao | vee | asm [| = | sm] tem [=] Icc TABLE Table 3 PARTNO. Pee a a a cc 021798 277

ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -1.0V to 47.0V Operating Temperature 0° to 70°C Storage Temperature -BB°C to +125°C Soldering Temperature 260°C for 10 seconds Short Circuit Output Current 50 mA for 1 second * This isa stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. DC ELECTRICAL CHARACTERISTICS (0°C to 70°C; Voc = 5.0V + 5%) TEST PARAMETER SYMBOL | CONDITIONS TYP NoTES High Level Input Vin Veo + v 1 Voltage 05 Active Current loo Voo = Max; Table 3 | Tables | mA Period = Min High Level Output Voc = Min. mA Current Vou=4 Low Level Output lou Voc = Min 12 mA Current Von =05 AC ELECTRICAL CHARACTERISTICS (Ty = 25°C; Voc = 5.0V + 5%) Input Pulse Width [tm | Table2 | Table2 | Tabie2 | ns | 6 | TAP to TAP Delay (leading edge) Tablet | Tablet | Tablet | ns | 34.567 [oupnrertoe | [| 20 [as [mf a] [Powe [ef |e CAPACITANCE (Ta = 25°C) (rnaneren [smo [ wn [ ve [ wae [ ore noes | 21786 37

NOTES: 1. All voltages are referenced to ground. 2. Measured with outputs open, minimum period. 3. Voc = 5V @ 25°C. 4. Temperature variations from 25°C to 0°C or 70°C may produce an additional tap-to-tap delay shift of +0.5 ns. Voltage variations from 5.0V to 4.75V or 5.25V produce a worst case tap-to-tap delay shift of 5%. 5. Alltap-to-tap delays vary unidirectionally over temperature or voltage range. For example, if the TAP 1 - TAP 2 delay, tpi. slows down, the TAP2 - TAP 4 delay, tpi, will also slow down. Since tp tracks tpy. symme- try is preserved. 6. See “Test Conditions" section at the end of this data sheet. 7. Since all four taps have identical output stages, tap-to-tap delays and waveform symmetry will exhibit minimal variation when capacitive loading is increased identically on all taps at the same time (e.g., the addition of one or more RISC coprocessors). 8. Voc = Min; C, = 30 pF 9. Trailing edge delays, tpj,, are adjusted to maintain waveform symmetry. 10. Guaranteed by design. Periodically tested. TIMING DIAGRAM: SILICON DELAY LINE Figure 2 PERIOD tor tor Vo. 3.0V 3.01 1.5V 0 1.5V 1.5V TAP Vv, o4v 0.4) tw twi ten {PL two NEXT TAP 15V1.5V 021798 4/7

POWER-UP TIMING DIAGRAM Figure 3 475V teu Voc t — tip in 2.4V 2.4V 1.5V IN ev o6v tpun. two 1.5V 1.5V TAP TEST CIRCUIT Figure 4 PULSE GENERATOR START TIP (TIME INTERVAL PROBE) V Y % TIME INTERNAL @ COUNTER Ole [Do > = VHF SWITCH DEVICE UNDER TEST CONTROL UNIT BUFFER R788 BF

TYPICAL APPLICATION Figure 5 Ds1003 3000 OSCILLATOR DELAY LINE CPU "2x" IN TAP 4 Cik2xSys FREQ tape |) | Okoxra taps | TT Cikaxsmp Tapa [TT | cikaxphi TaPt 3010 Clk2xSys COPROCESSOR TAp2 | tao ClkexRd O1k2xS) TAPS ‘sue CT chown Cik2xSmp LL] cixexsmp TAPS tsys L] cikexPhi CikexPhi NOTE: TAP 2 can be used for Cik2xSmp with TAP 3 as Cik2xRd. TERMINOLOGY tor (Output Rise Rime ): The elapsed time between Period: The time elapsed between the leading edge of 0.4V and 3.0V on the leading edge of the output pulse. the first trigger pulse and the leading edge of the follow- ing pulse. tor (Output Fall Time): The elapsed time between 3.0V and 0.4V of the trailing edge output pulse. Symmetry: That percent of the Period when the input or output is above 1.5V. tpiy (Time Delay, Rising): Input-to-tap or tap-to-tap delay measured between the 1.5V points on the leading tw (Pulse Width): The elapsed time on the pulse be- _ edges. tween the 1.5V point on the leading edge and the 1.5V point on the trailing edge, orthe 1.5V pointonthetrailing py, (Time Delay, Falling): Input-to-tap or tap-to-tap edge and the 1.5V point on the leading edge. delay measured between the 1.5V points on the trailing edges. tip (Input Rise Time): The elapsed time between 0.6V and 2.4V on the leading edge of the input pulse. tpy (Power-up Time): After Vc is valid, the time re- quired before timing specifications are within tolerance. tir (Input Fall Time): The elapsed time between 2.4V and 0.6V on the trailing edge of the input pulse. 021798 6/7

TEST SETUP DESCRIPTION Output: Figure 4 illustrates the hardware configuration used for __ Each output is loaded with the equivalent of one 74F04 measuring the timing parameters on the DS1003. The _input. Delays are measured at the 1.5V level. input waveform is produced by a precision pulse gener- ator under software control. Time delays are measured Note: by a time interval counter (20 ps resolution connected —_ Above conditions are for test only. The adjusted test lim- between the input and each tap). Each tap is selected —_its and guardbands used assure operation to data sheet and connected to the counter by a VHF switch control timing specifications. unit, All measurements are fully automated, with each instrument controlled by a central computer over an IEEE 488 bus. TEST CONDITIONS Input: Ambient Temperature: 25°C +3°C Supply Voltage (Vcc): 5.0V+01V Input Pulse: High = 3.0V+0.1V Low = 0.0V+0.1 Source Impedance 50 ohm max. Rise and Fall Time 3.0 ns max. (measured between 0.6V and 2.4) Pulse Width: 500 ns Period: 1000 ns 021798 717

8- TO 28-PIN DIP (300 MIL) Includes: DS1000 pst2i1 ost621 Ds1000m ps1215, os1625 B DS1003 ps1221 Dsi632 DS1003M S122 Ds1640 Hd DS1004M Ds1228 Ds1651 S105 Ds1229 ps1652

1 DS1005M Ds1231 s16528

Dst010 DSi2a2LP DS 1666. DS1012M 0S1234 DS1667 o DS1013 DS1236 Ds1669 DS1013M Dsi237 Ds1802 E Ds1020 0S1238 Ds1830 c WY DS1033M Ds1239 Ost832 TF J 0S1035M DS1259 0s1867 F DS1040M 0S1267 DS1868 a. — Ds1044 Ds1275 DS1869 K | ke +— H —| DS1045 081291 0820090 0S1200 Ds1293 $2010 Ds1206 DS1336 DS2011D 0S1210 DS1620 DS2013D 610 | 660 | 610 | 660 | 610 | 680 | 610 | 660 0.120 | 0.140 0140 | 0.120 | 0.140 3.05 | 3.56 356 | 305 | 3.56 3.04 3.56 279 3.56 3.56 2.29 229 | 279 | 229 | 279 | 229 | 279 313 | 940 | 813 | 940 | 813 | 940 | 819 | 9.40 020 | 030 | 020 | 030 | 020 | 030 | 020 | 030 038 | 053 | 038 | 053 | 0.38 0.38 Continued on following page. apy 185 by Dates Semicon Conoraton 081695 1/35 [AL Rights Reseried For mporart formation tgardig ened eat asey ama ao Mi 2b14130 0014415 109