DG403AK883

DG401 TEMIC | Alldatasheet

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Technical content

NC V– /C0055 /C0056 NC NC GND NC /C0068 NC NC V L NC /C0068 /C0055 /C0056 /C0055 /C0056 DG401 DG401/403/405 Siliconix S-53748—Rev. E, 05-Jun-97 Low-Power, High-Speed CMOS Analog Switches Features Benefits Applications 44-V Supply Max Rating 15-V Analog Signal Range On-Resistance—rDS(on): 20 Low Leakage—I D(on): 40 pA Fast Switching—tON : 100 ns Ultra Low Power Requirements—P D : 0.35 W TTL, CMOS Compatible Single Supply Capability Wide Dynamic Range Low Signal Errors and Distortion Break-Before-Make Switching Action Simple Interfacing Audio and Video Switching Sample-and-Hold Circuits Battery Operation Test Equipment Hi-Rel Systems PBX, PABX

Description

The DG401/403/405 monolithic analog switches were designed to provide precision, high performance switching of analog signals. Combining low power (0.35 W, typ) with high speed (tON : 100 ns, typ), the DG401 series is ideally suited for portable and battery powered industrial and military applications. Built on the Siliconix proprietary high-voltage silicon-gate process to achieve high voltage rating and superior switch on/off performance, break-before-make is guaranteed for the SPDT configurations. An epitaxial layer prevents latchup. Each switch conducts equally well in both directions when on, and blocks up to 30 V peak-to-peak when off. On-resistance is very flat over the full 15-V analog range, rivaling JFET performance without the inherent dynamic range limitations. The three devices in this series are differentiated by the type of switch action as shown in the functional block diagrams. Functional Block Diagrams and Pin Configurations Two SPST Switches per Package Truth Table Logic Switch

0 OFF

Logic “0” 0.8 V Logic“1” 24VLogic “1” 2.4 V Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70049.

D 3 V– S3 GND S4 V L D 4 V+ NC IN2 D 2 S2 /C0055 /C0056 D 3 GND NC /C0068 NC V L D 4 /C0068 /C0055 /C0056 /C0055 /C0056 DG403 DG405 D 1 S1 NC Dual-In-Line and SOIC IN1 D 3 V– S3 GND S4 V L D 4 V+ NC IN2 D 2 S2 /C0055 /C0056 D 3 GND NC /C0068 NC V L D 4 /C0068 /C0055 /C0056 /C0055 /C0056 DG405 DG401/403/405

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S-53748—Rev. E, 05-Jun-97 Functional Block Diagrams and Pin Configurations (Cont’d) Two SPDT Switches per Package Truth Table Logic SW 1, SW2 SW 3, SW4

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Logic “0” /C0118 0.8 V Logic “1” /C0119 2.4 VLogic 1 /C0119 2.4 V Two DPST Switches per Package Truth Table Logic Switch Logic “0” /C0118 0.8 V Logic “1” /C0119 2.4 VLogic 1 /C0119 2.4 V

S-53748—Rev. E, 05-Jun-97

Ordering Information

Temp Range Package Part Number DG401 –40 to 85/C0095C 16-Pin Plastic DIP DG401DJ 16-Pin CerDIP DG401AK –55 to 125/C0095C 16-Pin C erDIP DG401AK/883 LCC-20 DG401AZ/883 DG403 –40 to 85/C0095C 16-Pin Plastic DIP DG403DJ –40 to 85/C0095C 16-Pin Narrow SOIC DG403DY 16-Pin CerDIP DG403AK –55 to 125/C0095C 16-Pin C erDIP DG403AK/883 LCC-20 5962-8976301M2A DG405 –40 to 85/C0095C 16-Pin Plastic DIP DG405DJ –40 to 85/C0095C 16-Pin Narrow SOIC DG405DY –55 to 125/C0095C 16-Pin CerDIP DG405AK/883 –55 to 125/C0095C LCC-20 5962-89961012A Absolute Maximum Ratings or 30 mA, whichever occurs first Power Dissipation (Package)b Notes: a. Signals on SX , DX , or INX exceeding V+ or V– will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 6 mW//C0095C above 75/C0095C d. Derate 12 mW//C0095C above 75/C0095C e. Derate 7.6 mW//C0095C above 75/C0095C f. Derate 13 mW//C0095C above 75/C0095C

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S-53748—Rev. E, 05-Jun-97 Specificationsa Test Conditions Unless Specified A Suffix –55 to 125/C0095C D Suffix –40 to 85/C0095C Parameter Symbol V L = 5 V , VIN = 2.4 V , 0.8 Vf Temp b Typ c Min d Max d Min d Max d Unit Analog Switch Analog Signal Rangee VANALOG Full –15 15 –15 15 V Drain-Source On-Resistance rDS(on) IS = –10 mA, VD = 10 V Room Full 20 35 /C0087/C0068 Drain-Source On-Resistance /C0068rDS(on) IS = –10 mA, VD = 5 V , 0 V Room Full 3 3 /C0087 Switch Off Lk C IS(off) V1 5 5 V V 1 5 5 V Room Hot –0.01 –0.25 –20 0.25 –0.5 0.5 Leakage Current ID(off) V D = 15.5 V , VS = /C003515.5 V Room Hot –0.01 –0.25 –20 0.25 –0.5 0.5 5 nA Channel On Leakage Current ID(on) V S = VD = 15.5 V Room Hot –0.04 –0.4 –40 0.4 –10 Digital Control Input Current VIN Low IIL V IN under test = 0.8 V All Other = 2.4 V Full 0.005 –1 1 –1 1 /C0109A Input Current VIN High IIH V IN under test = 2.4 V All Other = 0.8 V Full 0.005 –1 1 –1 1 /C0109A Dynamic Characteristics Turn-On Time tON R L = 300 /C0087, CL = 35 pF SF i 2 Room 100 150 150 Turn-Off Time tOFF L , L p See Figure 2 Room 60 100 100 ns Break-Before-Make Time Delay (DG403) tD R L = 300 /C0087, CL = 35 pF Room 12 5 5 ns Charge Injection Q C L = 10,000 pF V gen = 0 V , Rgen = 0 /C0087 Room 60 pC Off Isolation Reject Ratio OIRR R L = 100/C0087C L =5p F Room 72 Channel-to-Channel Cross- talk X TALK R L = 100 /C0087, C L = 5 pF f = 1 MHz Room 90 dB Source Off Capacitance C S(off) Room 12 Drain Off Capacitance C D(off) f = 1 MHz, VS = 0 V Room 12 pF Channel On Capacitance C D , C S(on) Room 39 Power Supplies Positive Supply Current I+ Room Full 0.01 1 Negative Supply Current I– V0 5 V Room Full –0.01 –1 /C0109A Logic Supply Current IL V IN = 0 or 5 V Room Full 0.01 1 /C0109A Ground Current IGND Room Full –0.01 –1 Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 /C0095C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY , not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. V IN = input voltage to perform proper function.

S-53748—Rev. E, 05-Jun-97 Typical Characteristics V L = 5 V C L = 10 k pF 1 k pF 100 pF Input Switching Threshold vs. Supply VoltagesInput Switching Threshold vs. Logic Supply Voltage (V)TV 0 2 4 6 8 10 12 14 16 18 20 V+ = 15 V V– = –15 V TA = 25/C0095C DG403 SW3, 4 3.5 3.0 2.5 51 0 4 0 2.0 1.5 1.0 0.5 15 20 25 30 35(V+) V L = 5 V V L = 7 V (V)INV V L – Logic Supply (V) V D – Drain V oltage (V) rDS(on) vs. VD and Temperature Charge Injection vs. Analog Voltage Q (pC) rDS(on) vs. VD and Power Supply Voltage rDS(on) vs. VD and Power Supply Voltage (V– = 0 V) –15 –10 15 –5 0 5 10 –25 –15 26 –5 5 15 02 5 2015105 200 180 140 –15 –10 –5 0 5 10 15 160 120 100 V S – Source V oltage (V) V D – Drain V oltage (V) V D – Drain V oltage (V) 35 40 TA = 25/C0095C TA = 25/C0095C 25/C0095C 85/C0095C 0/C0095C –40/C0095C –55/C0095C 125/C0095C V L = 5 V 6 V 10 V 12 V 15 V 20 V 22 V 7.5 V 10 V 12 V 15 V 20 V 22 V rDS(on) – Drain-Source On-Resistance ( rDS(on) – Drain-Source On-Resistance ( rDS(on) – Drain-Source On-Resistance ( /C0041 /C0041 /C0041

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S-53748—Rev. E, 05-Jun-97 Typical Characteristics (Cont’d) Leakage Current vs. Analog VoltageLeakage Current vs. Temperature (pA)I , ISD Temperature (/C0095C) ID(off)100 pA –55 –35 –15 5 25 45 65 85 105 125 0.1 pA 1 pA 10 pA 1 nA 10 nA 100 nA V+ = 15 V V– = –15 V V L = 5 V V D = 14 V ID(on) ID(off) –150 –15 –10 –5 0 5 10 15 –30 –60 –90 –120 V L = 5 V , TA = 25/C0095C For ID(off), VS = 0 V For IS(off), VD = 0 V ID(on) ID(off), IS(off) V D or VS – Drain or Source V oltage (V) V+, V– Positive and Negative Supplies (V) Switching Time vs. Temperature*Supply Current vs. Temperature Switching Time vs. Positive Supply Voltage*Switching Time vs. Power Supply Voltage* I+, I–, IL (A) –55 –35 –15 5 25 45 65 85 105 125 1 p 100 p 10.0 p 1 n 10 n 100 n IL IL tON (ns), tOFF tON (ns), tOFF tON (ns), tOFF 240 180 120 –55 –35 –15 5 25 45 65 85 105 125 V+ = 15 V , V– = –15 V , VL = 5 V tON tOFF V S = –10 V V S = 10 V 210 150 *Refer to Figure 2 for test conditions. V S = 10 V V S = –10 V 200 180 140 160 120 100 tON tOFF VL = 5 V V S = 5 V V S = –5 V V S = 5 V V S = –5 V 300 270 210 02 5 240 180 150 120 2015105 tON tOFF V L = 5 V V S = 5 V 0 V 0 V 0 V –15 V –15 V –5 V –5 V TA – Temperature (/C0095C) V+ – Positive Supply (V) TA – Temperature (/C0095C) –15 V

Figure 2. Switching Time Figure 3. Break-Before-Make

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Figure 4. Charge Injection Figure 5. Off Isolation Figure 6. Insertion Loss Figure 7. Crosstalk Figure 8. Capacitances

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S-53748—Rev. E, 05-Jun-97 Applications (Cont’d) Peak Detector: A 3 acting as a comparator provides the logic drive for operating SW1. The output of A2 is fed back to A3 and compared to the analog input ein. If ein > eout the output of A 3 is high keeping SW1 closed. This allows C1 to charge up to the analog input voltage. When ein goes below eout A3 goes negative, turning SW1 off. The system will therefore store the most positive analog input experienced. A 2 – eout A 3 A 1ein Reset SW 1 SW 2 DG401 R 1 C 1 Figure 12.Positive Peak Detector