KTB8331 KINETIC | Alldatasheet

Document overview

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Technical content

Features

  • 2.7 to 5.5V Input Voltage Range
  • 0.6 to 3.345V Programmable Output Voltage  6.25mV steps below 1.39375V  15mV steps above 1.44V
  • 3.0A Output Current
  • ±1% Accuracy at TA = +25°C  ±2.5% over line/load/temp/setting
  • Fast Transient Response
  • Dynamic Voltage Scaling (DVS) with 8 ramp rates
  • Soft-Start with 10 ramp rates
  • 89% Peak Efficiency at Vout = 1.15625V
  • 2.4MHz with Auto-Skip at light loads  Programmable forced-PWM mode
  • 48uA typ. No-Load Supply Current in Skip Mode
  • Tiny External Components  L = 330 or 470nH (2012 or 2016 metric size)  Cin = 10µF (0402), Cout = 2x22µF (2x0402)
  • Over-Current, Short-Circuit, Under/Over-VIN, and Thermal Shutdown Protections
  • 1MHz I2C Interface
  • -40°C to 85°C Operating Temperature Range
  • 15-bump Pb-free WLCSP (0.4mm pitch)  1.340 x 2.045mm (0.6mm height)  Pin/Register Compatible with FAN53526 Brief Description The KTB8331 is a precision adaptive-on-time (AOT) buck switching regulator with class-leading accuracy, transient response, efficiency, and solution size optimized for mobile and non-mobile application. It is I2C programmable for output voltages in the 0.6V to 3.345V range. It features soft-start and DVS with multiple programmable ramp rates. Versions with various default settings can be ordered. The features and performance make the KTB8331 suitable for a variety of applications including CPU/GPU core, DSP and baseband, DDR memory, VIO, and sensor/analog power. The KTB8331 is available in RoHS and Green compliant 15-bump 1.340mm x 2.045mm x 0.6mm wafer-level chip-scale package (WLCSP).

Applications

  • CPU, GPU, AP, DSP, FPGA, I/O, XCVR Power
  • HDD, LPDDR3, LPDDR4 Memory Power
  • Tablets, Netbooks, Ultra-Books
  • Smartphones, Mobile Internet Devices, IoT
  • DSC, Drones, Gaming Consoles, Accessories Typical Application Schematic KTB8331 3A, 2.4MHz AOT Buck VIN PGND10µF VOUT LX 2x 22µF INPUT 2.7 to 5.5V OUTPUT 0.6 to 3.345V 330nH or 470nH AGND I2C Interface DVS Logic EN VSEL SCL SDA IRQ

December 2021 – Revision 04b Page 2 of 25 Kinetic Confidential Pin Descriptions Pin # Name Function A1, B1, C1 VIN Voltage Input for buck regulator and IC power A3, B3 PGND Power Ground for buck regulator C3, E1 AGND Analog Ground for IC power A2, B2 LX Inductor Connection for buck regulator E3 VOUT Output Voltage sense input D2 EN Chip Enable logic input E2 SCL I2C Clock digital input D3 SDA I2C Data digital I/O C2 IRQ̅̅̅̅̅̅ Interrupt Request open-drain output. If not used, tie to AGND or PGND. D1 VSEL DVS Voltage Select and Auto-Skip vs. Forced-PWM Mode Select logic input Pinout Diagram WLCSP-15 VIN VIN IRQ EN SCL AGND SDA VOUT PGND LX PGND VSEL WW XXYY ZZZZ A B C D E 1 2 3 TOP VIEW TOP VIEW LX VIN AGND 15-Bump 1.340mm x 2.045mm x 0.62mm Top Mark WW = Device Code, XX = Date Code, YY = Assembly Code, ZZZZ = Serial Number

December 2021 – Revision 04b Page 3 of 25 Kinetic Confidential Absolute Maximum Ratings1 (TA = 25C unless otherwise noted) Symbol Description Value Units VIN VIN to AGND -0.3 to 6 V VPGND PGND to AGND -0.3 to 0.3 V VLX2 LX to PGND -0.3 to (VIN+0.3) V VOUT VOUT to AGND -0.3 to (VIN+0.3) V VIO SCL, SDA, VSEL to AGND -0.3 to 6 V EN, IRQ̅̅̅̅̅̅ to AGND -0.3 to VIN V ILX LX Continuous Current 3.2 ARMS LX Peak Current (1ms maximum) 9.6 APEAK TJ Operating Junction Temperature Range -40 to 150 C TS Storage Temperature Range -55 to 150 C TLEAD Maximum Soldering Temperature (at leads, 10 sec) 260 C ESD Ratings3 Symbol Description Value Units VESD_HBM JEDEC JS-001-2017 ESD Human Body Model (all pins) ±2 kV Thermal Capabilities4 Symbol Description Value Units ΘJA Thermal Resistance – Junction to Ambient 77 C/W PD Maximum Power Dissipation at TA = 25°C 1.62 W ΔPD/ΔT Derating Factor Above TA = 25°C -13 mW/°C 1. Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any one time. 2. Absolute Maximum Rating for VLX is a DC voltage rating. During normal switching operation, short -duration voltage spikes beyond the DC rating are expected and normal for all DC-DC switching regulators. 3. ESD Ratings conform to JEDEC industry standards. Some pins may actually have higher performance. 4. Junction to Ambient thermal resistance is highly dependent on PCB layout. Values are based on thermal properties of the devi ce when soldered to an EV board.

December 2021 – Revision 04b Page 4 of 25 Kinetic Confidential

Ordering Information

Default Output Voltage & Mode7 7-bit I2C Slave Address Package (VSEL = 1) (VSEL = 0) KTB8331AEDAA-TR QKXXYYZZZZ 1.15625V Forced-PWM 1.15625V Auto-Skip 1100 000=0x60h WLCSP15 KTB8331BEDAA-TR QLXXYYZZZZ 3.300V Forced-PWM 3.150V Auto-Skip 1100 000=0x60h WLCSP15 KTB8331CEDAA-TR QMXXYYZZZZ 1.000V Forced-PWM 0.900V Auto-Skip 1100 000=0x60h WLCSP15 KTB8331DEDAA-TR QNXXYYZZZZ 0.600V Forced-PWM 0.600V Auto-Skip 1010 000=0x50h WLCSP15 KTB8331EEDAA-TR QOXXYYZZZZ 1.125V Forced-PWM 1.125V Auto-Skip 1010 111=0x57h WLCSP15 KTB8331FEDAA-TR QUXXYYZZZZ 0.950V Forced-PWM 0.950V Auto-Skip 1010 000=0x50h WLCSP15 KTB8331GEDAA-TR QVXXYYZZZZ 1.800V Forced-PWM 1.800V Auto-Skip 1010 000=0x50h WLCSP15 KTB8331HEDAA-TR QWXXYYZZZZ 3.300V Forced-PWM 3.300V Auto-Skip 1010 000=0x50h WLCSP15 KTB8331JEDAA-TR RAXXYYZZZZ 0.750V Forced-PWM 0.750V Auto-Skip 1010 001=0x51h WLCSP15 KTB8331KEDAA-TR RBXXYYZZZZ 1.200V Forced-PWM 1.200V Auto-Skip 1100 000=0x60h WLCSP15 KTB8331LEDAA-TR RCXXYYZZZZ 1.05V Forced-PWM 1.05V Auto-Skip 1100 000=0x60h WLCSP15 KTB8331MEDAA-TR RJXXYYZZZZ 1.081V Auto-Skip 1.125V Auto-Skip 1100 000=0x60h WLCSP15 5. For part numbers in Italic, please contact your local sales representative for availability. 6. “WW” is the device ID, “XX” is the date code, “YY” is the assembly code, and “ZZZZ” is the serial number. 7. For part numbers in Italic, please contact your local sales representative for availability.

December 2021 – Revision 04b Page 5 of 25 Kinetic Confidential Electrical Characteristics8 Unless otherwise noted, the Min and Max specs are applied over the full operation temperature range of Supply Specifications Symbol Description Conditions Min Typ Max Units VIN Input Supply Operating Range 2.7 5.5 V VUVLO Under-Voltage Lockout Threshold VIN rising VIN hysteresis 2.4 2.55 200 2.7 V mV VOVP Over-Voltage Protection Threshold VIN rising 5.5 5.75 5.9 V VIN hysteresis 200 mV IIN No-Load Supply Current EN = 1, VIN = 3.6V, VOUT 2.5V, Skip 48 80 µA EN = 1, VIN = 3.6V, Forced-PWM 16 mA ISHDN Shutdown Supply Current EN = 0, TA = 25C 0.2 1 µA EN = 1, ENn[0]=0, TA = 25C 0.2 1.5 µA Logic Pin Specifications (EN, VSEL, IRQ̅̅̅̅̅̅) Symbol Description Conditions Min Typ Max Units VIH Input Logic High (EN, VSEL) 1.15 V VIL Input Logic Low (EN, VSEL) 0.4 V II_LK Input Logic Leakage (EN, VSEL) TA = 25C, VI = 0V or VIN -1 ±0.01 1 µA RI_PD Input Logic Pull-Down (EN, VSEL) only connected when VI ≤ VIL (disconnected when VI ≥ VIH) 250 kΩ VOL Output Logic Low (IRQ̅̅̅̅̅̅) IO_SINK = 1mA 0.18 0.4 V IO_LK Output Logic Leakage (IRQ̅̅̅̅̅̅) TA = 25C, VO = high-Z or VIN 0.01 1 µA Thermal Shutdown Specifications Symbol Description Conditions Min Typ Max Units TJ_SHDN IC Junction Thermal Shutdown9 TJ rising 140 °C Hysteresis 20 °C (continued next page) 8. Device is guaranteed to meet performance specifications over the -40C to +85C operating temperature range by design, characterization and correlation with statistical process controls. 9. Guaranteed by design, characterization and statistical process control methods; not production tested.

Figure 1. I2C Compatible Interface Timing

December 2021 – Revision 04b Page 7 of 25 Kinetic Confidential Electrical Characteristics (continued)8 Unless otherwise noted, the Min and Max specs are applied over the full operation temperature range of Buck Regulator Specifications Symbol Description Conditions Min Typ Max Units VOUT Output Voltage Setting Range Low Range (G=1), RANGE[0]=0 0.600 1.39375 V High Range (G=2.4), RANGE[0]=1 1.440 3.345 V VOUT_STEP Output Voltage Setting Step Size Low Range (G=1), RANGE[0]=0 6.25 mV High Range (G=2.4), RANGE[0]=1 15 mV VOUT_ACC Output Voltage DC Accuracy TA = 25C, VOUT = 1.15625V, FPWM -1 ±0.2 1 % FPWM over line/load/temp/setting -2.5 ±1 2.5 % Auto-Skip over line/setting ±1 % VOUT_LOAD Output Voltage Load Regulation9 ILOAD = 1A to 3A, FPWM -0.01 %/A VOUT_LINE Output Voltage Line Regulation9 VIN = 2.7V to 5.5V, ILOAD = 1.5A ±0.01 %/V VOUT_TRAN Output Voltage Transient Response9 ILOAD = 10mA1.5A, tr = tf = 200ns, VOUT = 1.15625V ±50 mV IOUT_MAX Maximum Output Current 3 A ILX_PEAK LX Peak Current Limit 4 4.6 5.5 A ILX_VALLEY LX Valley Current Limit 3 4.3 5.5 A ILX_LEAK LX Leakage Current VLX = 0V or 5.5V, TA = 25C 0.1 1 µA RDSON_MS Main Switch On-Resistance MOSFET + metal + bumps 50 mΩ RDSON_SR Synch. Rectifier On-Resistance MOSFET + metal + bumps 30 mΩ RLX_DIS LX Active Discharge Resistance EN = 0 or ENn[0] = 0, DIS[0] = 1 133 Ω tSS_DELAY Soft-Start Ramp Delay9 Hardware enable, EN=0→1 350 µs Software enable, ENn[0] = 0→1 315 µs dV/dtSS Soft-Start Ramp Rates 10 programmable rates 1.5625 30 mV/µs tDVS_DELAY DVS Ramp Delay9 Hardware DVS, VSEL = 01 3 µs Software DVS, by I2C command <10 µs dV/dtDVS DVS Ramp Rates 8 programmable rates 3.125 25 mV/µs VOUT_POK VOUT Power OK Threshold Percentage of VOUT setting, falling 88 % Percentage of VOUT setting, rising 92 %

December 2021 – Revision 04b Page 8 of 25 Kinetic Confidential Typical Characteristics Unless otherwise noted, VIN = VEN = 3.6V, L = 330nH, CIN = 10µF, COUT = 2x 22µF, and TA = 25°C. Efficiency vs. Load at VOUT = 1.15625V VOUT Accuracy vs. VOUT Setting (IOUT = 10mA) VOUT Accuracy vs. Load (VOUT = 1.15625V) Supply Current vs. VIN (VOUT = 1.15625V, No Load, Mode = Auto) Shutdown Supply Current vs. VIN VLX and ILX Switching Waveforms (VOUT = 1.15625V, Mode = Auto) 60% 65% 70% 75% 80% 85% 90% 95% 100% 0.001 0.01 0.1 1 10 Efficiency (%) Output Load (A) VIN = 3V VIN = 3.6V VIN = 4.2V Skip Mode Forced PWM Inductor = DFE201612E-R33M 3.0V -10 Error (mV) VOUT Setting (V) Auto Skip Forced PWM Gain = 1 Gain = 2.4 -10 Error (mV) Output Current (A) VIN = 3V VIN = 3.6V VIN = 4.2V PWM FPWM Skip Mode 3.0V No Load Supply Current (µA) Input Voltage (V) 85°C 25°C -40°C 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Shutdown Current (µA) Input Voltage (V) Hardware Shutdown Software Shutdown 400ns / div 1.5AOUT 100mAOUT VLX: 2V / div ILX: 1A / div

December 2021 – Revision 04b Page 9 of 25 Kinetic Confidential Typical Characteristics (continued) Unless otherwise noted, VIN = VEN = 3.6V, L = 330nH, CIN = 10µF, COUT = 2x 22µF, and TA = 25°C. VOUT Ripple Waveforms (VOUT = 1.15625V, Mode = Auto) Short-Circuit Protection Load Transient Response (VOUT = 1.15625V, Load = 10mA-1.5A, Mode = FPWM) Load Transient Response (VOUT = 1.15625V, Load = 1.5A-3A, Mode = Auto) Line Transient Response (VOUT = 1.15625V, Mode = Auto) Line Transient Response (VOUT = 1.15625V, Mode = FPWM) 20µs / div 20mV / div 0mAOUT 5mAOUT 20mAOUT 100mAOUT 500mAOUT 20µs / div VOUT 500mA / div ILX 2A / div RSHORT = 70mΩ 40µs / div IOUT 1A / div VOUT (AC) 20mV / div 40µs / div VOUT (AC) 50mV / div IOUT 1A / div 20µs / div VIN 1V / div IOUT 10mA / div VOUT (AC) 20mV / div 20µs / div VIN 1V / div IOUT 1A / div VOUT (AC) 20mV / div

December 2021 – Revision 04b Page 10 of 25 Kinetic Confidential Typical Characteristics (continued) Unless otherwise noted, VIN = VEN = 3.6V, L = 330nH, CIN = 10µF, COUT = 2x 22µF, and TA = 25°C. Buck Enable Soft-Start Rates (VOUT = 1.15625V) DVS Positive Ramp-Up Rates (VOUT = 0.9-1.2V) DVS Negative Ramp-Down Rates (VOUT = 1.2-0.9V) Buck Shutdown (VOUT = 1.15625V, Active Discharge Enabled) Buck Shutdown (VOUT = 1.15625V, Active Discharge Disabled) 100µs / div 200mV / div 20µs / div 200mV / div 20µs / div 200mV / div 10ms / div EN 2V / div VOUT 500mV / div 10s / div EN 2V / div VOUT 500mV / div

December 2021 – Revision 04b Page 11 of 25 Kinetic Confidential Functional Description The KTB8331 is a highly efficient, high-performance, small buck regulator that operates from an input voltage of 2.7V to 5.5V and can output up to 3A. It integrates the main switch, synchronous rectifier switch, PWM control circuitry, VOUT setting DAC, various protection features, and an I2C serial interface to configure the output voltage, dynamic voltage scaling (DVS), control modes, and interrupts. Control Scheme The KTB8331 uses a proprietary adaptive on-time (AOT) PWM control scheme to maintain a nearly constant switching frequency as input voltage and output voltage vary. Compared to typical current-mode PWM schemes, the AOT control scheme provides quick response to line and load transients with excellent stability and wide bandwidth, thereby minimizing output voltage droop and soar for dynamic loads, even with minimal output capacitance. The adaptive on-time approximates fixed-frequency switching without using a fixed clock oscillator, which eliminates the need to wait for the next clock before responding to a load transient. The KTB8331 feedback loop also adds a proprietary, internally-compensated, integrating error amplifier to remove the output voltage offset normally associated with other AOT, constant on-time (COT), and hysteretic architectures. Shutdown Mode When the EN pin is low, the KTB8331 buck is in shutdown mode and draws very little current. In shutdown, the I2C is still active, allowing read and write commands, as long as VIN is above VUVLO. Similarly, register contents are retained during shutdown (and even when VIN is a little below VUVLO), as long as VIN is above VPOR=1.8V. Hardware Enable The KTB8331 buck regulator is turned on and off via hardware enable using the EN pin or via software enable using I2C commands. The default register settings allow simple hardware control. For hardware enable, drive the EN pin high. For hardware disable, drive the EN pin low. Software Enable For software enable/disable control, first write 0 into the EN0 bit (B7) of the VSEL0 configuration register (0x00), and/or write 0 into the EN1 bit (B7) of the VSEL1 configuration register (0x01). The VSEL pin determine s which register is used. Then bring the EN pin high. After that, write 1 into the corresponding EN0 or EN1 bit to enable the buck, and write 0 to disable the buck. Soft-Start The KTB8331 buck contains soft-start circuitry to ramp up VOUT slowly in order to reduce inrush current at VIN and prevent the inductor current from reaching the peak current limit (ILX_PEAK) during startup. The soft-start ramp rates are I2C programmable using the SLEW[2:0] bits (B6:4) in the CONTROL configuration register (0x02). The default register setting provides the slowest ramp rate to accommodate cold startup with certain processor cores. Once the processor is warm, faster ramps may be used. The slower rates are also better for applications with large amounts of total output capacitance. The inductor’s average current during soft-start is given by: 𝐼𝐿_𝑆𝑆 = 𝐶𝑂𝑈𝑇 × (𝑑𝑉 𝑑𝑡𝑆𝑆) + 𝐼𝐿𝑂𝐴𝐷_𝑆𝑆⁄ where dV/dtSS is the soft-start ramp rate and ILOAD_SS is the load current during soft-start. Choose a ramp rate that keeps the inductor current average below 3A, or even lower. As an example, if ILOAD_SS = 0, the fastest ramp rate of dV/dtSS = 30mV/µs is still slow enough for IL_SS ≤ 3A with COUT ≤ 100µF. But if ILOAD_SS = 1.5A and COUT = 300µF, choose a dV/dtSS < 5mV/µs. Setting the Output Voltage The KTB8331 has two independent output voltage ranges. The low range is VOUT = 0.6V to 1.39375V in 6.25mV steps. The high range is VOUT = 1.44V to 3.345V in 15mV steps. The range is I2C programmable using the RANGE bit (B3) in the CONTROL configuration register (0x02). The default range setting is factory trimmed to match the default output voltage setting – see the Ordering Information section.

December 2021 – Revision 04b Page 12 of 25 Kinetic Confidential After the correct range is selected, the KTB8331 register map contains two voltage setting registers to facilitate hardware control of DVS using the VSEL pin. The first output voltage setting is I2C programmable using the VOUT_VSEL0[6:0] bits (B6:0) in the VSEL0 configuration register (0x00). The second output voltage setting is I2C programmable using the VOUT_VSEL1[6:0] bits (B6:0) in the VSEL1 configuration register (0x01). The output voltage setting is given by: 𝑉𝑂𝑈𝑇 = 𝐺 × (600𝑚𝑉 + 6.25𝑚𝑉 × 𝑉𝑂𝑈𝑇_𝑉𝑆𝐸𝐿𝑛) where G = 1.0 when the RANGE bit is 0, and G = 2.4 when the RANGE bit is 1. VOUT_VSELn is the decimal equivalent of the binary bits of VOUT_VSEL0[6:0] or VOUT_VSEL1[6:0]. The default voltage settings are factory trimmed, and several versions are available – see the Ordering Information section. Dynamic Voltage Scaling (DVS) Dynamic Voltage Scaling (DVS) is used to slew the output voltage between two voltage settings contained in the VSEL0 and VSEL1 registers – see Setting the Output Voltage section. The VSEL pin selects which register is used. Or, as an alternative method, I2C commands can be used by simply connecting the VSEL pin to ground and dynamically writing a new setting into the VSEL0 register. In either method, all DVS output voltage transitions are slew-rate-controlled by an on-chip up/down counter and DAC. The DVS slew rate is I2C programmable using the SLEW[2:0] bits (B6:4) in the CONTROL configuration register (0x02). DVS slewing is only possible within a single output voltage range; slewing between a vol tage in the low range and a voltage in the high range is not possible. Forced-PWM vs. Auto-Skip Modes The KTB8331 has two ways to control light-load switching behavior – Forced-PWM mode and Auto-Skip mode. In Forced-PWM, the switching frequency remains nearly constant. This mode is helpful for applications that are noise sensitive. In Auto-Skip mode, the KTB8331 transitions automatically between PWM switching at heavy loads and Skip/PFM switching at light loads. Auto-Skip mode is helpful for applications that need high efficiency at light loads. While skipping, single pulses are evenly spaced, resulting in the lowest output ripple and noise when compared to competing “pulse-grouping” or “burst mode” devices. Furthermore, the PFM frequency during single-pulse skipping remains above the audio frequency band (20Hz to 20kHz) down to very light loads – see the Typical Operating Characteristics section. The switching mode is I2C programmable using the MODE[1:0] bits (B1:0) in the CONTROL configuration register (0x02). The MODE[1:0] bits work together with the VSEL pin to independently set the switching mode for the VOUT_VSEL0[6:0] and VOUT_VSEL1[6:0] output voltage settings. The default mode settings are factory trimmed, and several versions are available – see the Ordering Information section. Active Discharge When the KTB8331 buck is disabled, an active discharge feature connects an on-chip resistor (RLX_DIS) between the LX and PGND pins. This resistor discharges the output capacitor through the inductor. By default, this feature is enabled; however, it can be disabled for applications that require a high impedance at the output during shutdown. Enable and disable the active discharge feature via I2C commands by writing the DIS bit (B7) in the CONTROL configuration register (0x02). POR and Software Register Reset The KTB8331 does NOT contain non-volatile memory for the register settings. When VIN rises above VPOR=1.8V, either at initial power up or after a temporary VIN droop below VPOR, a Power-On Reset (POR) circuit resets all registers to their factory default settings. Thereafter, as long as VIN remains above VPOR, the I2C registers contents are retained, regardless if the buck is enabled or disabled. However, to reliably read or write to the I2C registers, VIN should be above VUVLO. To reset the registers manually via software, use I2C to write a 1 to the RESET bit (B2) in the CONTROL configuration register (0x02). This resets nearly all registers to their default settings. There are a few exceptions, as makes logical sense; refer to the CONTROL register description.

December 2021 – Revision 04b Page 13 of 25 Kinetic Confidential Internal Status Monitor The KTB8331 contains a MONITOR status register (0x05), which can be read to check the present status of the IC. The register has individual bits for the status of VOUT power-OK, VIN under-voltage lockout, VIN over-voltage protection, VOUT positive slew, VOUT negative slew, software reset event latch, over-temperature thermal shutdown, and buck enable. Refer to the MONITOR register description for more details. Interrupt Register and IRQ\\ Flag The KTB8331 contains an interrupt mask register, an interrupt latch register, and an interrupt request flag pin (IRQ\\) to inform a host processor that one or more status changes have occurred. The INTMASK mask register (0x06) and the INTLATCH interrupt register (0x07) both partially mirror the MONITOR status register bits. However, the enable (nEN_INT) interrupt has logic inversion (in comparison to the MONITOR status register) to indicate that the buck was disabled. Only unmasked events are latched into the INTLATCH register. By default, all interrupts are masked and need to be unmasked before they can be latched. The IRQ\\ pin pulls active low while any bit in the INTLATCH register is a 1. Reading the INTLATCH register resets and clears the register, thereby releasing the IRQ \\ pin. However, if an unmasked event is still on-going, it will not clear, and the IRQ\\ pin will remain low. This IRQ\\ flag remain active during UVLO events as long as VIN is above VPOR=1.8V. However, the IRQ\\ flag is always cleared if VIN falls below VPOR due to power-on reset (POR) of all registers. Input Under-Voltage Lockout (UVLO) When the input voltage (VIN) is below the under-voltage lockout threshold (VUVLO), the buck is disabled. The I2C registers and all logic pins remain functional during UVLO, so long as VIN remains above VPOR=1.8V. Exiting UVLO does not reset any registers. When VIN rises above VUVLO, either at initial power up or after a temporary VIN droop below VUVLO, and if the buck is enabled, the programmed soft-start ramp begins. The UVLO status is reflected in the MONITOR register. UVLO events do not reset the registers to their defaults. VIN must fall below VPOR to reset the registers. Input Over-Voltage Protection (OVP) When the input voltage (VIN) is above the over-voltage protection threshold (VOVP), the buck is disabled. The I2C registers and all logic pins remain functional during OVP. When VIN returns below VOVP, and if the buck is enabled, the programmed soft-start ramp begins. Just like UVLO, the OVP status is reflected in the MONITOR register. Inductor Over-Current Protection (OCP) Inductor peak current limit (ILX_PEAK) and valley current limit (ILX_VALLEY) protect the buck and inductor during over- current faults. The current limits control the buck’s switching on a cycle-by-cycle basis and have a higher priority than the voltage regulation threshold. During sustained over-current faults, the output voltage typically droops below the regulation threshold. The POK_STAT bit (B7) in the MONITOR register (0x05) indicates when VOUT is okay (above the VOUT_POK threshold). Output Short-Circuit Protection (SCP) and Hiccup Mode During a short-circuit event at the buck’s output, the inductor experiences a very low discharge voltage during the switching cycle’s off-time (tOFF, when the synchronous rectifier switch is on). In this case, the inductor current ramps down very slowly. In order to prevent inductor current runaway, the valley current limit (ILX_VALLEY) extends tOFF, keeping the inductor current well controlled. If an over-current fault or short-circuit event persists for more than 250µs, the buck enters hiccup mode and pause all switching. After about 5ms, the buck attempts to soft-start. If the fault persists, the buck once again enters hiccup mode and periodically re-attempts soft-start until the fault is removed. The low duty-factor during hiccup mode prevents the IC from getting hot.

December 2021 – Revision 04b Page 14 of 25 Kinetic Confidential Thermal Shutdown Over-Temperature (OT) Over-temperature (OT) protection occurs if the die junction temperature exceeds the thermal shutdown threshold (TJ_SHDN). During thermal shutdown, the buck pauses all switching until the die temperature cools. Once cooled, the buck re-starts with the programmed soft-start ramp. The OT status is reflected in the MONITOR register and, if unmasked, latched into the INTLATCH register. Trim Options The KTB8331 is factory trimmed using one-time programmable (OTP) registers. Standard versions are available for various default output voltage settings and modes – see the Ordering Information section. Contact a Kinetic Technologies representative regarding versions with other default settings or I2C slave addresses. I2C Interface Description I2C Serial Data Bus The KTB8331 supports the I2C bus protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the bus is called a master, whereas the devices controlled by the master are known as slaves. A master device must generate the serial clock (SCL), control bus access and generate START and STOP conditions to control the bus. The KTB8331 operates as a slave on the I2C bus. Within the bus specifications, a standard mode (100kHz maximum clock rate) and a fast mode (400kHz maximum clock rate) are defined. The KTB8331 works in both modes. Connections to the bus are made through the open-drain I/O lines SDA and SCL. The following bus protocol has been defined in Figure 2:

  • Data transfer may be initiated only when the bus is not busy.
  • During data transfer, the data line must remain stable whenever the clock line is HIGH. Ch anges in the data line while the clock line is high are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus Not Busy Both data and clock lines remain HIGH. Start Data Transfer A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data Valid The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Setup and hold times must also be taken into account.

the register address first to define which register data to read. Figure 4 shows the steps of the I2C read cycle. Figure 4. I2C Read Cycle

  • Master generates start condition.
  • Master sends 7-bit slave address and 1-bit data direction ‘0’ for write.
  • Slave sends acknowledge if the slave address is matched.
  • Master sends 8-bit register address.
  • Slave sends acknowledge.
  • Master generates repeated start condition.
  • Master sends 7-bit slave address and 1-bit data direction ‘1’ for read.
  • Slave sends acknowledge if the slave address is matched.
  • Slave sends the data byte of that addressed register.
  • If master sends acknowledge, the register address will be incremented by one after each acknowledge and the slave will continue to send the data for the updated addressed register.
  • If master sends no acknowledge, the slave will stop sending the data.
  • Master generate stop condition to finish the read cycle. Rs Device Address 1 A P ‘1’ Read 7 bits 8 bits S Device Address Register Address0 A A ‘0’ Write 7 bits 8 bits Data A* From Slave to Master From Master to Slave S = Start Rs = Repeated Start A = Acknowledge (SDA Low) A* = No Acknowledge (SDA High) P = Stop

December 2021 – Revision 04b Page 17 of 25 Kinetic Confidential I2C Registers I2C Slave Address Options10 7-Bit Address Write Address Read Address Bits 7 6 5 4 3 2 1 0 KTB8331A/B/C/K/L/M 0x60 0xC0 0xC1 1 1 0 0 0 0 0 R/𝑊̅ KTB8331D/F/G/H 0x50 0xA0 0xA1 1 0 1 0 0 0 0 R/𝑊̅ KTB8331E 0x57 0xAE 0xAF 1 0 1 0 1 1 1 R/𝑊̅ KTB8331J 0x51 0xA2 0xA3 1 0 1 0 0 0 1 R/𝑊̅ I2C Register Map Hex Address Name Type Access Default Reset B7 B6 B5 B4 B3 B2 B1 B0 0x00 VSEL0 Config R/W 1xxx xxxx EN0 VOUT_VSEL0[6:0] 0x01 VSEL1 Config R/W 1xxx xxxx EN1 VOUT_VSEL1[6:0] 0x02 CONTROL Config R/W 1000 x0xx DIS SLEW[2:0] RANGE RESET MODE[1:0] 0x03 ID1 Data R 1010 0010 VENDOR[2:0] DIE_ID[4:0] 0x04 ID2 Status R 0000 xxxx RSVD RSVD RSVD RSVD DIE_REV[3:0] 0x05 MONITOR Status R 0000 0000 POK _STAT UVLO _STAT OVP _STAT POS _STAT NEG _STAT RESET _STAT OT _STAT EN _STAT 0x06 INTMASK Mask R/W 1111 1111 RSVD RSVD RSVD POS _INTM NEG _INTM RESET _INTM OT _INTM nEN _INTM 0x07 INTLATCH Intrrpt R/C 0000 0000 RSVD RSVD RSVD POS _INT NEG _INT RESET _INT OT _INT nEN _INT Register contents are reset in hardware to their default values by VIN power-on reset. Additionally, most registers can be reset in software by writing 1 to the RESET bit (B2) in the CONTROL register (0x02). Default Reset bits marked with lower-case “x” in the register map and register details tables depend upon the ordered part# suffix and die revision; please see the Ordering Information section. Upper-case “X” used elsewhere in the tables designates “don’t care”. VSEL0 Configuration Register Register Address 0x00 Bit Name Access Default Reset Description

7 EN0 R/W 1

Software Buck Enable. When EN pin is low, the regulator is off. When EN pin is high and VSEL pin is low, the EN0 bit takes precedent. EN pin VSEL pin EN0 bit Regulator

0 X X off

6:0 VOUT_VSEL0[6:0] R/W xxx xxxx Sets the nominal VOUT regulation voltage when VSEL pin is low. When RANGE bit is low, the VOUT range is from 0.600 to 1.39375V. When RANGE bit is high, the VOUT range is from 1.440 to 3.345V. 𝑉𝑂𝑈𝑇 = 𝐺 × (600𝑚𝑉 + 6.25𝑚𝑉 × 𝑉𝑂𝑈𝑇_𝑉𝑆𝐸𝐿0) where G = 1.0 when RANGE bit is low, and G = 2.4 when RANGE bit is high. 10 For Alternate 1/2/3 Slave Addresses, please contact a Kinetic Technologies representative.

December 2021 – Revision 04b Page 18 of 25 Kinetic Confidential VSEL1 Configuration Register Register Address 0x01 Bit Name Access Default Reset Description

7 EN1 R/W 1

Software Buck Enable. When EN pin is low, the regulator is off. When EN pin is high and VSEL pin is high, the EN1 bit takes precedent. EN pin VSEL pin EN1 bit Regulator 6:0 VOUT_VSEL1[6:0] R/W xxx xxxx Sets the nominal VOUT regulation voltage when VSEL pin is high. When RANGE bit is low, the VOUT range is from 0.600 to 1.39375V. When RANGE bit is high, the VOUT range is from 1.440 to 3.345V. 𝑉𝑂𝑈𝑇 = 𝐺 × (600𝑚𝑉 + 6.25𝑚𝑉 × 𝑉𝑂𝑈𝑇_𝑉𝑆𝐸𝐿1) where G = 1.0 when RANGE bit is low, and G = 2.4 when RANGE bit is high. CONTROL Configuration Register Register Address 0x02 Bit Name Access Default Reset Description

7 DIS R/W 1

Active Discharge of LX when regulator is disabled. Discharging LX will discharge COUT through the inductor. 0 = VOUT is high impedance when disabled. 1 = VOUT is discharged through an internal pull-down resistor when disabled. 6:4 SLEW[2:0] R/W 000 Slew Rate Control for soft-start and DVS ramp-up/down rates. Works in conjunction with the RANGE bit. RANGE bit SLEW bits Soft-Start DVS fSTEP 0 000 1.5625mV/µs 3.125mV/µs 500kHz 0 001 3.125mV/µs 3.125mV/µs 500kHz 0 010 3.125mV/µs 6.25mV/µs 1MHz 0 011 6.25mV/µs 6.25mV/µs 1MHz 0 100 6.25mV/µs 12.5mV/µs 2MHz 0 101 12.5mV/µs 12.5mV/µs 2MHz 0 110 12.5mV/µs 25mV/µs 4MHz 0 111 25mV/µs 25mV/µs 4MHz 1 000 1.875mV/µs 3.75mV/µs 250kHz 1 001 3.75mV/µs 3.75mV/µs 250kHz 1 010 3.75mV/µs 7.5mV/µs 500kHz 1 011 7.5mV/µs 7.5mV/µs 500kHz 1 100 7.5mV/µs 15mV/µs 1MHz 1 101 15mV/µs 15mV/µs 1MHz 1 110 15mV/µs 25mV/µs 2MHz 1 111 30mV/µs 25mV/µs 2MHz

December 2021 – Revision 04b Page 19 of 25 Kinetic Confidential Bit Name Access Default Reset Description

3 RANGE R/W x

Sets the VOUT range. Also influences the DVS ramp-up/down slew rate (see SLEW[2:0] above). RANGE bit G VOUT(min) VOUT(max) VOUT(step) 0 1.0 0.600V 1.39375V 6.25mV 1 2.4 1.440V 3.345V 15mV 𝑉𝑂𝑈𝑇 = 𝐺 × (600𝑚𝑉 + 6.25𝑚𝑉 × 𝑉𝑂𝑈𝑇_𝑉𝑆𝐸𝐿𝑛) where G = 1.0 when RANGE bit is low, and G = 2.4 when RANGE bit is high. Note: There is no slew-rate control when toggling the RANGE bit; therefore, it is recommended to disable VOUT before changing the RANGE setting.

2 RESET R/W 0

Software Reset to default register settings. Writing 1 resets nearly all the registers. The RESET bit always reads back as 0. Before self-clearing, the software reset event is latched into the RESET_STAT bit (B2) in the MONITOR register (0x05) and also into the RESET_INT bit (B2) in the INTLATCH register (0x07) if unmasked. Items that are NOT reset by the RESET bit are: 1. RESET_STAT bit in the MONITOR register 2. RESET_INT bit in the INTLATCH register 1:0 MODE[1:0] R/W xx Auto-Skip vs. Forced-PWM mode control. Works in conjunction with the VSEL pin. Auto-Skip automatically uses PWM in continuous conduction at heavy loads and PFM pulse-skipping in discontinuous conduction at light loads. VSEL pin MODE bits Operating Mode

0 X0 Auto-Skip

0 X1 Forced-PWM

7:5 VENDOR[2:0] R 101 Vendor Identification 101 = Kinetic Technologies 4:0 DIE_ID[4:0] R 0 0010 Die Type Identification 0 0010 = KTB8331 ID2 Status Register Register Address 0x04 Bit Name Access Default Reset Description 7 RSVD R 0 Reserved. Always reads back as 0. 6 RSVD R 0 Reserved. Always reads back as 0. 5 RSVD R 0 Reserved. Always reads back as 0. 4 RSVD R 0 Reserved. Always reads back as 0. 3:0 DIE_REV[3:0] R xxxx Die Revision Identification

December 2021 – Revision 04b Page 20 of 25 Kinetic Confidential MONITOR Status Register Register Address 0x05 Bit Name Access Default Reset Description

7 POK_STAT R 0

0 = VOUT is below POK comparator threshold 1 = VOUT is above POK comparator threshold During normal operation, the POK_STAT bit is 1. During disabled, soft-start or overload conditions, the POK_STAT bit is 0.

6 UVLO_STAT R 0

0 = VIN is above the UVLO comparator threshold 1 = VIN is below the UVLO comparator threshold During normal operation or when disabled, the UVLO_STAT bit is 0. During low input voltage conditions, the buck is disabled by the UVLO comparator and the UVLO_STAT bit is set to 1 (so long as VIN remains above VPOR=1.8V).

5 OVP_STAT R 0

0 = VIN is below the OVP comparator threshold 1 = VIN is above the OVP comparator threshold During normal operation or when disabled, the OVP_STAT bit is 0. During high input voltage conditions, the buck is disabled by the OVP comparator and the OVP_STAT bit is set to 1.

4 POS_STAT R 0

0 = VOUT is at its set value 1 = VOUT is slewing in the positive direction towards it set value During normal operation, the POS_STAT bit is 0. During soft-start or positive DVS slew transitions, the POS_STAT bit is 1.

3 NEG_STAT R 0

0 = VOUT is at its set value 1 = VOUT is slewing in the negative direction towards it set value During normal operation, the NEG_STAT bit is 0. During negative DVS slew transitions, the NEG_STAT bit is 1.

2 RESET_STAT R/C 0

Software Reset Status Latch 0 = software reset was not performed since this bit was cleared 1 = software reset was performed since this bit was cleared The RESET_STAT bit is set to 1 when a software reset is written to the RESET bit (B2) in the CONTROL register. The RESET_STAT bit is NOT reset by the software reset. Instead, it is cleared (reset to 0) after the RESET_STAT bit is read or whenever chip power is removed (VIN<VPOR).

1 OT_STAT R 0

0 = the die is not in thermal shutdown 1 = the die is in thermal shutdown During normal operation, the OT_STAT bit is 0. During thermal shutdown, the OT_STAT bit is 1.

0 EN_STAT R 0

0 = the buck is disabled by hardware or software 1 = the buck is enabled by hardware or software During normal operation, the EN_STAT bit is 1. During hardware or software disabled conditions, the EN_STAT bit is 0.

December 2021 – Revision 04b Page 21 of 25 Kinetic Confidential INTMASK Mask Register Register Address 0x06 Bit Name Access Default Reset Description 7:5 RSVD R/W 111 RSVD

4 POS_INTM R/W 1

0 = the interrupt is not masked 1 = the interrupt is masked

3 NEG_INTM R/W 1

0 = the interrupt is not masked 1 = the interrupt is masked

2 RESET_INTM R/W 1

0 = the interrupt is not masked 1 = the interrupt is masked

1 OT_INTM R/W 1

0 = the interrupt is not masked 1 = the interrupt is masked 0 nEN_INTM R/W 1 nEN Interrupt Mask 0 = the interrupt is not masked 1 = the interrupt is masked INTLATCH Interrupt Register Register Address 0x07 Bit Name Access Default Reset Description 7:5 RSVD R/C 0 RSVD

4 POS_INT R/C 0

0 = VOUT has not slewed in positive direction due to DVS ramp-up or soft-start since cleared 1 = VOUT was slewed in positive direction due to DVS ramp-up or soft-start since cleared

3 NEG_INT R/C 0

0 = VOUT has not slewed in negative direction due to DVS ramp- down since cleared 1 = VOUT was slewed in negative direction due to DVS ramp-down since cleared

2 RESET_INT R/C 0

Software Reset Interrupt Latch 0 = software reset was not performed since this bit was cleared 1 = software reset was performed since this bit was cleared The RESET_INT bit is set to 1 when a software reset is written to the RESET bit (B2) in the CONTROL register. The RESET_STAT bit is NOT reset by the software reset. Instead, it is cleared (reset to 0) after the RESET_INT bit is read or whenever chip power is removed (VIN<VPOR).

1 OT_INT R/C 0

0 = the die has not entered thermal shutdown since cleared 1 = the die was in thermal shutdown since cleared 0 nEN_INT R/C 0 nEN (NOT Enabled = Disabled) Interrupt Latch 0 = the buck has not been disabled by hardware or software since cleared 1 = the buck was disabled by hardware or software since cleared

case-sizes are suitable. Table 1 is a list of recommended inductors from two leading suppliers. Table 1. Recommended Inductors characteristic of the capacitor. Table 2 is a list of recommended capacitors from two leading suppliers. Table 2. Recommended Capacitors through a connector or a cable, add additional bypass/bulk capacitance where VIN first arrives to the PCB.

effective capacitance compared to lower VOUT settings. transient arrival time with respect to the switching cycle of the regulator. load transient droop and soar. effective capacitance of 16µF. Figure 5. Typical DC bias derating characteristic for example 15µF ceramic capacitor. regulators operating at high duty-cycle.

Refer to Figure 6 for two example PCB layouts optimized for small footprint, low EMI, and good performanc e.

  1. Connect the input capacitor CIN as close as possible to the VIN and PGND pins using top-side thick metal
  2. Connect the ground terminals of output capacitors COUT as close as possible to the ground terminal of CIN

and the PGND pins using top-side metal.

  1. Connect the local top-side PGND island to the PCB ground plane using multiple parallel vias.
  2. Do not connect the AGND pins directly to the top-side PGND. Instead, connect the AGND pins to the

PCB ground plane using their own vias.

  1. Connect the inductor to the LX pins with a wide trace. For smallest CIN, the LX trace will not fit between

PCB layer 2 or layer 3 using multiple parallel vias. possible before and after the pinched area.

  1. Connect the VOUT terminals of the inductor to the output capacitors with a wide and short trace.
  2. Route the VOUT sense trace from COUT to the VOUT pin with care to keep it away from noisy traces,

especially the LX trace. Additionally, use ground fill to shield noise from coupling into the VOUT sense.

  1. Depending upon PCB design rules, it may be possible to place filled micro -vias directly under WLCSP

bumps. If not, route short traces to nearby vias. Figure 6. Two recommended PCB layouts

December 2021 – Revision 04b Page 25 of 25 Kinetic Confidential Packaging Information WLCSP35-15 (1.340mm x 2.045mm x 0.620mm) 0.400mm 0.400mm 15x 0.27mm Ø ±0.027mm 1.340mm ±0.050mm 2.045mm ±0.050mm 0.215mm ±0.022mm 0.620mm ±0.045mm 0.025mm ±0.003mm Bottom ViewSide ViewTop View Top Side Die Coating A1 Corner Recommended Footprint 1.60mm 0.80mm0.22mm Copper Pad Diameter 0.40mm 0.40mm (NSMD Pad Type) 0.32mm Solder Mask Opening Kinetic Technologies cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Kinetic Technologies product. No intellectual property or circuit patent licenses are implied. Kinetic Technologies reserves the right to change the circuitry and specifications without notice at any time.