DF6R

TPL910 3PEAK | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 17

Technical content

Features

◼ Input Voltage Range: 2.2 V to 6.5 V ◼ Output Voltage Options: ◆ Fixed Output Voltage: 0.8 V to 5 V ◆ Adjustable Output Voltage: 0.8 V to 5.2 V ◼ 3% Accuracy over Line Regulation, Load Regulation, and Operating Temperature Range ◼ 1 A Maximum Output Current ◼ Low Dropout Voltage: 500 mV Maximum at 1 A ◼ High PSRR: ◆ 65 dB at 1 kHz ◆ 50 dB at 100 kHz ◼ 24 μVRMS Output Voltage Noise (100 Hz to 100kHz) ◼ Excellent Transient Response ◼ Stable with a 10 μF or Larger Ceramic Output Capacitor ◼ Thermal Shutdown and Over-Current Protection ◼ Operating Junction Temperature: –40°C to +125°C ◼ Package: 3×3 DFN-8

Applications

◼ Wireless Communication: CPU, ASIC, FPGA, CPLD, DSP ◼ High-Performance Analog: ADC, DAC, LVDS, VCO ◼ Noise-Sensitive Imaging: CMOS Sensors, Video ASICs

Description

The TPL910 series products are 1-A high -current, 24-μVRMS low-noise, high-PSRR, high-accuracy linear regulators with only 500-mV maximum ultra-low dropout voltage at 1-A load current. The TPL910 series products support both fixed output voltage ranges from 0.8 V to 5 V and adjustable output voltage ranges from 0.8 V to 5.2 V with external resistor divider. Ultra-low noise, high PSRR, and high output current capabi lity makes the TPL910 series products ideal power supply for noise- sensitive applications, such as high -speed communication facilities, test and measurement devices, or high -definition imaging equipment. Accurate output voltage tolerance, output remote sen sing, excellent transient response, and adjustable soft-start control ensures the TPL910 series products optimal power supply for the large -scale processors or digital loads, such as ASIC, FPGA, CPLD and DSP . The TPL910 series products provide 3×3 DFN-8 package with guaranteed operating junction temperature range (T J) from – 40°C to +125°C. Typical Application Schematic VIN TPL910 CIN COUTR1 VOUT EN FB GND CFF NR VIN Digital I/O or VIN VOUT CNR

1-A Output, High-PSRR, Low-Noise LDO Regulator Product Family Table Part Number Output Voltage Orderable Number Package Transport Media, Quantity MSL Marking information TPL910 Adjustable (0.8 V ~ 5.2 V) TPL910ADJ-DF6R 3×3 DFN-8 4,000 MSL3 L910A

1-A Output, High-PSRR, Low-Noise LDO Regulator Table of Contents

1-A Output, High-PSRR, Low-Noise LDO Regulator

Revision History

2019/04/30 Rev.Pre Preliminary Version 2020/05/08 Rev.A.0 Initial Release 2021/06/07 Rev.A.1 1. Update the top view figure of DFN-8 Package in Page 5 2. Add Tape and Reel Information in Page 16 3. Change Package Outline Dimensions, 3×3 DFN-8, in Page 17

1-A Output, High-PSRR, Low-Noise LDO Regulator Pin Configuration and Functions TPL910 Series Top View 4 5 8OUT OUT FB GND IN IN NR EN Exposed PAD Pin Functions NAME PIN NUMBER TYPE DESCRIPTION EN 5 I Regulator enable pin. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic startup, connect EN to IN directly. FB 3 I Output voltage feedback pin. Connect to a n external resistor divider to adjust the output voltage. A 10-nF feed-forward capacitor from FB to OUT (as close as possible to FB pin) is recommended to maximize regulator ac performance. GND 4 – Ground reference pin. Connect GND pin to PCB ground plane directly. IN 7, 8 I Input voltage pin. A 10-μF or larger ceramic capacitor from IN to ground (as close as possible to IN pin) is required to reduce the jitter from previous-stage power supply. NR 6 I Noise-reduction and soft-start pin. A 10-nF or larger capacitor from NR/SS to GND (as close as possible to NR/SS pin) is recommended to maximize ac performance. OUT 1, 2 O Regulated output voltage pin. A 10-μF or larger ceramic capacitor from OUT to ground (as close as possible to OUT pin) is required to ensure regulator stability. (1) Exposed PAD must be connected to a large-area ground plane to maximum the thermal performance.

1-A Output, High-PSRR, Low-Noise LDO Regulator Specifications Absolute Maximum Ratings MIN MAX UNIT IN, EN –0.3 7 V OUT –0.3 VIN + 0.3 V FB, NR –0.3 3.6 V TJ Junction Temperature Range –40 150 °C TSTG Storage Temperature Range –65 150 °C TL Lead Temperature (Soldering 10 sec) 260 °C (1) Stresses beyond the Absolute Maximum Ratings may permanently damage the device. (2) All voltage values are with respect to GND. ESD Ratings Condition Minimum Level Unit HBM Human Body Model ESD ANSI/ESDA/JEDEC JS-001 ±4000 V CDM Charged Device Model ESD ANSI/ESDA/JEDEC JS-002 ±1500 V Recommended Operating Conditions MIN TYP MAX UNIT IN Input voltage 2.2 6.5 V EN Enable voltage 0 6.5 V OUT Output voltage 0.8 5.2 V OUT Output current 0 1 A CIN Input capacitor 10 µF COUT Output capacitor 10 µF CFF Feed-forward capacitor 10 nF CNR NR capacitor 10 nF PD Power dissipation 1000 mW TJ Junction Temperature Range –40 125 °C Thermal Information PACKAGE θJA θJC,bottom UNIT 3×3 DFN-8 69.3 8.16 °C/W

1-A Output, High-PSRR, Low-Noise LDO Regulator

Electrical Characteristics

TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VOUT(NOM) + 0.5 V or 2.2 V, whichever is greater; VEN = 2.2 V, IOUT = 1 mA, CIN = 10 µF, COUT = 47 µF, CNR = 10 nF, CFF = open, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Supply Input Voltage and Current VIN Input supply voltage range (1) 2.2 6.5 V UVLO Input supply UVLO VIN rising, RL = 1 kΩ 1.3 2.1 V Hysteresis 200 mV IGND GND pin current VIN = 6.5 V, IOUT = 1 mA 15 30 mA VIN = 6.5 V, IOUT = 1 A 15 30 mA ISD Shutdown current VIN = 6.5 V, VEN = Low 10 25 µA Device Enable VIH(EN) EN pin high-level input voltage Device enable 1.2 6.5 V VIL(EN) EN pin low-level input voltage Device disable 0 0.4 V IEN EN pin current VIN = 6.5 V, VEN = 0 V to 6.5 V 0.1 1 µA Regulated Output Voltage and Current VFB Feedback voltage 0.79 0.8 0.81 V IFB FB pin leakage current VIN = 6.5 V, stress VFB = 0.8V 0.1 1 µA VNR NR/SS pin voltage 0.8 V INR NR/SS pin charging current VIN = 6.5 V, VNR = GND 7.2 9 µA VOUT Output accuracy (2) VIN = VOUT(NOM) + 0.5 V or 2.5 V to 6 V, VOUT = 0.8 V to 5.2 V, IOUT = 100 mA to 500 mA –2% 2% VIN = VOUT(NOM) + 0.5 V or 2.2 V to 6.5 V, VOUT = 0.8 V to 5.2 V, IOUT = 100 mA to 1 A –3% 3% ΔVOUT Line regulation VIN = VOUT(NOM) + 0.5 V or 2.2 V to 6.5 V, IOUT = 100 mA 0.03 mV/V Load regulation IOUT = 100 mA to 1 A 0.07 mV/A VDO Dropout voltage (1) VIN = VOUT(NOM) + 0.5 V or 2.2 V to 6.5 V, IOUT = 500 mA, VFB = GND or VSNS = GND 250 mV VIN = VOUT(NOM) + 0.5 V or 2.2 V to 6.5 V, IOUT = 750 mA, VFB = GND or VSNS = GND 350 mV VIN = VOUT(NOM) + 0.5 V or 2.2 V to 6.5 V, IOUT = 1 A, VFB = GND or VSNS = GND 500 mV tSTR Start-up time VOUT(NOM) = 3.3 V, VOUT = 0% to 90% VOUT(NOM), RL = 3.3 kΩ, COUT = 10 μF, CNR = 100 nF 13 ms (1) Minimum VIN = VOUT(NOM) + VDO or 2.2 V, whichever is greater. (2) Resistor tolerance is not included. Output accuracy is not tested at this condition: VOUT = 0.8 V, 4.5V ≤ VIN ≤ 6.5 V, and 750 mA ≤ IOUT ≤ 1 A, because the power dissipation is out of package limitation.

1-A Output, High-PSRR, Low-Noise LDO Regulator Electrical Characteristics (continued) TJ = –40°C to +125°C (typical value at TJ = +25°C), VIN = VOUT(NOM) + 0.5 V or 2.2 V, whichever is greater; VEN = 2.2 V, IOUT = 1 mA, CIN = 10 µF, COUT = 47 µF, CNR = 10 nF, CFF = open, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PSRR and Noise PSRR Power supply ripple rejection VIN = 5.5 V, VOUT = 5.2 V, IOUT = 1 A f = 1 kHz 65 dB f = 100 kHz 50 dB f = 1 MHz 30 dB VN Output noise voltage BW = 10 0 Hz to 100 kHz, V IN = 5.5 V, VOUT = 5.2 V, IOUT = 1 A, CNR = 100 nF, CFF = 10 nF 24 μVRMS Temperature Range TSD Thermal shutdown threshold Temperature increasing 160 °C Hysteresis 20 °C TJ Operating junction temperature –40 125 °C

1-A Output, High-PSRR, Low-Noise LDO Regulator Detailed Description Overview The TPL910 series products are 1-A high-current, 24-μVRMS low-noise, high-PSRR, high-accuracy linear regulators with only 500-mV maximum ultra-low dropout voltage at 1-A load current. The TPL910 series products support both fixed output voltage ranges from 0.8 V to 5 V and adjustable output voltage ranges from 0.8 V to 5.2 V with external resistor divider. Ultra-low noise, high PSRR, and high output current capability makes the TPL910 series products ideal power supply for noise - sensitive applications, such as high -speed communication facilities, test and measurement devices, or high -definition imaging equipment. Accurate output voltage tolerance, output remote sensing, excellent transient response, and adjustable soft-start control ensures the TPL910 series products optimal power supply for the large-scale processors or digital loads, such as ASIC, FPGA, CPLD and DSP . Functional Block Diagram IN Regulator Control Current Control Thermal Control Enable Control VREF Active Discharge UVLO Control EA PSRR Control INR/SS EN NR OUT FB GND Figure 11 Functional Block Diagram Feature Description Enable (EN) The TPL910 series provide a device enable pin (EN) to enable or disable the device. Connect this pin to the GPIO of an external digital logic control circuit to control the device. When the VEN voltage falls below VIL(EN), the LDO device turns off, and when the VEN ramps above VIH(EN), the LDO device turns on. Under-Voltage Lockout (IN and UVLO) The TPL910 series use an under-voltage lockout circuit to keep the output shut off until the internal circuitry operates properly. Voltage Regulation (OUT and FB) The TPL910 series provide adjustable output voltage option. Using external resistors divider, the output voltage of TPL910 series is determined by the value of the resistor R1 and R2 in Figure 12. Use Equation 1 to calculate the output voltage.

1-A Output, High-PSRR, Low-Noise LDO Regulator OUT FB R1V V 1 R2 (1) Where the feedback voltage VFB is 0.8 V. Table 1 provides a list of recommended resistor combinations to achieve the common output voltage values. Table 1 External Resistor Combinations Target Output Voltage (V) External Resistors Divider Calculated Output Voltage (V) R1 (kΩ) R2 (kΩ) 0.80 0 Open 0.800 0.81 2 160 0.810 0.82 4.02 160 0.820 0.83 6.04 160 0.830 0.84 8.06 160 0.840 0.85 10 160 0.850 0.86 12 160 0.860 0.87 12.4 143 0.869 0.88 12.4 124 0.880 0.89 12 107 0.890 0.90 12.4 100 0.899 0.95 12.4 66.5 0.949 1.00 12.4 49.9 0.999 1.10 12.4 33.2 1.099 1.20 12.4 24.9 1.198 1.50 12.4 14.3 1.494 1.80 12.4 10 1.792 1.90 12.1 8.87 1.891 2.50 12.4 5.9 2.481 2.85 12.1 4.75 2.838 3.00 12.1 4.42 2.990 3.30 11.8 3.74 3.324 3.60 12.1 3.48 3.582 4.50 11.8 2.55 4.502 5.00 12.4 2.37 4.986 Output Active Discharge The TPL910 series integrate an output discharge path from OUT to GND. When the device is disabled, either EN or VIN is lower than turn-on threshold, the output will actively discharge the output voltage through an internal resistor of several hundred ohms. Do not rely on this active discharge circuit for discharging large output capacitors when the input voltage falls below the output voltage. Reverse current flow through internal power MOS FET can permanently damage the device, and external current protection is essential at this condition. Over-Current Protection The TPL910 series integrate an internal current limit that helps to protect the device during fault conditions. When the output is pulled down below the target output voltage, over -current protection starts to work and limit the output current to a typical value of 1.4 A. Under the over-current conditions, the internal junction temperature ramps up quickly. When the junction temperature is high enough,

1-A Output, High-PSRR, Low-Noise LDO Regulator it will cause the over temperature protection. Over-Temperature Protection The recommended operating junction temperature range is –40°C to 125°C. When the junction temperature is between 125°C and the thermal shutdown (TSD) threshold, the regulator can still work well, but will reduce the device lifetime for long-term using. The over-temperature protection works when the junction temperature exceeds the thermal shutdown (TSD) threshold, which turns off the regulator immediately. Until when the device cools down and the junction temperature falls below the thermal shutdown threshold minus thermal shutdown hysteresis, the regulator turns on again.

1-A Output, High-PSRR, Low-Noise LDO Regulator J A D JAT T P = +  (3) Layout Requirements

• Both input capacitors and output capacitors must be placed as close to the device pins as possible, and vias between capacitors and device power pins must be avoid.
• It is recommended to bypass the input pin to ground with a 0.1 μF bypass capacitor. The loop area formed by the bypass capacitor connection, IN pin and the GND pin of the system must be as small as possible.
• It is recommended to use wide trace lengths or thick copper weight to minimize I×R drop and heat dissipation.

1-A Output, High-PSRR, Low-Noise LDO Regulator Tape and Reel Information Order Number Package (mm) (mm) (mm) (mm) (mm) (mm) (mm) Pin1 Quadrant

1-A Output, High-PSRR, Low-Noise LDO Regulator Package Outline Dimensions 3× 3 DFN-8 Top View Side View Bottom View 3PEAK and the 3PEAK logo are registered trademarks of 3PEAK INCORPORATED. All other trademarks are the property of their respective owners.