CXR702080

CXR702080 SONY | Alldatasheet

Document overview

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Technical content

Features

• CPU SR11 series 32-bit RISC CPU core  Minimum instruction cycle 54.3ns (f SRC : 18.432MHz) 30.5µs (fTEX : 32.768kHz)  Incorporated ROM 256K bytes  Incorporated RAM 16K bytes  Peripheral functions — Bus interface unit — DMA controller 4 channels — A/D converter 8-bit 4-analog input, successive approximation system — Serial interface Clock synchronization, 2 channels Clock synchronization, 1 channel (Incorporated 64-byte buffer RAM) Asynchronization, 2 channels — Timers 8-bit timer, 8 channels 16-bit capture timer, 3 channels 8-bit time-base timer Clock prescaler 16-bit watchdog timer — Memory stick interface — Beep output circuit — External interruption 11 channels (polarity selection and both edge detection possible)  Standby mode Idle/sleep/stop  Package 176-pin plastic LFLGA Structure Silicon gate CMOS IC

– 2 – CXR702080 Block Diagram PORT M SERIAL INTERFACE UNIT (CH0) RAM INTERRUPT CONTROLLER UART (CH0) SCS0 AN0 to AN3 INT0 to INT9 SI0 SO0 SCK0 SCS1 SI1 SO1 EC0 MSSCLK MSIDR MSDIO MSBS SCK1 to A23 to D15 CS0 to CS7 RD WE LWR/LB UWR/UB WAIT 8-BIT TIMER/COUNTER (CH0) 8-BIT TIMER (CH1) SERIAL INTERFACE UNIT (CH1) MEMORY STICK INTERFACE 8-BIT TIMER/COUNTER (CH2) 8-BIT TIMER (CH3) 8-BIT TIMER (CH4) 8-BIT TIMER (CH5) 8-BIT TIMER (CH6) 8-BIT TIMER (CH7) TDI TMS TCK TEX TX EXTAL XTAL VDD VSS AVREF AVDD AVSS TDO RTCK TXOUT XOUT EC2 BEEP SCS2 SI2 SO2 SCK2 SERIAL INTERFACE UNIT (CH2) UART (CH1)TxD1 RxD1 TxD0 RxD0 A/D CONVERTER 2∗2 2∗2 8∗1 3∗1 RAM 16K BYTES EXTERNAL BUS DMAC (CH0) DMAC (CH1) DMAC (CH2) DMAC (CH3) 16-BIT CAPTURE TIMER (CH0) 16-BIT CAPTURE TIMER (CH1) 16-BIT CAPTURE TIMER (CH2) TOKEI PRESCALER WATCHDOG TIMER TRST MSINS PORT N PORT O PORT L PORT K PORT J PORT I PORT H PORT G PORT F PORT E PORT D PORT C PORT B PORT A RST DACK0 DREQ0 MA0 to MA18 MD0 to MD7 MCS0, MCS1 CT0ED0 CT0ED1 CT1ED0 CT1ED1 CT2ED0 CT2ED1 DACK1 DREQ1 MRD MWE CLOCK GENERATOR/ SYSTEM CONTROLLER BUS INTERFACE UNIT ARM7TDMI CPU CORE ROM 256K BYTES ∗1 The number of causes of interrupts generated from the module is as shown. But the number of causes input to the interrupt controller differs from the shown becauses of OR. ∗2 A part of the interrupt signals generated from UART , MEMORY STICK INTERFACE is input to the interrupt controller via DMA depending on applications.

– 3 – CXR702080 Pin Assignment (T op View) 176-pin LFLGA package  Pin Assignment 7 4 10 811 14 15 12 18 19 16 22 23 20 26 27 24 30 2831 34 35 32 374050 41 38 818290 8591 949592 96 99 98 102103100 106107104 110108 111 114115112 118119116 122120 123 128125 126 134 129 135 138 139 136 142 143 140 146 147 144 150 151 148 154 155 152 158 159 156 160 163 162 166 164 167 172 169 173 170 2 45656973 495357617780838687 133 137 141 145 149 153 157 161 165 168 171 174 175 2345678910111213 N M L K J H G F E D C B P R 101 105 109 113 117 121 124 127 130 131 132 1415 176 A N M L K J H G F E D C B P R A 23456789101112131415 1

– 4 – CXR702080  Pin Assignment Table Pin No. Pin position Symbol PB3 PB4 PB5 PB6 PB7 V DD VSS PC0 PC1 PC2 PC3 PC4 PC5 PD0 PD1 PD2 PD3 VDD VSS PE0/INT0 PE1/INT1 PE2/INT2 PE3/INT3 PE4/INT4 PE5/INT5 PE6/INT6 PE7/INT7 PF0/EC0 PF1/T1 PF2/EC2 PF3/T3 PF4/BEEP PF5/TXOUT VDD VSS PG0/CT0ED0 PG1/CT0ED1 Pin No. Pin position P10 M10 Symbol PG2/CT1ED0 PG3/CT1ED1 PG4/CT2ED0 PG5/CT2ED1 PH0/TxD0 PH1/RxD0 PH2/TxD1 PH3/RxD1 VDD VSS PI0/MD0 PI1/MD1 PI2/MD2 PI3/MD3 PI4/MD4 PI5/MD5 PI6/MD6 PI7/MD7 VDD VSS PJ0/D0 PJ1/D1 PJ2/D2 PJ3/D3 PJ4/D4 PJ5/D5 PJ6/D6 PJ7/D7 VDD VSS PK0/D8 PK1/D9 PK2/D10 PK3/D11 PK4/D12 PK5/D13 PK6/D14 Pin No. 100 101 102 103 104 105 106 107 108 109 110 111 Pin position M11 N10 R10 P11 N11 R11 P12 P13 R12 N12 N13 R13 R14 R15 P15 P14 N14 M14 N15 M12 M13 L14 M15 L12 L13 K14 L15 K12 K13 J14 K15 J12 J13 H14 J15 H12 H13 Symbol PK7/D15 VDD TEX TX V SS CS0 CS1 RD LWR/LB UWR/UB MRD MWE/WE MCS0 V DD VSS MA0 MA1/A9 MA2/A10 MA3/A11 MA4/A12 MA5/A13 MA6/A14 MA7/A15 MA8/A16 PL0/MA9/A17 PL1/MA10/A18 PL2/MA11/A19 PL3/MA12/A20 PL4/MA13/A21 PL5/MA14/A22 PL6/MA15/A23 VDD VSS MA16 MA17 MA18/A0

– 5 – CXR702080 PN5/SO1 PN6/SI1 PN7/SCS1/INT9 PO0/SCK2 PO1/SO2 PO2/SI2 PO3/SCS2 XOUT/CKO VDD VSS NC NC P A0/WAIT P A1/CS2 P A2/CS3 P A3/CS4 P A4/CS5 P A5/MCS1 PB0 PB1 PB2 Pin No. 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 Pin position G14 H15 G12 G13 F14 G15 F12 F13 E14 F15 E12 E13 E15 D14 C14 D15 D13 C13 C15 B15 A15 A14 Symbol V DD EXT AL XTAL V SS MSDIO MSBS MSSCLK MSDIR MSINS DACK0 DACK1 DREQ0 DREQ1 TEST2 TEST0 Pin No. 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Pin position B14 B13 B12 A13 D12 C12 B11 A12 D11 C11 B10 A11 D10 C10 A10 Symbol TEST1 AN0 PM0/AN1 PM1/AN2 PM2/AN3 AV SS AV REF AV DD TDI TMS TRST TCK RTCK TDO RST V DD VSS PN0/SCK0 PN1/SO0 PN2/SI0 PN3/SCS0/INT8 PN4/SCK1 Pin No. 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Pin position Symbol

– 6 – CXR702080 Pin Functions Symbol P A0/WAIT P A1/CS2 to P A4/CS5 P A5/MCS1 PB0 to PB7 PC0 to PC5 PD0, PD1 PD2, PD3 PE0/INT0 to PE7/INT7 PF0/EC0 PF1/T1 PF2/EC2 PF3/T3 PF4/BEEP PF5/TXOUT PG0/CT0ED0 to PG5/ CT2ED1 I/O I/O / Input I/O / Output I/O / Output I/O I/O Output I/O I/O / Input I/O / Input I/O / Output I/O / Input I/O / Output I/O / Output I/O / Output I/O / Input Functions (Port A) 6-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (6 pins) (Port B) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port C) 6-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (6 pins) (Port D) 4-bit open drain port. Lower 2 bits are for output; upper 2 bits are for I/O. (4mA drive) Upper 2 bits can be specified in 1-bit units. (4 pins) (Port E) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port F) 6-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (6 pins) (Port G) 6-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (6 pins) Wait input for external bus Chip select output for external S bus (4 pins) Chip select output for external M bus. External interruption request input. (8 pins) External event input to 8-bit timer (CH0). 8-bit timer (CH1) output. External event input to 8-bit timer (CH2). 8-bit timer (CH3) output. Beep output. Sub oscillation output. Capture input of 16-bit capture timer. (6 pins)

– 7 – CXR702080 Symbol PH0/TxD0 PH1/RxD0 PH2/TxD1 PH3/RxD1 PI0/MD0 to PI7/MD7 PJ0/D0 to PJ7/D7 PK0/D8 to PK7/D15 A1 to A8 MA18/A0 MA1/A9 to MA8/A16 PL0/MA9/A17 to PL6/MA15/ A23 MA0 MA16, MA17 AN0 PM0/AN1 to PM2/AN3 I/O I/O / Output I/O / Input I/O / Output I/O / Input I/O / I/O I/O / I/O I/O / I/O Output Output / Output Output / Output I/O / Output / Output Output Output Input Input / Input Functios (Port H) 4-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (4 pins) (Port I) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port J) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port K) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port L) 7-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (7 pins) (Port M) 3-bit input port. (3-pins) UART (CH0) transmit data output. UART (CH0) receive data input. UART (CH1) transmit data output. UART (CH1) receive data input. Data bus for external M bus. (8 pins) Data bus for external S bus. (16 pins) Address bus output for external M bus (19 pins) Analog input to A/D converter. (4 pins) Address bus output for external S bus. (24 pins)

– 8 – CXR702080 Symbol PN0/SCK0 PN1/SO0 PN2/SI0 PN3/SCS0/ INT8 PN4/SCK1 PN5/SO1 PN6/SI1 PN7/SCS1/ INT9 PO0/SCK2 PO1/SO2 PO2/SI2 PO3/SCS2 CS0, CS1 RD LWR/LB UWR/UB MRD MWE/WE MCS0 DACK0 DREQ0 DACK1 DREQ1 MSDIR MSBS MSSCLK MSDIO MSINS TEST0 TEST1 TEST2 TDI I/O I/O / I/O I/O / Output I/O / Input I/O / Input / Input I/O / I/O I/O / Output I/O / Input I/O / Input / Input I/O / I/O I/O / Output I/O / Input I/O / Input Output Output Output / Output Output / Output Output Output / Output Output Output Input Output Input Output Output Output I/O Input Input Input Input Input Functios (Port N) 8-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (8 pins) (Port O) 4-bit I/O port. I/O can be specified in 1-bit units. Pull-up resistor can be incorporated through program in 1-bit units. (4 pins) Chip select output for external S bus. (2 pins) Read signal output for external S bus. Write strobe signal output for D0 to D7. Write strobe signal output for D8 to D15. Read signal output for external M bus. Write signal output for external M bus. Chip select output for external M bus. T ransfer request acknowledge signal output from DMA controller (CH0). T ransfer request input to DMA controller (CH0). T ransfer request acknowledge signal output from DMA controller (CH1). T ransfer request input to DMA controller (CH1). Memory stick interface data I/O direction monitor. Memory stick interface bus state output. Memory stick interface clock output. Memory stick interface data I/O direction monitor. Memory stick interface card detection. T est. (Connect to Vss.) Data input for JT AG boundary scanning test. Serial clock (CH0) I/O. Serial data (CH0) output. Serial data (CH0) input. Serial chip select (CH0) External interruption input. request input. Serial clock (CH1) I/O. Serial data (CH1) output. Serial data (CH1) input. Serial chip select (CH1) External interruption input. request input. Serial clock (CH2) I/O. Serial data (CH2) output. Serial data (CH2) input. Serial chip select (CH2) input. Strobe signal output indicates access to D0 to D7. Strobe signal output indicates access to D8 to D15. Write signal output for external S bus.

– 9 – CXR702080 Symbol TMS TRST TCK RTCK TDO XOUT/CKO RST NC AV DD AVREF AV SS VDD VSS I/O Input Input Input Output Output Output / Output I/O Input Functions T est mode control input for JT AG boundary scanning test. Reset input for JT AG boundary scanning test. Clock input for JT AG boundary scanning test. Clock output for JT AG boundary scanning test. Data output for JT AG boundary scanning test. Oscillation connector of main oscillation. (When a clock is supplied externally, input it to EXT AL; opposite phase clock should be input to XT AL.) Main oscillation output. Oscillation connector of main oscillation. (When a clock is supplied externally, input it to TEX; opposite phase clock should be input to TX.) System reset. NC. (Leave this pin open or connect to Vss.) Positive power supply for A/D converter. Reference voltage input for A/D converter. GND for A/D converter. Positive power supply (Connect all twelve V DD pins to positive power supply.) GND (Connect all twelve Vss pins to GND) System clock output. EXT AL XTAL Input Output TEX TX Input Output

– 10 – CXR702080 I/O Circuit Format for Pins Pin Circuit format After a reset Port A data MPX RD WAIT Port A direction "0" after a reset Pull-up resistor "0" after a reset Input data latch Internal data bus IP Port A data MPX RD Port A direction "0" after a reset Port A function select "0" after a reset Input data latch Internal data bus MPX CS2 to CS5 S bus pin active MPX IP Pull-up resistor "0" after a reset Port A data MPX RD Port A direction "0" after a reset Port A function select "0" after a reset Input data latch Internal data bus MPX MCS1 (M bus unused: CS7) IP Pull-up resistor "0" after a reset P A0/WAIT Hi-Z P A1/CS2 to P A4/CS5 Hi-Z P A5/MCS1 Hi-Z

– 11 – CXR702080 Pin Circuit format After a reset Port B data MPX RD Port B direction "0" after a reset Input data latch Internal data bus IP Pull-up resistor "0" after a reset Port C data MPX RD Port C direction "0" after a reset Input data latch Internal data bus IP Pull-up resistor "0" after a reset Port D data RD Internal data bus Port D data MPX RD Port D read select "0" after a reset Input data latch Internal data bus IP PB0 to PB7 Hi-Z PC0 to PC5 Hi-Z PD0 PD1 Hi-Z PD2 PD3 Hi-Z

– 12 – CXR702080 Pin Circuit format After a reset Port E data MPX RD INT0 to INT7 Port E direction "0" after a reset Input data latch Internal data bus IP Pull-up resistor "0" after a reset CMOS Schmitt input Port F data MPX RD EC0, EC2 Port F direction "0" after a reset Input data latch Internal data bus IP Pull-up resistor "0" after a reset CMOS Schmitt input Port F data MPX RD Port F direction "0" after a reset Port F function select "0" after a reset Input data latch Internal data bus MPX T1, T3, BEEP , TXOUT IP Pull-up resistor "0" after a reset PE0/INT0 to PE7/INT7 Hi-Z PF0/EC0 PF2/EC2 Hi-Z PF1/T1 PF3/T3 PF4/BEEP PF5/TXOUT Hi-Z

– 13 – CXR702080 Pin Circuit format After a reset Port G data MPX RD CT0ED0, CT0ED1 CT1ED0, CT1ED1 CT2ED0, CT2ED1 Port G direction "0" after a reset Input data latch Internal data bus IP CMOS Schmitt input Pull-up resistor "0" after a reset Port H data MPX RD Port H direction "0" after a reset Port H function select "0" after a reset Input data latch Internal data bus MPX TxD0, TxD1 IP Pull-up resistor "0" after a reset Port H data MPX RD RxD0, RxD1 Port H direction "0" after a reset Input data latch Internal data bus IP CMOS Schmitt input Pull-up resistor "0" after a reset PG0/CT0ED0 PG1/CT0ED1 PG2/CT1ED0 PG3/CT1ED1 PG4/CT2ED0 PG5/CT2ED1 Hi-Z PH1/RxD0 PH3/RxD1 Hi-Z PH0/TxD0 PH2/TxD1 Hi-Z

– 14 – CXR702080 Pin Circuit format After a reset Port I data MPX RD Port I direction "0" after a reset Port I function select "1" after a reset Input data latch Internal data bus MPX M bus output enable MPX IP MD0 to MD7 MD0 to MD7 Pull-up resistor "0" after a reset Port J data MPX RD Port J direction "0" after a reset Port J function select "1" after a reset Input data latch Internal data bus MPX S bus output enable MPX IP D0 to D7 D0 to D7 Pull-up resistor "0" after a reset Port K data MPX RD Port K direction "0" after a reset Port K function select "1" after a reset Input data latch Internal data bus MPX S bus output enable MPX IP D8 to D15 D8 to D15 Pull-up resistor "0" after a reset PI0/MD0 to PI7/MD7 Hi-Z PJ0/D0 to PJ7/D7 Hi-Z PK0/D8 to PK7/D15 Hi-Z

– 15 – CXR702080 Pin Circuit format After a reset A1 to A8 S bus pin active MPX S bus/M bus select MA18 MPX S bus/M bus select MA1 to MA8 A9 to A16 Port L data MPX RD Port L direction "0" after a reset Port L function select "1" after a reset Input data latch Internal data bus MPX MA9 to MA15 S bus pin high impedance S bus/M bus select IP A17 to A23 Pull-up resistor "0" after a reset MA0 MA16, MA17 A1 to A8 Low MA18/A0 Low MA1/A9 to MA8/A16 Low MA0 Low MA16 MA17 Low PL0/MA9/A17 to PL6/MA15/A23 Low

– 16 – CXR702080 Pin Circuit format After a reset AN0 Analog input select ("1" after a reset) IP Internal data bus IP RD Input data latch AN1, AN2, AN3 Analog input select ("0" after a reset) Port M function select "1" after a reset Port N data MPX RD Port N direction "0" after a reset Port N function select "0" after a reset Input data latch Internal data bus MPX SCKEN0, SCKEN1 MPX IP SCK0, SCK1 SCK0, SCK1 CMOS Scmitt input Pull-up resistor "0" after a reset Port N data MPX RD Port N direction "0" after a reset Port N function select "0" after a reset Input data latch Internal data bus MPX SOEN0, SOEN1 MPX IP SO0, SO1 Pull-up resistor "0" after a reset PN0/SCK0 PN4/SCK1 Hi-Z PN1/SO0 PN5/SO1 Hi-Z AN0 Hi-Z PM0/AN1 to PM2/AN3 Hi-Z

– 17 – CXR702080 Pin Circuit format After a reset Port N data MPX RD SI0, SI1 Port N direction "0" after a reset Input data latch Internal data bus IP Pull-up resistor "0" after a reset Port N data MPX RD SCS0, SCS1 Port N direction "0" after a reset Input data latch Internal data bus IP INT8, INT9 CMOS Schmitt input Pull-up resistor "0" after a reset Port O data MPX RD Port O direction "0" after a reset Port O function select "0" after a reset Input data latch Internal data bus MPX SCKEN2 MPX IP SCK2 SCK2 CMOS Schmitt input Pull-up resistor "0" after a reset PN3/SCS0/INT8 PN7/SCS1/INT9 Hi-Z PO0/SCK2 Hi-Z PN2/SI0 PN6/SI1 Hi-Z

– 18 – CXR702080 Pin Circuit format After a reset Port O data MPX RD Port O direction "0" after a reset Port O functon select "0" after a reset Input data latch Internal data bus MPX SOEN2 MPX IP SO2 Pull-up resistor "0" after a reset Port O data MPX RD SI2 Port O direction "0" after a reset Input data latch Internal data bus IP Pull-up resistor "0" after a reset Port O data MPX RD SCS2 Port O direction "0" after a reset Input data latch Internal data bus IP CMOS Schmitt input Pull-up resistor "0" after a reset PO1/SO2 Hi-Z PO2/SI2 Hi-Z PO3/SCS2 Hi-Z

– 19 – CXR702080 Pin Circuit format After a reset CS0, CS1 S bus pin active RD S bus pin active 16-bit SRAM access method select MPX S bus pin active LWR, UWR LB, UB MRD MPX 16-bit SRAM access method select MWE WE MCS0 (M bus unused: CS6) DACK0, DACK1 DREQ0, DREQ1IP CS0 CS1 High RD High LWR/LB UWR/UB High MRD High MWE/WE High MCS0 High DACK0 DACK1 High DREQ0 DREQ1 Hi-Z

– 20 – CXR702080 Pin Circuit format After a reset MSDIR, MSBS, MSSCLK MSDIO (output data) MSDIO (input data) MSDIO output enable IP MSINSIP CMOS Schmitt input MPX Clock output enable Output clock select System clock XTAL EXTAL XTAL IP TEX TX IP  Diagram shows circuit configuration during oscillation.  Feedback resistor is removed during stop mode, and XT AL is driven at “H ” level.  Diagram shows circuit configuration during oscillation.  Feedback resistor is removed during stop mode, and TEX is driven at “L” level; TX at “H ” level. MSDIR MSBS MSSCLK Low MSDIO Hi-Z MSINS Hi-Z XOUT/CKO Oscillation output EXT AL XTAL Oscillation TEX TX Oscillation

– 21 – CXR702080 Pin Circuit format After a reset IP CMOS Schmitt input Internal reset signal RSTWD (from watchdog timer) TDI, TMS, TCK (to CPU core) IP TRST (to CPU core) IP RTCK TDO TDO output enable TEST0, TEST1 (to test circuit) IP TEST2 (to test circuit) IP RST Pull-up TDI TMS TCK Pull-up TRST Pull-down RTCK High TDO Low TEST0 TEST1 Hi-Z TEST2 Pull-down

– 22 – CXR702080 Absolute Maximum Ratings (Vss = 0V reference) Item Supply voltage Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation Symbol VDD AV DD AV SS AV REF VIN VOUT IOH ΣIOH IOL ΣIOL T opr Tstg PD Rating –0.3 to +4.6 AV SS to +4.6∗1 –0.3 to +0.3 AV SS to +4.6 –0.3 to +4.6∗2 –0.3 to +4.6∗2 –40 –40 to +85 –55 to +150 380 Unit V V V V V V mA mA mA mA mW Remarks Output (value per pin) T otal for all output pins Output (value per pin) T otal for all output pins ∗1 AV DD and VDD must be the same voltage. ∗2 VIN and VOUT must not exceed VDD + 0.3V . Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Recommended Operating Conditions (Vss = 0V reference) Item Supply voltage Analog voltage High level input voltage Low level input voltage Hysteresis width Operating temperature Symbol VDD AV DD VIH VIHS VIHEX VIL VILS VILEX VIHS – VILS T opr Min. 2.7 2.7 0.7VDD 0.7VDD 0.9VDD –0.3 –40 Ty p. 0.5 Max. 3.6 3.6 V DD VDD VDD + 0.3 0.2VDD 0.2VDD 0.4 +85 Unit V V V V V V V V V Remarks CMOS input∗2 CMOS Schmitt trigger input∗3 EXT AL∗4, TEX∗4 CMOS input∗2 CMOS Schmitt trigger input∗3 EXT AL∗4, TEX∗4 CMOS Schmitt trigger input∗3 ∗1 AV DD and VDD must be the same voltage. ∗2 Normal input port (P A to PC, PD2, PD3, PE, PF1, PF3 to PF5, PH0, PH2, PI to PM, PN1, PN2, PN5, PN6, PO1, PO2, DREQ0, DREQ1, MSDIO, TDI, TMS, TRST , TCK and TEST0 to TEST2). ∗3 Each pin of EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, SCK0 to SCK2, SCS0 to SCS2, INT8, INT9, MSINS and RST . ∗4 Specified only during external clock input.

– 23 – CXR702080

Electrical Characteristics

DC Characteristics (VDD = 2.7 to 3.6V) (T opr = –40 to +85°C, Vss = 0V reference) Item High level output voltage Low level output voltage Input current Symbol VOH VOL IIHE IILE IIHT IILT IIH IIL Pins P A to PC, PE to PL, PN, PO, T1, T3, TxD0, TxD1, MCS0, MCS1, MA0 to MA18, MD0 to MD7, MRD, MWE, CS0 to CS5, A0 to A23, D0 to D15, RD, LWR, LB, UWR, UB, WE, RST BEEP , TXOUT , SCK0 to SCK2, SO0 to SO2, DACK0, DACK1, MSDIR, MSBS, MSSCLK, MSDIO, RTCK, TDO, XOUT , CKO P A to PC, PE to PL, PN, PO, T1, T3, TxD0, TxD1, MCS0, MCS1, MA0 to MA18, MD0 to MD7, MRD, MWE, CS0 to CS5, A0 to A23, D0 to D15, RD, LWR, LB, UWR, UB, WE, RST PD, BEEP , TXOUT , SCK0 to SCK2, SO0 to SO2, DACK0, DACK1, MSDIR, MSBS, MSSCLK, MSDIO, RTCK, TDO, XOUT , CKO EXT AL TEX TRST P A to PC, PE to PL, PN, PO, WAIT , INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2, SCS0 to SCS2∗ TDI, TMS, TCK Conditions IOH = –0.5mA IOH = –4mA IOL = 1mA IOL = 4mA VIH = 3.6V VIL = 0.4V VIH = 3.6V VIL = 0.4V VIH = 3.6V VIL = Vss VIL = Vss Min. VDD – 0.4 VDD – 0.4 0.1 –0.1 0.1 –0.1 –20 –20 Typ. 100 –50 –100 Max. 0.4 0.4 –10 –10 240 –120 –240 Unit V V V V µA µA µA µA µA µA µA ∗1 P A to PC, PE to PL, PN, PO, WAIT , INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2 and SCS0 to SCS2 pins specify the input current when the pull-up resistor is selected, and specify leakage current when non-resistor is selected.

– 24 – CXR702080 Item I/O leakage current Supply current∗2 Input capacity Symbol IZH IZL IDD1 IDDI1 IDDS1 IDDS2 C IN Pins PD2, PD3, PM, AN0 to AN3, DREQ0, DREQ1, MSDIO, MSINS, P A to PC, PE to PL, PN, PO, WAIT , INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2, SCS0 to SCS2 PD2, PD3, PM, AN0 to AN3, DREQ0, DREQ1, MSDIO, MSINS, P A to PC, PE to PL, PN, PO, WAIT , INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2, SCS0 to SCS2∗ VDD P A to PC, PD2, PD3, PE to PO, WAIT , INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, AN0 to AN3, SCK0 to SCK2, SI0 to SI2, SCS0 to SCS2, MSDIO, EXT AL, TEX, RST , TEST0 DREQ0, DREQ1, MSINS, TDI, TMS, TRST , TCK, TEST1, TEST2 Conditions V I = 3.6V VI = 0V Main execution mode 18.432MHz crystal oscillation (C 1 = C2 = 10pF) Main idle mode 18.432MHz crystal oscillation (C 1 = C2 = 10pF) Sub sleep mode 32.768kHz crystal oscillation (C 1 = C2 = 10pF) Ta = –20 to +25°C Stop mode 32.768kHz oscillation stop Ta = –20 to +25°C Clock 1MHz 0V other than the measured pins Min. T yp. Max. –10 120 100 Unit µA µA mA mA µA µA µA µA pF pF ∗1 P A to PC, PE to PL, PN, PO, WAIT , INT0 to INT9, EC0, EC2, CT0ED0, CT0ED1, CT1ED0, CT1ED1, CT2ED0, CT2ED1, RxD0, RxD1, MD0 to MD7, D0 to D15, SCK0 to SCK2, SI0 to SI2 and SCS0 to SCS2 pins specify the input current when the pull-up resistor is selected, and specify leakage current when non-resistor is selected. 2 When all output pins are left open and XOUT/CKO = “L” (POSL register SLCKO bit = “00” or “01”).

– 25 – CXR702080 0.9VDD 0.4V tCRtXLtCF 1/fEX EXTAL XTAL tXH EXTAL C 1 XTAL C 2 Crystal oscillation Ceramic oscillation EXTAL XTAL 74HC04 External clock TEX C 1 TX C 2 32kHz clock applied condition Crystal oscillation 0.7VDD 0.2VDD tERtELtEF EC0 EC2 t EH Fig. 3. Event count input timing Fig. 2. System clock applied condition Fig. 1. Clock timing AC Characteristics (1) Clock timing (T opr = –40 to +85°C, VDD = 2.7 to 3.6V , Vss = 0V reference) Note)fPS4 is fSRC /16 (MHz) for output fSRC of main oscillation circuit. Item Main oscillation input clock frequency Main oscillation input clock pulse width Main oscillation input clock rise time, fall time Sub oscillation input clock frequency Event count input clock pulse width Event count input clock rise time, fall time Symbol fEX tXL, tXH tCR , tCF fTEX tEH , tEL tER , tEF Pins XTAL EXT AL XTAL EXT AL XTAL EXT AL TEX TX EC0 EC2 EC0 EC2 Min. 22.5 2/fPS4 Typ. 32.768 Max. 100/fEX Unit MHz ns ns kHz µs ms Conditions Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 2 32kHz clock applied condition Fig. 3 Fig. 3

– 26 – CXR702080 (2) Serial transfer (CH0, CH1, CH2) (T opr = –40 to +85°C, VDD = 2.7 to 3.6V , Vss = 0V reference) Notes)1. The load condition for the SCK output mode and SO output delay time is 50pF . 2. fSIO is fSRC /2 (MHz) for output fSRC of main oscillation circuit. As for fSCK and fSYS , see the following. Item SCS ↓ → SCK delay time SCS ↑ → SCK float delay time SCS ↓ → SO delay time SCS ↑ → SO float delay time SCS high level width SCK interval time SCK cycle time SCK high, low pulse width Input setup time (for SCK ↑) SI input hold time (for SCK ↑) SCK ↓ → SO delay time Symbol tDCSK tDCSKF tDCSO tDCSOF tWHCS tKINT tKCY tKH tKL tSIK tKSI tKSO Pins SCK0 SCK1 SCK2 SCK0 SCK1 SCK2 SO0 SO1 SO2 SO0 SO1 SO2 SCS0 SCS1 SCS2 SCK0 SCK0 SCK1 SCK2 SCK0 SCK1 SCK2 SI0 SI1 SI2 SI0 SI1 SI2 SO0 SO1 SO2 Conditions External start transfer mode Input mode (SCKOE = “1”) Output mode External start transfer mode (SCK = output mode, SCKOE = “1”) External start transfer mode (SOEN = “1”) External start transfer mode (SOEN = “1”) External start transfer mode SCK input mode Internal start high- speed transfer mode External start high- speed transfer mode Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode Min. 100 200 + + + + 400 1000/f SCK 200 500/fSCK – 50 100 Max. 100 100 100 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Serial clock selection PS3 ∗1 PS4 ∗1 PS5 PS6 PS7 ∗2 PS8 ∗2 fSCK (MHz) fSRC /8 fSRC /16 fSRC /32 fSRC /64 fSRC /128 fSRC /256 Serial clock frequency division ratio No frequency division 2 frequency division 4 frequency division 16 frequency division fSCK (MHz) No fSRC /2 fSRC /4 fSRC /16 ∗1 CH1, CH2 only ∗2 CH0 only 2000 fSIO 6000 fSYS tKCY 3000 fSIO 6000 fSYS tKCY

– 27 – CXR702080 0.7VDD 0.7VDD 0.2VDD 0.2VDD 0.7VDD 0.2VDD Output data 0.7VDD 0.2VDD 0.7VDD 0.2VDD Input data tWHCS tKCY tKL tSIK tDCSK tKSI tKSO tDCSOF tKINT tDCSO tDCSKFtKH SCS0 SCS1 SCS2 SCK0 SCK1 SCK2 SCK0 SCK1 SCK2 n byte n + 1 byte SO0 SO1 SO2 SI0 SI1 SI2 Fig. 4. Serial transfer CH0, CH1, CH2 timing

– 28 – CXR702080 (3) Serial transfer (memory stick) (T opr = –40 to +85°C, VDD = 2.7 to 3.6V , Vss = 0V reference) Notes)1. The load condition is 26pF . 2. fMSCK is as follows for output fSRC of main oscillation circuit. Item MSSCLK cycle time MSSCLK high, low pulse width MSBS output delay time MSDIO output delay time MSDIO input setup time MSDIO input hold time MSDIR output delay time Symbol tKCY tKH tKL tBSD tDIOD tDIOS tDIOH tDIRD Pins MSSCLK MSSCLK MSBS MSDIO MSDIO MSDIO MSDIR Min. 1000/fMSCK 500/fMSCK – 5 Max. Unit ns ns ns ns ns ns ns Conditions For MSSCLK ↓ For MSSCLK ↓ For MSSCLK ↑ For MSSCLK ↑ For MSSCLK ↓ Shift clock frequency division ratio No frequency division 2 frequency division 4 frequency division 8 frequency division fMSCK (MHz) fSRC fSRC /2 fSRC /4 fSRC /8

– 29 – CXR702080 0.2VDD tKCY tKL tKH tBSD Bus state output 0.7VDD MSSCLK MSBS MSDIO (output) tDIOD Output data MSDIO (input) tDIOS Input data tDIOH MSDIR tDIRD Serial data I/O direction output Fig. 5. Memory stick transfer timing

– 30 – CXR702080 FFh FEh AV REF 01h Absolute error Analog input Digital conversion value 00h Fig. 6. Definition of A/D converter terms (5) Interruption and reset input (T opr = –40 to +85°C, VDD = 2.7 to 3.6V , Vss = 0V reference) Fig. 7. Interruption input, RST input timing 0.2VDD tILtIH 0.7VDD INT0, INT1, INT2, INT3, INT4, INT5, INT6, INT7, INT8, INT9, RST Note) fSRC is output of main oscillation circuit. Item External interruption high, low level width Reset input high, low level width Symbol tIH tIL tIH tIL Pins INT0 to INT9 RST Min. 100 Ty p. 200 32/fSRC Max. Unit ns µs Conditions (4) A/D converter characteristics (T opr = –40 to +85°C, VDD = 2.7 to 3.6V , VDD = AVDD , Vss = AVss = 0V reference) Note) fPS4 is fSRC /16 (MHz) for output fSRC of main oscillation circuit. Conversion time indicates the time required from conversion start to ADC interruption request occurrence when 1 channel is selected. This includes sampling time. Item Resolution Absolute error Conversion time Sampling time Reference input voltage Analog input voltage Symbol tCONV tSAMP VREF VIAN Pins AV REF AN0 to AN3 Min. 19/fPS4 AV DD – 0.3 Ty p. 5/fPS4 Max. 20/fPS4 AV DD AVREF Unit Bits LSB µs µs V V Conditions VDD = AVDD = 2.7V

– 31 – CXR702080 Fig. 8. Recommended oscillation circuit EXTAL (i) (ii) ∗1 C1 1 XTAL C2 1 Rd 1 TEX C1 2 TX C2 2 Rd 2 Manufacturer RIVER EIETEC CO., LTD. Model FCK-03 fc (MHz) 18.432 C2 1 (pF) Rd 1 (Ω ) Circuit example (i) C1 1 (pF) ∗1 As for (ii) sub oscillation circuit C12, C22 and Rd2, decide them by seeing matching with oscillator. Appendix

– 32 – CXR702080 Package Outline Unit: mm Sony Corporation SONY CODE EIAJ CODE JEDEC CODE PACKAGE MASS PACKAGE STRUCTURE LFLGA-176P-01 ORGANIC SUBSTRATEPACKAGE MATERIAL TERMINAL TREATMENT TERMINAL MATERIAL S 0.10 P-LFLGA176-13X13-0.8 PIN 1 INDEX 13.0 0.2 AS 13.0 0.2 B S0.15 A B 3 – φ0.50 φ0.08M SA B 11112 34567891 0 1 2 1 3 1 4 5 A B C D E F G H J K L M N P R 0.5 0.5 0.55 0.55 0.8 X 0.55 0.55 0.8 176PIN LFLGA (PLASTIC) 0.90 0.90 DETAIL X 1.4MAX S S 0.2 0.1MAX 176 – φ0.40 ± 0.05 0.5g NICKEL & GOLD PLATING COPPER