CXP912032

CXP912032 SONY | Alldatasheet

Document overview

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Technical content

Features

An efficient instruction set as a controller — Direct addressing, numerous abbreviated forms, multiplication and division instructions
Instruction sets for C language and RTOS — Highly quadratic instruction system, general-purpose register of 16-bit
8-pin · 16-bank configuration
Minimum instruction cycle time 100ns at 20MHz operation
Incorporated ROM capacity 128K bytes
Incorporated RAM capacity 6144 bytes
Peripheral functions — A/D converter 8-bit 12-channel successive approximation system, automatic scanning function, 8-stage (soft) + 4-stage (hard) FIFO for conversion results (Conversion time: 20µs at 20MHz) — Serial interface Buffer RAM (128 bytes, supports high-speed transfer mode), 3 channels — Timers 8-bit timer/counter + 8-bit timer (with timing output), 1 channel 16-bit capture timer/counter (with timing output), 1 channel 16-bit timer, 4 channels — High-precision timing pattern generator PPG for 27 pins, 42 stages (max.) PPG for 16 pins, 16 stages (max.) RTG for 5 pins, 3 channels — PWM/DA gate output PWM for 14 bits, 2 channels (Repetitive frequency of 39.1kHz, 20MHz) DA gate pulse for 14 bits, 2 channels — Servo input control Capstan FG, drum FG/PG, reel FG — VSYNC separator — FRC capture unit 24-bit and 8-stage FIFO — PWM output 14 bits, 2 channels — General-purpose prescaler 10 bits, 1 channel — Pulse cycle measurement circuit 1 channel with mask input
General-purpose I/O 80 pins (max.; when all multi-purpose pins are used as general-purpose I/O.)
Interruption 28 factors, 28 vectors, multi-interruption and priority selection possible
Standby mode Sleep/stop
Package 100-pin plastic QFP/LQFP, 104-pin plastic LFBGA
Piggyback/evaluation chip CXP912000 100-pin ceramic QFP/LQFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin QFP (Plastic)100 pin LQFP (Plastic) 104 pin LFBGA (Plastic) Structure Silicon gate CMOS IC

– 2 – CXP912032 Vss VDD C LO C K G EN ER ATO R / SYSTEM C O N TR O LLER R AM

6144 BYTES

SER IAL IN TER FAC E U N IT (C H 0) R AM 8-BIT TIM ER /C O U N TER 0 8-BIT TIM ER 1 V SYN C SEPAR ATO R PU LSE M EASU R E U N IT SER VO IN PU T C O N TR O LC APSTAN D R U M R EEL PM SK PM I PW M 3 PW M 2 D A1 PW M 0 EXI1 EXI0 R FG 1 R FG 0 C FG SYN C 1 SYN C 0 C IN T EC 0 SC K2 SO 2 SI2 SC K1 SO 1 SI1 C S1 R EALTIM E PU LSE G EN ER ATO R NMI INT0 RST PORT A PORT B PORT C PORT D PORT E PORT F PORT G PORT H PORT I EXTAL /LiteDiagLines XTAL PR ESC ALER 14-BIT PW M /D A G EN ER ATO R (× 2ch) SER IAL IN TER FAC E U N IT (C H 1) C H 0 PORT J RTO0 to RTO4 PPO100 to PPO109 16-BIT TIM ER (× 4ch) PR O G R AM M ABLE PATTER N G EN ER ATO R R AM(C H 1) C H 1 C H 2 FIFO FIFO A/D C O N VER TER INT1 INT2 PPO000 to PPO018 PR O G R AM M ABLE PR ESC ALER PR O G R AM M ABLE PATTER N G EN ER ATO R R AM(C H 0) INTERRUPT CONTROLLER SER IAL IN TER FAC E U N IT (C H 2) 16-BIT C APTU R E TIM ER /C O U N TER R AM R AM AN0 to AN11 AVSS AVREF AVDD 14-BIT PW M G EN ER ATO R (× 2ch) D A0 PW M 1 XO U T (O SC O ) PC K/O SC I PO D PG D FG EC 2 SC K0 SO 0 SI0 C S0 C S2 Block Diagram

– 3 – CXP912032 Pin Configuration 1(Top View) 100-pin QFP Package PB2/PPO 010 PB3/PPO 011 PB4/PPO 012 PB5/PPO 013 PB6/PPO 014 PB7/PPO 015 PC 0/PPO 016 PC 1/PPO 017 PC 2/PPO 018 PC 3/R TO 0 PC 4/R TO 1 PC 5/R TO 2 PC 6/R TO 3 PC 7/R TO 4 VSS PD 0/KS0 PD 1/KS1 PD 2/KS2 PD 3/KS3 PD 4/KS4 PD 5/KS5 PD 6/KS6 PD 7/KS7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PJ0/AN 4/KS8 AVD D AVR EF AVSS AN 3 AN 2 AN 1 PI7/AN 0 VSS PI6/XO U T PI5/O SC O PI4/PC K/O SC I PI3/C S2/PO PI2/SC K2 PI1/SO 2 PI0/SI2 SC K0 SO 0 SI0 C S0 PH 7/C FG PH 6/D FG PH 5/D PG PH 4/PM SK PH 3/SYN C 1 PH 2/SYN C 0/PM I PH 1/EXI1 PH 0/EXI0 PG 7/R FG 1 PG 6/R FG 0 PB1/PPO009/PPO109 PB0/PPO008/PPO108 PA7/PPO007/PPO107 PA6/PPO006/PPO106 PA5/PPO005/PPO105 PA4/PPO004/PPO104 PA3/PPO003/PPO103 PA2/PPO002/PPO102 PA1/PPO001/PPO101 PA0/PPO000/PPO100 V SS V DD NC PJ7/AN11/KS15 PJ6/AN10/KS14 PJ5/AN9/KS13 PJ4/AN8/KS12 PJ3/AN7/KS11 PJ2/AN6/KS10 PJ1/AN5/KS9 PE7 PF0/EC0/INT0 PF1/EC2/INT1 PF2/CS1/NM I/CINT PF3/SI1/INT2 PF4/SO1 PF5/SCK1 PF6/T1 PF7/T2 RST V SS XTAL EXTAL V DD PG0/PW M PG1/PW M PG2/PW M PG3/PW M PG4/DA0 PG5/DA1 4039383736353431 32 33 41 42 43 44 45 46 47 48 49 50 8182838488 87 86 858990100 99 98 97 96 95 94 919293 Note) 1. Vss (Pins 15, 41, 72 and 90) must be connected to GND. 2. VDD (Pins 44 and 89) must be connected to VDD . 3. NC (Pin 88) is left open.

– 4 – CXP912032 Pin Configuration 2 (Top View) 100-pin LQFP Package PB4/PPO 012 PB5/PPO 013 PB6/PPO 014 PB7/PPO 015 PC 0/PPO 016 PC 1/PPO 017 PC 2/PPO 018 PC 3/R TO 0 PC 4/R TO 1 PC 5/R TO 2 PC 6/R TO 3 PC 7/R TO 4 VSS PD 0/KS0 PD 1/KS1 PD 2/KS2 PD 3/KS3 PD 4/KS4 PD 5/KS5 PD 6/KS6 PD 7/KS7 PE0 PE1 PE2 PE3 AVSS AN 3 AN 2 AN 1 PI7/AN 0 VSS PI6/XO U T PI5/O SC O PI4/PC K/O SC I PI3/C S2/PO PI2/SC K2 PI1/SO 2 PI0/SI2 SC K0 SO 0 SI0 C S0 PH 7/C FG PH 6/D FG PH 5/D PG PH 4/PM SK PH 3/SYN C 1 PH 2/SYN C 0/PM I PH 1/EXI1 PH 0/EXI0 PB3/PPO011 PB2/PPO010 PB1/PPO009/PPO109 PB0/PPO008/PPO108 PA7/PPO007/PPO107 PA6/PPO006/PPO106 PA5/PPO005/PPO105 PA4/PPO004/PPO104 PA3/PPO003/PPO103 PA2/PPO002/PPO102 PA1/PPO001/PPO101 PA0/PPO000/PPO100 V SS V DD NC PJ7/AN11/KS15 PJ6/AN10/KS14 PJ5/AN9/KS13 PJ4/AN8/KS12 PJ3/AN7/KS11 PJ2/AN6/KS10 PJ1/AN5/KS9 PJ0/AN4/KS8 AV DD AV REF PE4 PE5 PE6 PE7 PF0/EC0/INT0 PF1/EC2/INT1 PF2/CS1/NM I/CINT PF3/SI1/INT2 PF4/SO1 PF5/SCK1 PF6/T1 PF7/T2 RST V SS XTAL EXTAL V DD PG0/PW M PG1/PW M PG2/PW M PG3/PW M PG4/DA0 PG5/DA1 PG6/RFG0 PG7/RFG1 7677787980 26 27 28 29 30 4039383736353431 32 33 41 42 43 44 45 46 47 48 49 50 8182838488 87 86 858990100 99 98 97 96 95 94 919293 Note) 1. Vss (Pins 13, 39, 70 and 88) must be connected to GND. 2. VDD (Pins 42 and 87) must be connected to VDD . 3. NC (Pin 86) is left open.

– 5 – CXP912032 Pin Configuration 3 (Top View) 104-pin LFBGA Package A11A3 A13A4 A5 A6 A7 A8 A9 A10A1 B11B3 B4 B5 B6 B7 B8 B9 B10 C 2 C 12 C 13C 4 C 5 C 6 C 7 C 8 C 9 C 10C 1 D 11D 2 D 12D 3 D 13D 1 E11E2 E12E3 E13E1 F11F2 F12F3 F13F1 G 11G 2 G 12G 3 G 13G 1 H 11H 2 H 12H 3 H 13H 1 J11J2 J12J3 J13J1 K11K2 K12K3 K13K1 L2 L12 L13L4 L5 L6 L7 L8 L9 L10L1 M 11M 3 M 4 M 5 M 6 M 7 M 8 M 9 M 10 N 11N 3 N 13N 4 N 5 N 6 N 7 N 8 N 9 N 10N 1 N C 1 2 3 4 5 6 7 8 9 10 11 12 13 A B C D E F G H J K L M N PB1 PA7 PA4 PA1 V SS N C PJ5 PJ2 PJ0 N C PB2 PB0 PA5 PA2 VD D PJ7 PJ4 PJ1 AVD D PB6 PB5 PB3 PA6 PA3 PA0 PJ6 PJ3 AVR EF AN 2 PC 0 PB4 AVSS PI7 PC 3 PC 1 VSS PI5 PC 6 PC 4 PI4 PI2 VSS PD 0 PI1 PI0 PD 1 PD 3 C S0 SO 0 PD 4 PD 6 PH 5 PH 7 PD 7 PE3 PH 0 PH 4 PE1 PE4 PF1 PF4 VSS VD D PG 2 PG 7 PH 2 PE5 PE7 PF2 PF5 PF7 EXTAL PG 1 PG 4 PG 6 N C PE6 PF0 PF3 PF6 R ST XTAL PG 0 PG 3 PG 5 N C PE2 PE0 PD 5 PD 2 PC 7 PC 5 PC 2 PB7 AN 3 PH 1 PH 3 PH 6 SI0 SC K0 PI3 PI6 AN 1 Note) 1. Vss (Pins A7, E11, G1 and L7) must be connected to GND. 2. VDD (Pins B7 and L8) must be connected to VDD . 3. NC (Pins A1, A13, N1, N13 and A8) are left open. 4. A1, A13, N1 and N13 pins are reinforced balls.

– 6 – CXP912032 Output / Real time output / Real time output Output / Real time output / Real time output Output / Real time output Output / Real time output Output / Real time output I/O I/O (Port A) 8-bit output port. Data is gated with PPO0 and PPO1 contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO0 and PPO1 contents by OR- gate and they are output. (8 pins) (Port C) 8-bit I/O port. I/O can be specified by bit unit. Data is gated with PPO0 or RTO contents by OR- gate and they are output. (8 pins) (Port D) 8-bit I/O port. I/O can be specified by bit unit. Standby release input function can also be specified by bit unit. Can drive 12mA sync current when V DD = 5V. (8 pins) (Port E) 8-bit I/O port. I/O can be specified by bit unit. Can drive 12mA sync current when V DD = 5V. (8 pins) (Port F) 8-bit port. Lower 4 bits are for input; upper 4 bits are for output. (8 pins) Programmable pattern generator (PPG0, PPG1) output. Functions as high-precision real-time pulse output port. (PPG0 19 pins, PPG1 10 pins) Real-time pulse generator (RTG) output. Functions as high-precision real-time pulse output port. (5 pins) Symbol I/O Functions PA0/PPO000 /PPO100 to PA7/PPO007 /PPO107 PB0/PPO008 /PPO108 PB1/PPO009 /PPO109 PB2/PPO010 to PB7/PPO015 PC0/PPO016 to PC2/PPO018 PC3/RTO0 to PC7/RTO4 PD0 to PD7 PE0 to PE7 PF0/EC0/ INT0 Input / Input / Input Input / Input / Input Input / Input / Input / Input Input / Input / Input PF1/EC2/ INT1 PF2/CS1/ NMI/CINT PF3/SI1/INT2 PF4/SO1 PF5/SCK1 PF6/T1 PF7/T2 Output / Output Output / I/O Output / Output Output / Output Pin Description External event input for timer/counter. (2 pins) Serial data (CH1) input. Serial data (CH1) output. Serial data (CH1) I/O. 8-bit timer/counter output. 16-bit capture timer/counter output. Input to request external interruption. Active at the falling edge. Serial chip select (CH1) input. Input to request external interruption. Active at the falling edge. (2 pins) Input to request non-maskable interruption. Active at the falling edge. External capture input for 16-bit timer/counter.

– 7 – CXP912032 PG0/PWM0 PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/DA0 PG5/DA1 PG6/RFG0 PG7/RFG1 PH0/EXI0 PH1/EXI1 PH2/ SYNC0/PMI PH3/SYNC1 PH4/PMSK PH5/DPG PH6/DFG PH7/CFG SCK0 SO0 SI0 CS0 PI0/SI2 PI1/SO2 PI2/SCK2 PI3/CS2/PO PI4/PCK/ OSCI PI5/OSCO PI6/XOUT PI7/AN0 AN1 to AN3 PJ0/AN4 to PJ7/AN11 Output / Output Output / Output Output / Output Output / Output Output / Output Output / Output Input / Input Input / Input Input / Input Input / Input Input / Input / Input Input / Input Input / Input Input / Input Input / Input Input / Input I/O Output Input Input I/O / Input I/O / Output I/O / I/O I/O / Input / Output Input / Input / Input Input / Output Input / Output Input / Input Input I/O / Input 14-bit PWM output. (4 pins) DA gate pulse output. (2 pins) Reel FG input. (2 pins) External input for FRC capture unit. (2 pins) Composite sync signal input. (2 pins) Mask input for pulse cycle measurement circuit. Drum PG input. Drum FG input. Capstan FG input. Serial data (CH2) input. Serial data (CH2) output. Serial clock (CH2) I/O. General-purpose prescaler external clock input. Clock output from clock generator or general-purpose prescaler. Serial clock (CH0) I/O. Serial data (CH0) output. Serial data (CH0) input. Serial chip select (CH0) input. Pulse input for pulse cycle measurement circuit. (Port G) 8-bit port. Lower 6 bits are for output; upper 2 bits are for input. (8 pins) (Port H) 8-bit input port. (8 pins) (Port I) 8-bit port. Lower 4 bits are for I/O; upper 4 bits are for input. Lower 4 bits can be specified by bit unit. (8 pins) (Port J) 8-bit I/O port. I/O can be specified by bit unit. Standby release input function can also be specified by bit unit. (8 pins) Analog input for A/D converter. (12 pins) Serial chip select (CH2) input. General-purpose prescaler output. Symbol I/O Functions Connects a crystal for general- purpose prescaler clock oscillation. (Mask option)

– 8 – CXP912032 EXTAL XTAL RST AV DD AV REF AV SS VDD VSS Input Output I/O Input Connects a crystal for system clock oscillation. When the clock is supplied externally, input it to EXTAL and input an opposite phase clock to XTAL. System reset. Active at "L" level. Positive power supply for A/D converter. Reference voltage input for A/D converter. A/D converter GND. Positive power supply. All three V DD pins must be connected to the positive power supply. GND. All four VSS pins must be connected to GND. Symbol I/O Functions

– 9 – CXP912032 10 pins Hi-Z Hi-Z After a reset PA0/PPO000/ PPO100 to PA7/PPO007/ PPO107 PB0/PPO008/ PPO108 to PB1/PPO009/ PPO109 PC0/PPO016 to PC2/PPO018 PC3/RTO0 to PC7/RTO4 Hi-Z PD0/KS0 to PD7/KS7 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines PPO 0 data D ata bus O utput becom es active from H i-Z by w riting data to port register. Port A or Port B data R D PPO 1 data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines PPO 0 data D ata bus O utput becom es active from H i-Z by w riting data to port register. Port B data R D PPO 0 or R TO data D ata bus R D (Port C ) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port C direction /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort C data Input protection circuit IP (Every bit) /LiteDiagLines /LiteDiagLines "0" after a reset D ata bus R D /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port D direction /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort D data IP (Every bit) /LiteDiagLines /LiteDiagLines Standby release "0" after a reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort D standby release data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Edge detection ∗ Large current drive transistor 6 pins Hi-Z PB2/PPO010 to PB7/PPO015 I/O Circuit Format for Pins Port A Port B Pin Circuit format 8 pins 8 pins Port B Port C Port D

– 10 – CXP912032 8 pins Hi-Z Hi-Z After a reset PE0 to PE7 PF2/CS1/ NMI/CINT Hi-Z PF4/SO1 D ata bus R D /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port E direction/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort E data IP (Every bit) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines "0" after a reset ∗ Large current drive transistor /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP R D (Port F) D ata bus Schm itt trigger input Interrupt circuit and tim er/counter or SIO /LiteDiagLines /LiteDiagLines /LiteDiagLines IP R D (Port F) Schm itt trigger input/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort F function selection Interrupt circuit Tim er/counter or SIO D ata bus "0" after a reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines M PX D ata bus R D (Port F) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port F function selection SO 1 from SIO "0" after a reset H i-Z control /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort F data 3 pins Hi-Z PF0/EC0/INT0 PF1/EC2/INT1 PF3/SI1/INT2 Port E Pin Circuit format 1 pin 1 pin Port F Port F Port F

– 11 – CXP912032 1 pin Hi-Z Hi-Z After a reset PF5/SCK1 PG6/RFG0 PG7/RFG1 Hi-Z PH0/EXI0 PH1/EXI1 PH2/SYNC0/PMI PH3/SYNC1 PH4/PMSK PH5/DPG PH6/DFG PH7/CFG /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines M PX D ata bus R D (Port F) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort F function selection Internal serial clock from SIO "0" after a reset H i-Z control /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port F data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesIP SIO Schm itt trigger input /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines M PX D ata bus R D (Port F) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port F function selection Tim er/counter "0" after a reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort F data"1" w hen reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines M PX D ata bus R D (Port G ) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port G function selection D A gate output or PW M output "0" after a reset H i-Z control /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port G data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesIP R D (Port G ) D ata bus Servo circuit Schm itt trigger input /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP R D (Port H ) D ata bus Servo circuit N ote) PH 2/SYN C 0/PM I and PH 3/SYN C 1 can select C M O S Schm itt trigger input or TTL Schm itt trigger input w ith the m ask option. Schm itt trigger input 2 pins "H" level Hi-Z PF6/T1 PF7/T2 PG0/PWM0 PG1/PWM1 PG2/PWM2 PG3/PWM3 PG4/DA0 PG5/DA1 Port F Pin Circuit format 2 pins 8 pins Port F Port G 6 pins Port G Port H

– 12 – CXP912032 2 pins Hi-Z Hi-Z After a reset CS0 SI0 PI0/SI2 Hi-Z PI1/SO2 PI2/SCK2 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP SIO Schm itt trigger input SO 0 output enable /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines SO 0 from SIO SC K0 output enable /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Internal serial clock from SIO /LiteDiagLines /LiteDiagLines IP External serial clock to SIO Schm itt trigger input D ata bus R D (Port I) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port I direction/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort I data IP (Every bit) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines "0" after a reset SIO Schm itt trigger input /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines M PX /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort I data /LiteDiagLines /LiteDiagLines IP D ata bus R D (Port I) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port I function selection /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines M PX Schm itt trigger input SIO "0" after a reset SIO /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort I direction"0" after a reset N ote) O nly PI2 is Schm itt trigger input. SIO (PI2 only) 1 pin Hi-Z Hi-Z SO0 SCK0 Pin Circuit format 1 pin 2 pins 1 pin Port I Port I

– 13 – CXP912032 Hi-Z Oscillation Hi-Z After a reset PI3/CS2/PO PI4/PCK/OSCI PI5/OSCO Hi-Z PI6/XOUT /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines M PX /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort I data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesIP D ata bus R D (Port I) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort I direction /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port I function selection G eneral-purpose prescaler "0" after a reset "0" after a reset Schm itt trigger inputSIO /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines O SC I O SC O /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port I function selection"0" after a reset G eneral-purpose prescaler /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines M PX /LiteDiagLines /LiteDiagLines IP D ata bus R D (Port I) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort I function selection C lock generator G eneral-purpose prescaler "0" after a reset Pin Circuit format 2 pins 1 pin 1 pin Port I Port I Port I Fig. 1. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP R D (Port I) D ata bus G eneral-purpose prescalerPI4/PC K or PI5 N ote) The circuit form at in Fig. 1 or Fig. 2 can be selected w ith the m ask option. Fig. 2.

– 14 – CXP912032 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL

D iagram show s circuit com position during oscillation.
Feedback resistor is rem oved during stop m ode. Stop signal Hi-Z Osillation After a reset AN1 to AN3 PI7/AN0 EXTAL XTAL /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort J data /LiteDiagLines /LiteDiagLines IP D ata bus R D (Port J) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort J direction /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port J input selection "0" after a reset "0" after a reset Input m ultiplexer A/D converter Standby release Hi-Z PJ0/AN4/KS8 to PJ7/AN11/KS15 "L" level RST /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP A/D converter Input m ultiplexer Hi-Z /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP A/D converter Input m ultiplexer /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port I function selection "0" after a reset D ata bus R D (Port I) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP Schm itt trigger input Pull-up resistorM ask option O P From em ulator (C XP912000 only) Pin Circuit format 2 pins 1 pin 3 pins Port J 1 pin 8 pins Port I

– 15 – CXP912032 *1 AV DD and VDD must be the same voltage. *2 VIN and VOUT must not exceed VDD + 0.3V. *3 Nch transistors of PD and PE output ports are the large current drive transistors. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Supply voltage Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD AV DD AV SS VIN VOUT IOH ∑ IOH IOL IOLC ∑ IOL Topr Tstg PD –0.3 to +7.0 AVss to +7.0*1 –0.3 to +0.3 –0.3 to +7.0*2 –0.3 to +7.0*2 –50 130 –20 to +75 –55 to +150 600 380 500 V V V V V mA mA mA mA mA mW Total for all output pins All pins excluding large current output pins Large current output pins*3 Total for all output pins QFP package LQFP package LFBGA package Item Symbol Rating Unit Remarks Absolute Maximum Ratings (VSS = 0V reference)

– 16 – CXP912032 Analog voltage High level input voltage Low level input voltage Operating temperature Supply voltage 5.5 5.5 5.5 5.5 VDD VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.2VDD 0.8 0.4 +75 V V V V V V V V V V V V V Item Symbol Min. Max. Unit Remarks 2.7 2.7 2.5 2.7 0.7VDD 0.8VDD 2.2 VDD – 0.4 –0.3 –20 AV DD VIH VIHS VIHTS VIHEX VIL VILS VILTS VILEX Topr Guaranteed operation range for high-speed mode (1/2 frequency dividing clock) Guaranteed operation range for low-speed mode (1/16 frequency dividing clock) Guaranteed data hold range during stop mode CMOS Schmitt trigger input*3 TTL Schmitt trigger input*4, *7 EXTAL *5 *2, *6 CMOS Schmitt trigger input*3 TTL Schmitt trigger input*4, *7 EXTAL VDD *1 AV DD and VDD must be the same voltage. *2 PC, PD, PE, PI1, PI3 to PI7, PJ for normal input port *3 CS0, SI0, SCK0, RST, PF0/EC0/INT0, PF1/EC2/INT1, PF2/CS1/NMI/CINT, PF3/SI1/INT2, PF5/SCK1, PG6/RFG0, PG7/RFG1, PH (PH2 and PH3 when CMOS Schmitt trigger input is selected with the mask option), PI0/SI2, PI2/SCK2. 4 PH2 and PH3 (when TTL Schmitt trigger input is selected with the mask option). *5 Specified only during external clock input. *6 When the supply voltage (VDD ) is within the range of 2.7 to 3.6V. *7 When the supply voltage (VDD ) is within the range of 4.5 to 5.5V. Recommended Operating Conditions (VSS = 0V reference)

– 17 – CXP912032 (Ta = –20 to +75°C, VSS = 0V reference)DC Characteristics Item High level output voltage V OH PA to PE, PF6 to PF7, PG0 to PG5, PI0, PI3, PI6, PJ PF4, PF5, PI1, PI2, SO0, SCK0 PA to PC, PF4 to PF7, PG0 to PG5, PI0 to PI3, PI6, PJ, SO0, SCK0, RST * VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 2.7V, IOH = –0.15mA VDD = 2.7V, IOH = –0.5mA VDD = 4.5V, IOH = –4.0mA VDD = 3.0V, IOH = –4.0mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 2.7V, IOL = 1.2mA VDD = 2.7V, IOL = 1.6mA VDD = 4.5V, IOL = 12.0mA VDD = 2.7V, IOL = 5.0mA VDD = 5.5V, VIH = 5.5V VDD = 3.6V, VIH = 3.6V VDD = 5.5V, VIL= 0.4V VDD = 3.6V, VIL= 0.3V VDD = 5.5V, VIL= 0.4V VDD = 3.6V, VIL= 0.3V VDD = 5.5V, VI= 0, 5.5V VDD = 3.6V, VI= 0, 3.6V 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 5V ± 10% 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 3.3V ± 0.3V 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 5V ± 10%, sleep mode 20MHz crystal oscillation (C1 = C2 = 10pF), VDD = 3.3V ± 0.3V, sleep mode VDD = 5.5V, stop mode VDD = 3.6V, stop mode Clock 1MHz 0V for all pins excluding measured pins 4.0 3.5 2.4 2.0 3.6 2.0 0.5 0.3 –0.5 –0.3 –1.5 –0.9 4.5 0.4 0.6 0.3 0.5 1.5 1.0 –40 –20 –400 –200 ±10 ±10 V V V V V V V V V V V V µA µA µA µA µA µA µA µA mA mA mA mA µA µA pF PD, PE EXTAL RST * PA to PJ, AN1 to AN3, CS0, SI0, SO0, SCK0 RST * VDD , VSS Pins other than VDD , VSS , AV DD , AVSS VOL IIHE IILE IILR IIZ IDD *4 IDDS1 *5 IDDS2 C IN Low level output voltage Input current I/O leakage current Supply current* Input capacitance Symbol Pin Conditions Min. Typ. Max. Unit

– 18 – CXP912032 * tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register CLC (address: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") EXTAL tXH tXLtC F tC R 0.4V VD D – 0.4V 1/fc /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines External clock EXTAL XTAL 74H C 04 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C rystal oscillation PF0/EC 0 PF1/EC 2 tEH tELtEF tER 0.2VD D 0.8VD D AC Characteristics (1) Clock timing System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time f C tXH , tXL tCR , tCF tEH , tEL tER , tEF XTAL, EXTAL EXTAL EXTAL PF0/EC0, PF1/EC2 PF0/EC0, PF1/EC2 Item Symbol Pin Conditions Unit Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 Min. tsys + 50* tsys + 100* 200 200 MHz MHz ns ns ns ns ns ns ms ms Max. (Ta = –20 to +75°C, V SS = 0V reference) Fig. 1. Clock timing VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% Fig. 2. Clock applied conditions *1 RST is specified only in evaluation mode. *2 In RST, the input current is specified when pull-up resistor is selected; the leakage current is specified when no resistor is selected. *3 When all output pins are open. *4 When the upper two bits (CPU clock selected) of the clock control register CLC (address: 0002FEh) are set to "00" and the LSI is operated in high-speed mode (1/2 frequency dividing clock). *5 When the clock generator output is not selected at PI6. Fig. 3. Event count clock timing

– 19 – CXP912032 Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode V DD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% tsys + 100 tsys + 100 2tsys + 200 2tsys + 200 16000/fc 16000/fc tsys + 100 tsys + 100 8000/fc – 50 8000/fc – 75 100 100 200 – tsys 200 – tsys tsys + 100 tsys + 100 tsys + 100 tsys + 100 2tsys + 100 2tsys + 125 8000/fc – 50 8000/fc – 75 tsys + 200 tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 250 tsys + 100 tsys + 150 100 Note 1)tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register CLC (address: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2)The load condition for the SCK output mode, SO output delay time is 150pF when VDD = 5.0V ± 10% and 100pF when VDD = 3.0V ± 10%. (2) Serial interface (CH0, CH1, CH2) (Ta = –20 to +75°C, VSS = 0V reference) Item CS ﬂ ﬁ SCK delay time CS › ﬁ SCK float delay time CS ﬂ ﬁ SO delay time CS › ﬁ SO float delay time CS High level width SCK cycle time SCK High, Low level width SI input setup time (for SCK ›) SI input hold time (for SCK ›) SCK ﬂ ﬁ SO delay time Minimum interval time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH , tKL tSIK tKSI tKSO tINT SCK0, SCK1, SCK2 SO0, SO1, SO2 SO0, SO1, SO2 CS0, CS1, CS2 SCK0, SCK1, SCK2 SCK0, SCK1, SCK2 SCK0, SCK1, SCK2 SI0, SI1, SI2 SI0, SI1, SI2 SO0, SO1, SO2 SCK0, SCK1, SCK2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol Pin Min Max. UnitConditions

– 20 – CXP912032 Fig. 4. Serial interface CH0, CH1, CH2 timing tKSI C S0 C S1 C S2 SC K0 SC K1 SC K2 0.2VD D 0.8VD D tW H C S tD C SK tD C SKF 0.8VD D 0.2VD D tKC Y tKL tKH 0.8VD D 0.2VD D SI0 SI1 SI2 tSIK tD C SO tKSO tD C SO F 0.8VD D 0.2VD D SO 0 SO 1 SO 2 SC K0 SC K1 SC K2 0.8VD D tIN T Input data O utput data

– 21 – CXP912032 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = AVDD = AVREF = 3.0 to 5.5V, VSS = AVSS = 0V reference) Analog input Linearity error VFTVZT 00h 01h FEh FFh Digital conversion value Ta = 25°C Operation mode Sleep mode Stop mode VDD = AVDD = 5.0V VDD = AVDD = 3.0V VDD = AVDD = 5.0V VDD = AVDD = 3.0V VDD = AVDD = 5.0V VDD = AVDD = 3.0V VDD = 5.5V VDD = 3.6V VDD = 5.5V VDD = 3.6V –10 –10 4935 2955 200 tsys 14tsys 0.9AVDD 4975 2985 0.65 0.45 ±15 ±15 5015 3015 AV DD AV REF 1.2 0.8 Bits LSB mV mV µs µs V V mA µA Item Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Reference input voltage Analog input voltage AV REF current VZT*1 VFT*2 tCONV tSAMP VREF VIAN IREF IREFS AV REF AN0 to AN11 AV REF Symbol Pin Min. Typ. Max. UnitConditions *1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. *2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. Note) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register CLC (address: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Fig. 5. Definition of A/D converter terms

– 22 – CXP912032 External interruption High, Low level width Reset input Low level width NMI INT0 INT1 INT2 PD0 to PD7 RST tsys* µs µs Item Symbol Pin Conditions Min. Max. Unit tIH, tIL tRSL (4) Interruption and reset input(Ta = –20 to +75°C, VDD = 2.7 to 5.5V, VSS = 0V reference) 0.2VD D 0.8VD D tIH tIL N M I IN T0 IN T1 IN T2 PD 0 to PD 7 PJ0 to PJ7 (D uring standby release input) (Falling edge) Fig. 6. Interruption input timing tR SL 0.2VD D R ST Fig. 7. RST input timing * tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register CLC (address: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

– 23 – CXP912032 External clock input PCK tR = tF = 6ns External clock input PCK tR = tF = 6ns VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% (5) General-purpose prescaler Item fPCK tWH , tWL tR , tF tPLH tPHL tTLH tTHL PCK PCK PCK PO PO MHz ns ns ns ns ns ns Symbol Pin Min. 130 100 Typ. 200 200 130 220 100 150 100 280 Max. UnitConditions External clock input frequency External clock input pulse width External clock input rise time, fall time Prescaler output delay time (for PCK ›) Prescaler output rise time, fall time Note) PO pin load condition: 50pF PC K PO 1/fPC K tW H tF 0.2VD D 0.8VD D tW L 0.5VD D tR 0.2VD D 0.8VD D 0.5VD D tPLH tTLH tTH L tPH L (Ta = –20 to +75°C, Vss = 0V reference) Fig. 8. General-purpose prescaler timing

– 24 – CXP912032 VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% (6) Other (Ta = –20 to +75°C, VSS = 0V reference) Item tCFH , tCFL tDFH , tDFL tDPW tDPR tRFH , tRFL tEIH, tEIL tPIH, tPIL tPMW tPMR tTLH tTHL CFG DFG DPG DPG RFG0 RFG1 EXI0 EXI1 PMI PMSK PMSK XOUT When tsys = 2000/fc When the load is 50pF ns ns ns ns ns ns ns ns ns ns Symbol Pin Min. 100 Typ. 100 280 Max. UnitConditions CFG input High, Low level width DFG input High, Low level width DPG minimum pulse width DPG minimum removal time RFG input High, Low level width EXI input High, Low level width PMI input High, Low level width PMSK minimum pulse width PMSK minimum removal time XOUT output rise time, fall time tsys + 200 tsys + 200 1000/fc + 200 1000/fc + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 Note) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register CLC (address: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")

– 25 – CXP912032 Fig. 9. Other timing 0.8VD D C FG tC FH tC FL D FG tD FH tD FL R FG 0 R FG 1 tR FH tR FL 0.8VD D tD PR tD PW tD PR D PG 0.2VD D 0.8VD D 0.2VD D EXI0 EXI1 tEIH tEIL 0.8VD D 0.2VD D 0.8VD D 0.2VD D PM I tPIH tPIL 0.8VD D tPM R tPM W tPM R PM SK 0.8VD D 0.2VD D XO U T 0.8VD D 0.2VD D tTLH tTH L

– 26 – CXP912032 Appendix C 2C 1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL M ain clock C 2C 1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines O SC I O SC O G eneral-purpose prescaler clock M ask option Manufacturer RIVER ELETEC CO., LTD. KINSEKI LTD. Model HC-49/U03 HC-49/U (-S) fc (MHz) 10 10 C 1 (pF) C 2 (pF) C 1 (pF) C 2 (pF) 4 4 4 4 Main clock General-purpose prescaler clock EXTAL system operating voltage* Reset pin pull-up resistor PH2 input circuit PH3 input circuit PI4/PI5 pin circuit 2.7 to 5.5V Non-existent CMOS Schmitt trigger CMOS Schmitt trigger Oscillation circuit 4.5 to 5.5V Existent TTL Schmitt trigger TTL Schmitt trigger Input pin Item Selection Note 1)Use the general-purpose prescaler clock at 12MHz or less. Note 2)Crystals and capacitors should be placed near the LSI and wiring should be as short as possible. Mask option table Fig. 10. Recommended oscillation circuit

– 27 – CXP912032 1/2 frequency dividing m ode 1/4 frequency dividing m ode 1/8 frequency dividing m ode 1/16 frequency dividing m ode Sleep m ode 1/2 frequency dividing m ode 1/4 frequency dividing m ode 1/8 frequency dividing m ode 1/16 frequency dividing m ode Sleep m ode 2 3 4 5 6 VD D – Supply voltage [V] IDD – Supply current [m ID D vs. VD D (fc = 20M H z, Ta = 25°C , Typical) 0 5 10 15 20 fc – System clock [M H z] ID D vs. fC (VD D = 5V, Ta = 25°C , Typical) IDD – Supply current [m 40.00 38.00 36.00 34.00 32.00 30.00 28.00 26.00 24.00 22.00 20.00 18.00 16.00 14.00 12.00 10.00 8.00 6.00 4.00 2.00 0.00 Example of Representative Characteristics

– 28 – CXP912032 Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G 42/C O PPER ALLO Y PAC KAG E STR U C TU R E 23.9 ± 0.4 Q FP-100P-L01 100PIN Q FP (PLASTIC ) 20.0 – 0.1 + 0.4 0.15 – 0.05 + 0.1 15.8 ± 0.4 17.9 ± 0.4 14.0 – 0.1 + 0.4 2.75 – 0.15 + 0.35 A 0.65 M0.13 Q FP100-P-1420 1.7g 100 80 51 0.3 – 0.1 + 0.15 D ETAIL A 0° to 10° 0.8 ± 0.2 (16.3) 0.150.1 – 0.05 + 0.2 SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G

42 ALLO Y

PAC KAG E STR U C TU R ED ETAIL A LQ FP-100P-L01 LQ FP100-P-1414 100PIN LQ FP (PLASTIC ) 16.0 ± 0.2 ∗ 14.0 ± 0.1 75 51 251 0.5 0.18 – 0.03 + 0.08 (0.22) A 1.5 – 0.1 + 0.2 0.127 – 0.02 + 0.05 0.5 ± 0.2 (15.0) 0° to 10° 0.1 ± 0.1 0.5 ± 0.2 100 0.1 N O TE: D im ension “∗” does not include m old protrusion. 0.8g 0.13 M

– 29 – CXP912032 Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E M ASS PAC KAG E STR U C TU R E LFBG A-104P-01 O R G AN IC SU BSTR ATE 0.5g PAC KAG E M ATER IAL BO AR D TR EATM EN T TER M IN AL M ATER IAL C O PPER -C LAP R AM IN ATE SO LD ER 104PIN LFBG A LFBG A104-P-1313 S0.10 1.6 M AX S S0.20 S0.20 13.0 13.0 φ0.15 AS φ0.15 B S PIN 1 IN D EX 1 2 3 4 5 6 7 8 910111213 104 – φ0.40 ± 0.05 φ0.08 M S A B A B 0.8 A B C D E F G H J K L M N 0.8 1.7 1.7 SO LD ER BALL 0.3

Summary

CMOS 16-bit Single Chip Microcomputer

Description

The CXP912032 is a CMOS 16-bit micro-computer integrating on a single chip an A/D converter, serial interface with an incorporated buffer RAM, highprecision timing pattern generation function, pulse cycle measurement circuit, PWM generator, generalpurpose prescaler, vertical sync separation circuit, and a measurement circuit which measures the signals of capstan FG, drum FG/PG, reel FG and other servo systems with high precision, as well as basic configurations like a 16-bit CPU, ROM, RAM, and I/O port.

Source title CXP912032 Datasheet(PDF) - Sony Corporation

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