CXP85112B SONY | Alldatasheet

Document overview

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Technical content

Features

  • Wide-range instruction system (213 instructions) to cover various types of data — 16-bit arithmetic/multiplication and division/boolean bit operation instructions
  • Minimum instruction cycle 1µs at 4MHz operation
  • Incorporated ROM capacity 12K bytes (CXP85112B) 16K bytes (CXP85116B) 20K bytes (CXP85220A) 24K bytes (CXP85224A) 28K bytes (CXP85228A) 32K bytes (CXP85232A)
  • Incorporated RAM capacity 352 bytes (CXP85112B/85116B) 448 bytes (CXP85220A/85224A/85228A/85232A)
  • Peripheral functions — On-screen display function 12
  • 16 dots, 128 types 21 words · 4 Iines (more than 4 Iines possible) Double scan mode compatible, jitter elimination circuit — I2C bus interface — PWM output 14 bits, 1 channel 6 bits, 8 channels — Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO — A/D converter 4 bits, 4channels, successive approximation method (Conversion time of 40µs/4MHz) — HSYNC counter — Power supply frequency counter — Watch dog timer — Serial I/O 8-bit clock synchronization — Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer
  • Interruption 14 factors, 14 vectors, multi-interruption possible
  • Standby mode Sleep
  • Package 64-pin plastic SDIP/QFP
  • Piggyback/evaluation chip CXP85100A, CXP85190 (Custom font compatible) CXP85200A, CXP85290 (Custom font compatible) – 1 – E93Z17B86 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP85112B/85116B CXP85220A/85224A/85228A/85232A 64 pin SDIP (Plastic) 64 pin QFP (Plastic) Structure Silicon gate CMOS IC Purchase of Sony's I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.

– 2 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A O N SC R EEN D ISPLAY SER IAL I/O TIM ER /C O U N TER R EM O C O N FIFO H SYN C C O U N TER AC TIM ER A/D C O N VER TER I2C IN TER FAC E U N IT W ATC H D O G TIM ER

14 BIT PW M 6 BIT PW M 8C H

C LO C K G EN ./ SYSTEM C O N TR O L R AM 352/448 BYTES SPC 700 C PU C O R E PR ESC ALER / TIM E BASE TIM ER PORT A PORT B PORT C PORT D PORT E PORT F VSS VDD MP XTAL EXTAL RST PF0/PWM0 to PF7/PWM7 INTERRUPT CONTROLLER PA0 to PA7 PB0 to PB7 PC 0 to PC 7 PD 0 to PD 7 PE0 to PE5 PE6 to PE7 PF0 to PF7 XLC B R BLK H SYN C VSYN C PD 3/SI PD 2/SO PD 1/SC K PD 7/EC PE7/TO PD 6/R M C PD 4/H SI PD 5/AC I PE2/AN 0 to PE5/AN 3 PF4/SC L0 PF5/SC L1 PF6/SD A0 PF7/SD A1 PE6/PWM PE0/INT0 PE1/INT1 PD0/INT2 G EXLC R O M 12K/16K/20K/24K/28K/32K BYTES Block Diagram

– 3 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A VD D N C VSS M P PF0/PW M 0 PF1/PW M 1 PF2/PW M 2 PF3/PW M 3 BLK R G B VSYN C H SYN C EXLC XLC PE0/IN T0 PE1/IN T1 PE2/AN 0 PE3/AN 1 PE4/AN 2 PE5/AN 3 PE6/PW M PE7/TO R ST EXTAL XTAL PD 0/IN T2 PF4/PW M 4/SC L0 PF5/PW M 5/SC L1 PF6/PW M 6/SD A0 PF7/PW M 7/SD A1 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 PD 7/EC PD 6/R M C PD 5/AC I PD 4/H SI PD 3/SI PD 2/SO PD 1/SC K VSS Note) 1. NC (Pin 63) must be connected to VDD . 2. Vss for both Pins 32 and 62 must be grounded. 3. MP (Pin 61) must be connected to GND. Pin Assignment 1 (Top View) 64 pin SDIP Package

– 4 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A PF3/PW M 3 BLK R G B VSYN C H SYN C EXLC 52616364 62 5354555657585960 PF4/PW M 4/SC L0 PF5/PW M 5/SC L1 PF6/PW M 6/SD A0 PF7/PW M 7/SD A1 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 PD 7/EC 20 21 22 23 24 25 26 27 28 29 30 PA2 PA3 PA4 PA5 PA7 V SS PA6 V DD NC M P PF0/PW M PF2/PW M PF1/PW M PA1 PA0 PD6/RM C PD5/ACI PD4/HSI PD3/SI PD1/SCK V SS PD2/SO PD0/INT2 XTAL EXTAL RST PE6/PW M PE7/TO 31 32 XLC PE0/IN T0 PE1/IN T1 PE2/AN 0 PE3/AN 1 PE4/AN 2 PE5/AN 3 Note) 1. NC (Pin 56) must be connected to VDD . 2. Vss for both Pins 26 and 58 must be grounded. 3. MP (Pin 55) must be connected to GND. Pin Assignment 2 (Top View) 64 pin QFP Package

– 5 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) (Port D) 8-bit I/O port. I/Ocan be set ina a unit of single bits. Capable of driving 12mA sink current. (8 pins) (Port E) 8-bit port. Lower 6 bits are for inputs; upper 2 bits are for outputs. (Port F) 8-bit output port, operating as N-ch open drain output for high current (12mA). Lower 4 bits are medium voltage drive outputs (12V), upper 4bits are 5V drive outputs. (8 pins) 4-bit outputs for CRT display. Horizontal synchronizing signal input for CRT display. Vertical synchronizing signal input for CRT display. Pin Description Symbol PA0 to PA7 PB0 to PB7 PC0 to PC7 PD0/INT2 PD1/SCK PD2/SO PD3/SI PD4/HSI PD5/ACI PD6/RMC PD7/EC PE0/INT0 PE1/INT1 PE2/AN0 to PE5/AN3 PE6/PWM PE7/TO PF0/PWM0 to PF3/PWM3 PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 R, G, B, BLK HSYNC VSYNC I/O I/O I/O I/O/Input I/O/I/O I/O/Output I/O/Input I/O/Input I/O/Input I/O/Input I/O/Input Input/Input Input/Input Output/Output Output/Output Output/Output Output/Output/ I/O Output/Output/ I/O Output Input Input I/O Description External interruption request input. Active at falling edge. Serial clock I/O. Serial data output. Serial data input. HSYNC counter input. Input for power supply frequency counter. Input for remote control reception circuit. External event input for timer/counter. External interruption request inputs. Active at falling edge. (2 pins) Analog inputs for A/D converter. (4 pins) 14-bit PWM output. (CMOS output) Rectangular waveform output for Timer 1. (Duty output 50%) 6-bit PWM outputs. (8 pins) Transfer clock I/Os for I 2C bus interface. Transfer data I/Os for I2C data bus.

– 6 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Symbol EXLC XLC EXTAL XTAL RST MP V DD Vss Input Output Input Output I/O Input Clock oscillation I/Os for CRT display. Oscillation frequency is set using the external L and C. Crystai connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Low-level active, system reset. RST is an I/O, from whlch Low level is output when the built-in power-on reset function is activated at the rise of power on. (Mask option) Microprocessor mode input. For this device, this pin must be grounded. Vcc supply. GND. Both Vss must be grounded. I/O Description

– 7 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A D ata bus R D (Port D ) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesIP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port D direction /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port D data H igh current 12m A Schm itt input SC K only SC K or SO O utput eneble D ata bus R D (Ports A, B, and C ) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesIP /LiteDiagLines /LiteDiagLines Input protection circuit /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines D ata for Ports A, B, and C /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines D irection for Ports A, B, and C D ata bus R D (Port D ) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesIP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort D direction/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort D data H igh current 12m A IN T2, SI, H SI, AC I, R M C , EC Schm itt input Port D 2 pins PD1/SCK PD2/SO Input/Output Circuit Formats for Pins Port A Port B Port C Port D 24 pins 6 pins Hi-Z Hi-Z Hi-Z Pin When resetCircuit format PA0 to PA7 PB0 to PB7 PC0 to PC7 PD0/INT2 PD3/SI PD4/HSI PD5/ACI PD6/RMC PD7/EC

– 8 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP R D (Port E) D ata bus Schm itt input (To interruption circuit) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP Input m ultiplexer To A/D converter R D (Port E) D ata bus /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines TO , PW M /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort selection/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort E data Port E 2 pins 4 pins 2 pins Pin When resetCircuit format PE0/INT0 PE1/INT1 Port E Port E High level Hi-Z Hi-Z PE2/AN0 to PE5/AN3 PE6/PWM PE7/TO SC L, SD A /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort selection/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port F data PW M I2C output enable /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP Schm itt input SC L, SD A (To I2C circuit) To other I2C pins BU S SW PW M /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort selection/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort F data M iddle tension proof 12V H igh current 12m A Port F Port F 4 pins 4 pins PF4/PWM4/ SCL0 PF5/PWM5/ SCL1 PF6/PWM6/ SDA0 PF7/PWM7/ SDA1 Hi-Z Hi-Z PF0/PWM0 to PF3/PWM3

– 9 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A 4 pins 2 pins Pin When resetCircuit format Hi-Z Oscillation terminated BLK R G B EXLC XLC /LiteDiagLines /LiteDiagLines BLK, R , G , B H i-Z → output active by w riting into the output polarity register. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesO utput polarity 2 pins Hi-Z HSYNC VSYNC H SYN C VSYN C /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP Schm itt input /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Input polarity O scillation control /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXLC /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesIP C R T display clock /LiteDiagLines /LiteDiagLines IPXLC /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 2 pins 1 pin RST Oscillation Low level EXTAL XTAL /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL

  • D iagram show s circuit com position during oscillation.
  • Feedback resistor is rem oved during stop. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines From pow er-on reset circuit M ask option Schm itt input Pull-up resistance O P (M ask option) 1 pin MP Hi-Z /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP C PU m ode

– 10 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A *1 VIN and VOUT must not exceed VDD + 0.3V. *2 The high current operation transistor is the N-ch transistor of PD and PF0 to PF3. Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Supply voltage Input voltage Output voltage Medium voltage drive output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD VIN VOUT VOUTP IOH ∑ IOH IOL IOLC ∑ IOL Topr Tstg PD –0.3 to +7.0 –0.3 to +7.0*1 –0.3 to +7.0*1 –0.3 to +15.0 –50 130 –20 to +75 –55 to +150 1000 600 V V V V mA mA mA mA mA mW mW Pins PF0 to PF3 Total for all output pins Excludes high current outputs High current outputs* Total for all output pins SDIP QFP Symbol Rating Unit Remarks Absolute Maximum Ratings (Vss = 0V reference) Supply voltage High level input voltage Low level input voltage Operating temperature 5.5 5.5 5.5 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 V V V V V V V V V Item Symbol Min. Max. Unit Remarks 4.5 3.5 2.5 0.7VDD 0.8VDD VDD – 0.4 –0.3 –20 VIH VIHS VIHEX VIL VILS VILEX Topr Guaranteed operation range Low-speed mode guaranteed operation range*1 Guaranteed data hold range during stop Includes I2C Schmitt input*2 CMOS Schmitt input*3 EXTAL *4 Includes I2C Schmitt input*2 CMOS Schmitt input*3 EXTAL *4 VDD *1 Specifies only for 1/16 frequency demultiplication mode and sleep mode. *2 Value for each pin of normal input ports (PA, PB, PC, PE2 to PE5), PF4 to PF7, and MP. *3 Value of the following pins: PD0/lNT2, PD1/SCK, PD2, PD3/Sl, PD4/HSl, PD5/ACI, PD6/RMC, PD7/EC, PE0/INT0, PE1/lNT1, HSYNC, VSYNC, RST. *4 Specifies only during external clock input. Recommended Operating Conditions (Vss = 0V reference) Item

– 11 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 3.0mA VDD = 4.5V, IOL = 4.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL= 0.4V VDD = 4.5V, IOL = 12.0mA High level output current Low level output current Input current I/O leakage current Open drain output leakage current (N-ch Tr in off state) Impedance connected to I 2C bus switch (outputTr in off state) Power supply current Input capacity 4.0 3.5 0.5 µA pF 120 mA mA µA µA Ω 0.4 0.6 1.5 0.4 0.6 –40 –400 ±10 V V V V V µA µA µA µA 0.5 –0.5 –1.5 V V PA to PD, PE6, PE7, R, G, B, BLK PA to PD, PE6, PE7, R, G, B, BLK, PF0 to PF3, RST* PD, PF0 to PF3 PF4 to PF7 (SCL0, SCL1, SDA0, SDA1) EXTAL RST * PA to PE, HSYNC, VSYNC, R, G, B, BLK, RST* 2, MP PF0 to PF3 PF4 to PF7 SCL0: SCL1 SDA0: SDA1 VDD = 5.5V, VIL= 0.4V VDD = 5.5V VI= 0, 5.5V VDD = 5.5V, VOH = 12.0V VDD = 5.5V, VOH = 5.5V VDD = 4.5V VSCL0 = VSCL1 = 2.25V VSDA0 = VSDA1 = 2.25V VDD *3 Operation mode*3 (1/2 frequency demultiplier clock) 4MHz crystal oscillation 1 = C2 = 22pF) All outputs open Stop mode*4 Sleep mode Pins other than VDD and Vss Clock 1MHz 0V for all pins excluding Item Symbol Pins Conditions Min. Typ. Max. Unit VOH VOL IIZ ILOH R BS IDD IDDSL IDDST C IN IIHE IIHL IILR

Electrical Characteristics

DC Characteristics (Ta = –20 to +75°C, Vss = 0V reference) *1 RST specifies only when the power-on reset circuit has been selected througn mask option. *2 RST specifies input current when the pull-up resistance has been selected; Ieakage current when no resistance has been selected. *3 Specifies only when the oscillatlon of OSD has been terminated. *4 This device does not enter the stop mode.

– 12 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A AC Characteristics (1) Clock timing *1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH ). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") System clock frequency System clock input pulse width System clock input rise time, fall time Event clock input clock pulse width Event count input clock rise time, fall time fC tXL, tXH tCR , tCF tEH , tEL tER , tEF XTAL EXTAL EXTAL EXTAL EC EC MHz ns ns ns ms Item Symbol Pins Conditions Min. Max. Unit Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 4.5 200 3.5 100 tsys + 50*1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Fig. 1. Clock timing EXTAL tXH tXLtC F tC R 0.4V VD D – 0.4V 1/fc Fig. 2. Clock applying condition /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines C rystal oscillation C eram ic oscillation EXTAL XTAL External clock EXTAL XTAL O PENC 1 C 2 Fig. 3. Event count clock timing EC tEH tELtEF tER 0.2VD D 0.8VD D

– 13 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (2) Serial transfer (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item SCK cycle time tKCY SCK Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode 1000 8000/fc 400 4000/fc – 50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns SCK SI SI SO tKH tKL tSIK tKSI tKSO SCK High and Low level widths SI input setup time (for SCK ›) SI input hold time (for SCK ›) SCK fl fi SO delay time Symbol Pins Conditions Min. Max. Unit Note)The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL. Fig. 4. Serial transfer timing 0.2VD D 0.8VD D tKL tKH SO tKC Y tSIK tKSI 0.2VD D 0.8VD D tKSO 0.2VD D 0.8VD D O utput data Input dataSI SC K

– 14 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A External interruption High and Low level widths Reset input Low level width INT0 to INT2 RST 8/fc µs µs Item Symbol Pins ConditionsMin. Max. Unit tIH tIL tRSL Power supply rise time Power supply cut-off time tR tOFF VDD Power-on reset Repetitive power-on reset 0.05 50 ms ms Item Symbol Pins Conditions Min. Max. Unit (3) Interruption, reset input(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) (4) Power on reset Power on reset* (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) 0.2VD D 0.8VD D tIH tIL IN T0 to IN T2 (Falling edge) 0.2V0.2V 4.5VVD D tR tO FF The pow er supply should be raised sm oothly. Fig. 5. Interruption input timing tR SL 0.2VD D R ST Fig. 6. RST input timing Fig. 7. Power-on reset * Specifies only when the power-on reset function has been selected.

– 15 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Resolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage V ZT*1 VFT*2 tCONV tSAMP VIAN AN0 to AN3 Ta = 25°C VDD = 5.0V Vss = 0V –10 4370 160/fc 12/fc 160 4530 320 4690 VDD Bits LSB mV mV µs µs V Item Symbol Pin Condition Min. Typ. Max. Unit (5)A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Linearity error VZT VFT Analog input FH EH Digital conversion value Fig. 8. Definition of A/D converter terms *1 VZT:Value at which the digital conversion value changes from 0H to 1H and vice versa. *2 VFT:Value at which the digital conversion value changes from EH to FH and vice versa. Note)The 4-bit conversion specifies values based on the upper 5 bits of the A/D data register (ADD: Address 00F5H ), compensated into 4-bit data. A program example is shown below: (A/D converter program example) MOV A, ADD ; ACC ‹ conversion data LSR A ; Shift to the right (4 times) LSR A ; LSR A ; LSR A ; ADC A, #00H ; Addition with carry (data increment if AD3 = 1) CMP A, #10H ; BNE ADC_SKIP ; MOV A, #0FH ; ADC_SKIP:

– 16 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (6)I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item SCL clock frequency Bus free time prior to transfer start Transfer start hold time Clock Low level width Clock High level width Setup time during repetitive transfer Data hold time Data setup time SDA, SCL rise time SDA, SCL fall time Transfer end setup time f SLC tBUF tHD; STA tLOW tHIGH tSU; STA tHD; DAT tSU; DAT tR tF tSU; STO SCL SDA, SCL SDA, SCL SCL SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL SDA, SCL 4.7 4.0 4.7 4.0 4.7 250 4.7 100 300 kHz µs µs µs µs µs µs ns µs ns µs Symbol Pins Conditions Min. Max. Unit *1 The data hold time does not take into consideration SCL rise time (300ns max.). Ensure that the data hold time exceeds 300ns. Fig. 9. I2C bus transfer timing PSt tSU ; STOtSU ; STA tH D ; STA tSU ; D ATtH IG HtH D ; D AT tFtR tLO W tH D ; STA SP tBU F SD A SC L Fig. 10. Recommended circuit example for I2C device I2C deviceI2C device R S R S R S R S R P R P SD A0 (or SD A1) SC L0 (or SC L1)

  • Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
  • Serial resistance (Rs = 300Ω and under) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise caused by CRT flashover.

– 17 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A (7)OSD (On-Screen Display) timing(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item OSD clock frequency HSYNC pulse width VSYNC pulse width HSYNC after-edge rise time/fall time VSYNC after-edge rise time/fall time f OSC tHWD tVWD tHCG tVCG EXLC XLC HSYNC VSYNC HSYNC VSYNC Fig. 12 Fig. 11 Fig. 11 Fig. 11 Fig. 11 1.2 1.0 200 1.0 MHz µs ns µs Symbol Pins Condition UnitMin. Max. Fig. 11. OSC timing 0.8VD D 0.2VD D tH C G tH W D H SYN C w hen Bit 5 of O PO L register (01FBH ) is set to "0" 0.8VD D 0.2VD D tVC G VSYN C w hen Bit 4 of O PO L register (01FBH ) is set to "0" tVW D Fig. 12. LC oscillation circuit example L C 2C 1 EXLC XLC * H indicates 1HSYNC period.

– 18 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A 4.00 4.19 4.00 4.19 4.00 4.19 4.00 4.19 Supplement C 2C 1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL R d/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL R d (i) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 1 C 2 R d XTAL (ii) Manufacturer MURATA MFG CO., LTD. KINSEKI LTD. Model CSA4.00MG CSA4.19MG CST4.00MGW * CST4.19MGW * HC-49/U03 HC-49/U (-S) fc (MHz) 30 30 0 C 1 (pF) C 2 (pF) Rd (Ω ) Circuit example (i) (ii) (i) 18 0 * Indicates types with on-chip grounding capacitance (C1 and C2). RIVER ELETEC CORPORATION Item Content Reset pin pull-up resistance Power-on reset circuit Non-existent Non-existent Existent Existent Mask option table Fig. 13. Recommended Oscillation circuit

– 19 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A Fig. 14. Characteristics curves ID D vs. VD D (fc = 4M H z, Ta = 25°C typical) 0.1 2 3 4 5 6 VD D – Supply voltage [V] IDD – Power supply current [m 1/2 frequency dem ultiplication m ode 1/4 frequency dem ultiplication m ode 1/16 frequency dem ultiplication m ode Sleep m ode fc – System clock [M H z] IDD – Power supply current [m 1/2 frequency dem ultiplication m ode 1/4 frequency dem ultiplication m ode 1/16 frequency dem ultiplication m ode Sleep m ode 0 2 3 4 5 6 O SD oscillation vs. C C alculated curves (reference value by theoretical calculation) 100 0 50 100 13.0M H z 6.5M H z L – Inductasce [µH] C 1, C 2 – C apacitance [pF] ID D vs. fc (VD D = 5V, Ta = 25°C typical) fosc = C = C 1//C 2 2π LC 5.0M H z

– 20 – CXP85112B/85116B, CXP85220A/85224A/85228A/85232A PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS SO N Y C O D E EIAJ C O D E JED EC C O D E SD IP-64P-01

42 ALLO Y

64PIN SD IP (PLASTIC ) SD IP064-P-0750 57.6 – 0.1 + 0.4 64 33 1 32 1.778 19.05 17.1 – 0.1 + 0.3 0° to 15° 0.25 – 0.05 + 0.1 0.5 M IN 4.75 – 0.1 + 0.4 3.0 M IN 0.5 ± 0.1 0.9 ± 0.15 8.6g SO N Y C O D E EIAJ C O D E JED EC C O D E 23.9 ± 0.4 20.0 – 0.1 0.4 – 0.1 + 0.15 14.0 – 0.1 1 19 3351 0.15 – 0.05 + 0.1 2.75 – 0.15 16.3 0.1 – 0.05 + 0.2 0.8 ± 0.2 M0.2 0.15 + 0.4 17.9 0.4 + 0.4 + 0.35 64PIN Q FP(PLASTIC ) Q FP-64P-L01 Q FP064-P-1420 PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER /PALLAD IU M 42/C O PPER ALLO Y PAC KAG E STR U C TU R E PLATIN G 1.5g 1.0 0° to10° Package Outline Unit: mm