CXP84548

Sony Corporation

CMOS 8-bit Single Chip Microcomputer

Manufacturer: Sony Corporation

Document: 27 Pages / 387Kb

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CXP84540 SONY | Alldatasheet

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PDF pages: 27

Technical content

Features

Wide range instruction system (213 instructions) which covers various of data — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
Minimum instruction cycle 143ns at 28MHz operation (4.5 to 5.5V) 200ns at 20kHz operation (3.0 to 5.5V)
Incorporated ROM capacity 40K bytes (CXP84540) 48K bytes (CXP84548)
Incorporated RAM capacity 1472 bytes
Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 1.93µs / at 28MHz, 2.7µs / at 20MHz) — Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes, latch output function, MSB/LSB first selectable), 1 channel 8-bit clock syncronization, 1 channel — Timer 8-bit timer 8-bit timer/counter 19-bit time-base timer 16-bit capture time/counter — PWM output 8 bits, 2 channels
Interruption 14 factors, 14 vectors, multi-interruption possible
Standby mode Sleep/Stop
Package 80-pin plastic QFP/LQFP 80-pin plastic LFLGA
Piggyback/evaluator CXP84500 Structure Silicon gate CMOS IC – 1 – E96528B9X-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP84540/84548 80 pin LQFP (Plastic) 80 pin LFLGA (Plastic) 80 pin QFP (Plastic)

– 2 – CXP84540/84548 8AN 0 to AN 7 PW M 0 PW M 1 C S0 SI0 SO 0 SC K0 SI1 SO 1 SC K1 TO C IN T EC 1 EC 0 A/D C O N VER TER AVss AVREF 8-BIT PW M G EN ER ATO R 0 SER IAL IN TER FAC E U N IT (C H 0) FIFO SER IAL IN TER FAC E U N IT (C H 1) 8-BIT TIM ER /C O U N TER 0 8-BIT TIM ER 1 16-BIT C APTU R E TIM ER /C O U N TER 2 INTERRUPT CONTROLLER INT0 INT1 INT2 INT3 NMI SPC 700 C PU C O R E R O M 40K/48K BYTES C LO C K G EN ER ATO R / SYSTEM C O N TR O L R AM

1472 BYTES

PORT B PORT C PORT D PORT E PORT F PORT G PORT I PH 0 to PH 78 PORT H LAT0 8-BIT PW M G EN ER ATO R 1 Block Diagram

– 3 – CXP84540/84548 Pin Assignment(Top View) 80-pin QFP package 25 26 27 28 29 30 4039383736353431 32 33 70 69 68 67 6566 71727374757677787980 PE1/EC 1 PI4 PI3/IN T3 PI2/IN T2 PI1/IN T1 PI0/IN T0 PE5/TO /PW M 1 PE4/PW M 0 PE3/N M I PE2/C IN T PE0/EC 0 PB7/SO 1 PB6/SI1 PB5/SC K1 PB4/SO 0 PB3/SI0 PB2/SC K0 PB1/C S0 PB0/LAT0 PA7/AN 7 PA6/AN 6 PA5/AN 5 PA4/AN 4 PA3/AN 3 PH3 PH4 PH5 PH6 PH7 RST EXTAL XTAL V SS PE6 PE7 AV SS AV REF PA0/AN0 PA1/AN1 PA2/AN2 PF3 PF4 PF5 PF6 PF7 PD 0 PD 1 PD 2 PD 3 PD 4 PD 5 PD 6 PD 7 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 PH 0 PH 1 PH 2 PF2 PF1 PF0 PG7 PG6 PG5 PG4 NC V DD PG3 PG2 PG1 PG0 PI7 PI6 PI5 Note) NC (Pin 73) is left open. However, this pin is used for the Flash EEPROM incorporated version (CXP845F60).

– 4 – CXP84540/84548 Pin Assignment(Top View) 80-pin LQFP package Note) NC (Pin 73) is left open. PF5 PF6 PF7 PD 0 PD 1 PD 2 PD 3 PD 4 PD 5 PD 6 PD 7 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 PH 0 PI2/IN T2 PI1/IN T1 PI0/IN T0 PE5/TO /PW M 1 PE4/PW M 0 PE3/N M I PE2/C IN T PE1/EC 1 PE0/EC 0 PB7/SO 1 PB6/SI1 PB5/SC K1 PB4/SO 0 PB3/SI0 PB2/SC K0 PB1/C S0 PB0/LAT0 PA7/AN 7 PA6/AN 6 PA5/AN 5 PH1 PH2 PH3 PH4 PH5 PH6 PH7 RST EXTAL XTAL V SS PE6 PE7 AV SS AV REF PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PF4 PF3 PF2 PF1 PF0 PG7 PG6 PG5 PG4 NC V DD PG3 PG2 PG1 PG0 PI7 PI6 PI5 PI4 PI3/INT3 21 22 23 24 25 26 27 28 29 30 4039383736353431 32 33 70 69 68 67 656671727374757677787980 6364 6162

– 5 – CXP84540/84548 Pin Assignment(Top View) 80-pin LFLGA package Note) NC (Pin 71) is left open. 80 78 75 72 69 67 65 62 2 1 79 76 73 70 66 63 61 60 5 3 4 77 74 71 68 64 59 58 7 6 8 57 56 55 9 10 11 54 53 52 12 13 14 51 50 49 15 16 17 48 46 47 18 19 24 28 31 34 37 44 43 45 20 21 23 26 30 33 36 39 41 42 22 25 27 29 32 35 38 40 PF4 PF2 PG 7 PG 4 PG 3 PG 1 PI7 PI4 PF5PF6 PF3 PF0 PG 5 VD D PG 0 PI5 PI3 PI2 PF7PD 1 PD 0 PF1 PG 6 N C PG 2 PI6 PI1 PI0 PD 2PD 3 PD 4 PE5 PE4 PE3 PD 6PD 5 PD 7 PE2 PE1 PE0 PC 1PC 0 PC 2 PB7 PB6 PB5 PC 4PC 3 PC 5 PB4 PB2 PB3 PC 7PC 6 PH 4 R ST VSS AVSS PA1 PB0 PA7 PB1 PH 1PH 0 PH 3 PH 6 XTAL PE7 PA0 PA3 PA5 PA6 PH 2 PH 5 PH 7 EXTAL PE6 AVR EF PA2 PA4

– 6 – CXP84540/84548 Pin Description Symbol I/O Description I/O/Analog input PA0/AN0 to PA7/AN7 (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the pull-up resistance can be set through the software in a unit of 4 bits. (8 pins) Analog inputs to A/D converter. (8 pins) I/OPC0 to PC7 (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Can drive 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) I/OPD0 to PD7 (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull- up resistor can be set through the software in a unit of 4 bits. (8 pins) I/OPF0 to PF7 (Port F) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Input/Input Input/Input Input/Input Input/Input Output/Output Output/Output/ Output Output Output PE0/EC0 PE1/EC1 PE2/CINT PE3/NMI PE4/PWM0 PE5/TO/ PWM1 PE6 PE7 (Port E) 8-bit port. Lower 4 bits are for inputs; upper 4 bits are for outputs. (8 pins) External event inputs for timer/counter. (2 pins) Capture trigger input. Non-maskable interruption request input. 8-bit PWM0 output. Rectangular wave output for 16-bit timer/ counter and 8-bit PWM1 output. I/O/Output I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output PB0/LAT0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Latch output for serial interface (CH0). Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1).

– 7 – CXP84540/84548 Symbol I/O Description I/OPG0 to PG7 (Port G) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull- up resistor can be set through the software in a unit of 4 bits. (8 pins) I/OPH0 to PH7 (Port H) 8-bit I/O port. I/O and standby release input function can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) I/O/Input PI0/INT0 to PI3/INT3 I/OPI4 to PI7 Input Crystal connectors for system clock oscillation. When the clock is supplied externally, input it to EXTAL; opposite phase clock should be input to XTAL. EXTAL OutputXTAL I/O System reset for active at Low level. This pin is I/O pin, and outputs Low level at the power on with the power-on reset function executed. (Mask option) RST No connected. Leave this pin open. However, this is used for the Flash EEPROM incorporated version (CXP845F60). NC Input Reference voltage input for A/D converter.AV REF A/D converter GND.AVss Positive power supply.VDD GNDVss (Port I) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) External interruption request inputs. (4 pins)

– 8 – CXP84540/84548 D ata bus R D (Port B) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port B direction IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor "0" w hen reset "0" w hen reset LAT0 Latch output enable ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 300kΩ (VD D = 3.0 to 3.6V) D ata bus R D (Port B) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B direction IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor "0" w hen reset "0" w hen reset Schm itt input C S0 SI0 SI1 ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 300kΩ (VD D = 3.0 to 3.6V) Port B 8 pins Hi-Z Hi-Z When reset PA0/AN0 to PA7/AN7 PB0/LAT0 Port B 1 pin 3 pins Hi-Z PB1/CS0 PB3/SI0 PB6/SI1 D ata bus R D (Port A) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port A direction IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port A data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort A function selection Input protection circuit "0" w hen reset "0" w hen reset "0" w hen reset Input m ultiplexer A/D converter ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 300kΩ (VD D = 3.0 to 3.6V) Input/Output Circuit Formats for Pins Port A Pin Circuit format

– 9 – CXP84540/84548 D ata bus R D (Port B) /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B function selection "0" w hen reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B direction "0" w hen reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor Serial data output enable SO ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 300kΩ (VD D = 3.0 to 3.6V) D ata bus R D (Port C ) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort C direction IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort C data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor "0" w hen reset "0" w hen reset ∗1 Large current drive (12m A: VD D = 4.5 to 5.5V) ( 5m A: VD D = 3.0 to 3.6V) ∗2 Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 300kΩ (VD D = 3.0 to 3.6V) Port B 2 pins Hi-Z Hi-Z PB2/SCK0 PB5/SCK1 PB4/SO0 PB7/SO1 Port C 2 pins 8 pins Hi-Z PC0 to PC7 D ata bus R D (Port B) /LiteDiagLines /LiteDiagLines IP/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port B function selection "0" w hen reset Schm itt input SC K0, SC K1 in /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B direction "0" w hen reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor "0" w hen reset SC K O U T Serial clock output enable ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 300kΩ (VD D = 3.0 to 3.6V) Port B When resetPin Circuit format

– 10 – CXP84540/84548 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port E data "1" w hen reset Port E function selection (low er) "00" w hen reset TO Port E function selection (upper) PW M 1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines M PX Internal reset signal TO output enable ∗ Pull-up transistor approx. 150kΩ (VD D = 4.5 to 5.5V) approx. 400kΩ (VD D = 3.0 to 3.6V) High level with resistor of pull-up transistor ON for reset 4 pins 1 pin PE0/EC0 PE1/EC1 PE2/CINT PE3/NMI PE4/PWM0 PE5/TO/ PWM1 1 pin Low level PE6, PE7 2 pins D ata bus R D (Port E) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort E data "0" w hen reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesIP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Schm itt input R D (Port E) D ata bus EC 0, EC 1 C IN T, N M I D ata bus /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port E function selection PW M 0 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort E data "0" w hen reset "1" w hen reset R D (Port E) Port E Port E Port E Port E Hi-Z High level ( ) When resetPin Circuit format

– 11 – CXP84540/84548 28 pins PD0 to PD7 PF0 to PF7 PG0 to PG7 PI4 to PI7 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPorts D , F, G , I data "0" w hen reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPorts D , F, G , I direction /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor "0" w hen reset R D D ata bus ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 300kΩ (VD D = 3.0 to 3.6V) Port I 8 pins Hi-Z PH0 to PH7 D ata bus R D (Port H ) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort H direction IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort H data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor "0" w hen reset "0" w hen reset Standby release /LiteDiagLines /LiteDiagLines Edge detection ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 300kΩ (VD D = 3.0 to 3.6V) Port H 4 pins Hi-Z PI0/INT0 to PI3/INT3 Port D Port F Port G Port I Hi-Z D ata bus /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort I data "0" w hen reset ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 300kΩ (VD D = 3.0 to 3.6V) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort I direction /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPull-up resistor "0" w hen reset IN T0 IN T1 IN T2 IN T3 R D Schm itt input When resetPin Circuit format

– 12 – CXP84540/84548 2 pins Oscillation EXTAL XTAL 1 pin RST Low level /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL

D iagram show s the circuit com position during oscillation.
Feedback resistor is rem oved during stop m ode and XTAL becom es H igh level./LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines Schm itt input Pull-up resistor M ask option /LiteDiagLines /LiteDiagLines IP From pow er-on reset circuit (M ask option) O P When resetPin Circuit format

– 13 – CXP84540/84548 *1 VIN and VOUT must not exceed VDD + 0.3V. *2 The large current drive transistor is the N-ch transistor of Port C (PC) Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Input voltage Output voltage High level output current High level total output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD AV SS VIN VOUT IOH ∑ IOH IOL IOLC ∑ IOL Topr Tstg PD Supply voltage Low level output current –0.3 to +7.0 –0.3 to +0.3 –0.3 to +7.0*1 –0.3 to +7.0*1 –50 100 –20 to +75 –55 to +150 600 380 500 V V V V mA mA mA mA mA mW mW mW Output (value per pin) Total of all output pins Pins excluding large current outputs (value per pin) Large current outputs (value per pin* Total of all output pins QFP-80P-L01 LQFP-80P-L01 LFLGA-80P-02 Item Symbol Ratings Unit Remarks Absolute Maximum Ratings (Vss = 0V reference) High level input voltage Low level input voltage Operating temperature Supply voltage*1 5.5 5.5 5.5 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.1VDD +75 V V V V V V V Item Symbol Min. Max. Unit Remarks 4.5 (3.0) 3.5 (2.7) 2.0 0.7VDD 0.8VDD 0.9VDD –0.3 –20 VIH VIHS VIHEX VIL VILS VILEX Topr Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks Guaranteed operation range for 1/16 frequency dividing clock and sleep mode Guaranteed data hold range during stop mode Hysteresis input*3 EXTAL *4 Hysteresis input*3 EXTAL *4 VDD *1 Specifies values in parenthesis for 1 to 20MHz system clock operation. *2 Normal input ports (PA, PB0, PB4, PB7, PC, PE0 to PE3, PD, PF to PH, PI4 to PI7) *3 RST, CINT, CS0, SCK0, SCK1, EC0, EC1, SI0, SI1, NMI, INT0, INT1, INT2, INT3 *4 Specifies only during external clock input. Recommended Operating Conditions (Vss = 0V reference)

– 14 – CXP84540/84548

Electrical Characteristics

DC Characteristics(VDD 4.5 to 5.5V) (Ta = –20 to +75°C, Vss = 0V reference) VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL= 0.4V VDD = 5.5V, VIL= 4.0V High level output voltage 4.0 3.5 0.1 –0.1 –1.5 –2.78 V V V V V µA µA µA µA µA µA PC PA to PD, PE4 to PE7, PF to PI, RST (only VOL )*1 EXTAL RST *2 PA to PD*3 PF to PI*3 Item Symbol Pins Conditions Min. Clock 1MHz 0V for no-measured pins VDD IDD1 IIZ IDD2 IDDS1 IDDS2 IDDS3 C IN VOH VOL IIHE IILE IILR IIL Low level output voltage Input current Typ. 0.4 0.6 1.5 –25 –400 –50 ±10 Max. Unit *1 Specifies RST pin when the power-on reset circuit is selected with mask option. *2 For RST pin, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. *3 For PA to PD and PF to PI pins, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. *4 When all pins are open. VDD = 5.5V, 28MHz crystal oscillation (C1 = C2 = 5pF) Sleep mode Supply current *4 Input capacity VDD = 4.5V, VIL= 4.0V VDD = 5.5V, VI= 0, 5.5V 1/2 frequency dividing clock operation I/O leakage current PA to PD*3 PF to PI*3 PE0 to PE3, RST *2 4.0 mA mA µA pF VDD = 5.5V, 28MHz crystal oscillation (C1 = C2 = 5pF) Stop mode VDD = 5.5V, termination of 28MHz crystal oscillation PA to PD, PE0 to PE3, PF to PI, EXTAL, RST

– 15 – CXP84540/84548 DC Characteristics(VDD = 3.0 to 3.6V) (Ta = –20 to +75°C, VSS = 0V reference) VDD = 3.0V, IOH = –0.15mA VDD = 3.0V, IOH = –0.5mA VDD = 3.0V, IOL = 1.2mA VDD = 3.0V, IOL = 1.6mA VDD = 3.0V, IOL = 5mA VDD = 3.6V, VIH = 3.6V VDD = 3.6V, VIL= 0.3V VDD = 3.6V, VIL= 2.7V High level output voltage 2.7 2.3 0.05 –0.05 –0.7 –1.0 V V V V V µA µA µA µA µA µA PC PA to PD, PE4 to PE7, PF to PI, RST (only VOL )*1 EXTAL RST *2 PA to PD*3 PF to PI*3 VDD IDD1 IIZ IDD2 IDDS1 IDDS2 IDDS3 VOH VOL IIHE IILE IILR IIL Low level output voltage Input current 0.3 0.5 1.0 –15 –200 –30 VDD = 3.6V, 20MHz crystal oscillation (C1 = C2 = 10pF) Sleep mode Supply current*4 VDD = 3.0V, VIL= 2.7V VDD = 3.6V, VI= 0, 3.6V 1/2 frequency dividing clock operation I/O leakage current PA to PD*3 PF to PI*3 PE0 to PE3, RST *2 13.5 1.2 4.0 mA mA µA VDD = 3.6V, 20MHz crystal oscillation (C1 = C2 = 10pF) Stop mode VDD = 3.6V, termination of 20MHz crystal oscillation *1 Specifies RST pin when the power-on reset circuit is selected with mask option. *2 For RST pin, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. *3 For PA to PD and PF to PI pins, specifies the input current when pull-up resistance is selected; leakage current when no resistance is selected. *4 When all pins are open. Item Symbol Pins Conditions Min. Typ. Max. Unit

– 16 – CXP84540/84548 *1 tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") EXTAL tXH tXLtC F tC R 0.4V VD D – 0.4V 1/fc /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines C rystal oscillation C eram ic oscillation EXTAL XTAL External clock EXTAL XTAL 74H C 04C 1 C 2 AC Characteristics (1) Clock timing System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time fC tXL, tXH tCR , tCF tEH , tEL tER , tEF XTAL EXTAL EXTAL EXTAL EC0 EC1 EC0 EC1 MHz ns ns ns ns Item Symbol Pin Conditions Min. Unit Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 15.6 tsys + 50*1 Typ. Max. 100 (Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) Fig. 2. Clock applied conditions Fig. 1. Clock timing tEH tELtEF tER 0.2VD D 0.8VD D tTH tTLtTF tTR EC 0 EC 1 Fig. 3. Event count clock timing VDD = 4.5 to 5.5V VDD = 4.5 to 5.5V

– 17 – CXP84540/84548 Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Note 1)tsys indicates three values according to the ccontents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2)The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. (2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item CS0 ﬂ ﬁ SCK0 delay time CS0 › ﬁ SCK0 float delay time CS0 ﬂ ﬁ SO0 delay time CS0 › ﬁ SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level widths SI0 input setup time (for SCK0 ›) SI0 input hold time (for SCK0 ›) SCK0 ﬂ ﬁ SO0 delay time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO tLADLY tLAPLS SCK0 SCK0 SO0 SO0 CS0 SCK0 SCK0 SI0 SI0 SO0 LAT0 LAT0 Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Latch output mode (SCK0 = output mode) Latch output mode (SCK0 = output mode) ns ns ns ns ns Symbol Pin Min. 1.5tsys + 100 1.5tsys + 100 1.5tsys + 100 1.5tsys + 100 tsys + 150 2tsys + 200 8000/fc tsys + 90 4000/fc – 25 100 tsys + 100 tKCY tKCY – 10 ns ns ns ns ns ns ns ns ns ns ns ns tsys + 100 tKCY + 50 tKCY + 50 Max. UnitCondition SCK0 ﬂ ﬁ LAT0 output delay time LAT0 data pulse width

– 18 – CXP84540/84548 Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Note 1)tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2)The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, Vss = 0V reference) CS0 ﬂ ﬁ SCK0 delay time CS0 › ﬁ SCK0 float delay time CS0 ﬂ ﬁ SO0 delay time CS0 › ﬁ SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level widths SI0 input setup time (for SCK0 ›) SI0 input hold time (for SCK0 ›) SCK0 ﬂ ﬁ SO0 delay time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO tLADLY tLAPLS SCK0 SCK0 SO0 SO0 CS0 SCK0 SCK0 SI0 SI0 SO0 LAT0 LAT0 Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Latch output mode (SCK0 = output mode) Latch output mode (SCK0 = output mode) ns ns ns ns ns 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 1.5tsys + 200 tsys + 200 2tsys + 200 8000/fc tsys + 80 4000/fc – 50 150 tsys + 120 tKCY tKCY – 10 ns ns ns ns ns ns ns ns ns ns ns ns tsys + 200 tKCY + 100 tKCY + 100 SCK0 ﬂ ﬁ LAT0 output delay time LAT0 data pulse width Item Symbol Pin Min. Max. UnitCondition

– 19 – CXP84540/84548 Fig. 4. Serial transfer CH0 timing SC K0 0.2VD D 0.8VD D tW H C S tD C SK tD C SKF 0.8VD D 0.2VD D 0.8VD D tKC Y tKL tKH 0.8VD D 0.2VD D SI0 tSIK Input data tD C SO tKSO tD C SO F O utput data 0.8VD D 0.2VD D SO 0 C S0 tKSI tLAPLS LAT0 tLAD LY 0.8VD D 0.8VD D0.8VD D

– 20 – CXP84540/84548 (3) Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) Item SCK1 cycle time tKCY SCK1 Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode 500 8000/fc 200 4000/fc – 25 100 100 100 ns ns ns ns ns ns ns ns ns ns SCK1 SI1 SI1 SO1 tKH tKL tSIK tKSI tKSO SCK1 High, Low level widths SI1 input set-up time (for SCK1 ›) SI1 input hold time (for SCK1 ›) SCK1 ﬂ ﬁ SO1 delay time Symbol Pin Condition Min. Max. Unit Note)The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, VSS = 0V reference) Item SCK1 cycle time tKCY SCK1 Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode 700 8000/fc 300 4000/fc – 50 150 150 150 ns ns ns ns ns ns ns ns ns ns SCK1 SI1 SI1 SO1 tKH tKL tSIK tKSI tKSO SCK1 High, Low level widths SI1 input set-up time (for SCK1 ›) SI1 input hold time (for SCK1 ›) SCK1 ﬂ ﬁ SO1 delay time Symbol Pin Condition Min. Max. Unit Note)The load condition for the SCK1 output mode, SO1 output delay time is 50pF.

– 21 – CXP84540/84548 Fig. 5. Serial transfer CH1 timing 0.2VD D 0.8VD D tKL tKH SO 1 tKC Y tSIK tKSI 0.2VD D 0.8VD D tKSO 0.2VD D 0.8VD D O utput data Input dataSI1 SC K1

– 22 – CXP84540/84548 Conversion time Sampling time Reference input voltage Analog input voltage tCONV tSAMP VREF VIAN VZT*1 VFT*2 IREF AV REF AN0 to AN7 Ta = 25°C VDD = AVREF = 5.0V VSS = AVSS = 0V Operation mode Sleep mode Stop mode Linearity error Zero transition voltage Full-scale transition voltage Resolution AV REF current AV REF IREFS µs µs V V V DD AV REF 1.0 mA 10 µA 0.6 27/fADC *3 6/fADC *3 VDD – 0.5 Item Symbol Pin Condition Min. Typ. Max. Unit Bits (4) A/D converter characteristics(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to VDD , Vss = AVSS = 0V reference) LSB 70 mV 5030 4970 –10 4910 mV Conversion time Sampling time Reference input voltage Analog input voltage tCONV tSAMP VREF VIAN VZT*1 VFT*2 IREF AV REF AN0 to AN7 Ta = 25°C VDD = AVREF = 3.3V VSS = AVSS = 0V Operation mode Sleep mode Stop mode Linearity error Zero transition voltage Full-scale transition voltage Resolution AV REF current AV REF IREFS µs µs V V V DD AV REF 0.7 mA 5 µA 0.4 27/fADC *3 6/fADC *3 VDD – 0.3 Item Symbol Pin Condition Min. Typ. Max. Unit Bits (Ta = –20 to +75°C, VDD = 3.0 to 3.6V, AVREF = 2.7 to VDD , Vss = AVSS = 0V reference) LSB 70 mV 3345 6.5 3280.5 –10 3216 mV Fig. 6. Definition of A/D converter terms Analog input Linearity error VFTVZT 00h 01h FEh FFh Digital conversion value *1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. *2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. *3 fADC indicates the values below due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9h). fADC = fc (CKS = "0"), fc/2 (CKS = "1") However, the selection for fADC = fc (CKS = "0") is limited in the clock range of fc = 1 to 14MHz (VDD 4.5 to 5.5V) and fc = 1 to 10MHz (VDD = 3.0 to 4.5V).

– 23 – CXP84540/84548 External interruption High, Low level widths Reset input Low level width INT0 INT1 INT2 INT3 NMI RST 32/fc µs µs Item Symbol Pin Condition Min. Max. Unit tIH tIL tRSL (4) Interruption, reset input(Ta = –20 to +75°C, VDD = 3.0 to 5.5V, Vss = 0V reference) 0.2VD D 0.8VD D tIH tIL IN T0 IN T1 IN T2 IN T3 N M I (Specifies N M I only for the falling edge.) tIL tIH 0.2VD D 0.8VD D Fig 7. Interruption input timing tR SL 0.2VD D R ST Fig. 8. RST input timing Power supply rise time Power supply cut-off time VDD 0.05 50 ms ms Item Symbol Pin Condition Min. Max. Unit tR tOFF Power-on reset Repetitive power-on reset (5) Power-on reset*1 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference) *1 Specifies only when the power-on reset function is selected. Power-on reset function can be selected only for the supply voltage range of 4.5 to 5.5V. VD D tR tO FF 0.2V0.2V 4.5V Take care w hen turning the pow er on. Fig. 9. Power-on reset

– 24 – CXP84540/84548 Appendix C 1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 2 R d/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL (i) M ain clock /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 1 C 2 R d (ii) M ain clock Models with an asterisk (*) have the built-in ground capacitance (C1, C2). Manufacturer MURATA MFG CO., LTD. TDK CORPORATION. KINSEKI LTD. Model CSA8.00MTZ CSA10.0MTZ CSA12.00MTZ CST8.00MTW * CST10.0MT * CST12.0MTW * CSA16.00MXZ040 CST16.00MXZ0C1 * CSA20.00MXZ040 CSA24.00MXZ040 CSA28.00MXZ040 CCR20.0MC6 * CCR24.0MC6 * HC49/U-S CX-11F fc (MHz) 8.00 10.00 12.00 8.00 10.00 12.00 16.00 16.00 20.00 24.00 28.00 20.00 24.00 28.00 28.00 OPEN OPEN 220 220 C 1 (pF) C 2 (pF) Rd (Ω ) Circuit example (i) (ii) (i) (ii) (i) (ii) (i) *1 "Existent" for power-on reset circuit cannot be selected when the supply voltage VDD of 3.0 to 4.5V. Item Contents Reset pin pull-up resistor Power-on reset circuit *1 Non-existent Non-existent Existent Existent Mask option table Fig. 10. SPC700 Series recommended oscillation circuit

– 25 – CXP84540/84548 Characteristics Curves (100µA) 3 4 5 6 0.1 5.0 1.0 VD D – Supply voltage [V] IDD – Supply current [m ID D vs. VD D (fc = 28M H z, Ta = 25°C , Typical) 0.05 (50µA) 0.01 (10µA) 0.5 10.0 20.0 1/16 dividing m ode 1/4 dividing m ode Sleep m ode Stop m ode 1/2 dividing m ode 1/4 dividing m ode 1/16 dividing m ode Sleep m ode fc – System clock [M H z] IDD – Supply current [m ID D vs. fc (VD D = 5V, Ta = 25°C , Typical) 10 30 1/2 dividing m ode (100µA) 3 4 5 6 0.1 5.0 1.0 VD D – Supply voltage [V] IDD – Supply current [m ID D vs. VD D (fc = 20M H z, Ta = 25°C , Typical) 0.05 (50µA) 0.01 (10µA) 0.5 10.0 20.0 1/16 dividing m ode 1/4 dividing m ode Sleep m ode fc – System clock [M H z] IDD – Supply current [m ID D vs. fc (VD D = 3.3V, Ta = 25°C , Typical) 10 30 1/2 dividing m ode 1/2 dividing m ode 1/4 dividing m ode 1/16 dividing m ode Sleep m ode

– 26 – CXP84540/84548 Package Outline Unit: mm PAC KAG E STR U C TU R E SO N Y C O D E EIAJ C O D E JED EC C O D E Q FP-80P-L01 Q FP080-P-1420 PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G 42/C O PPER ALLO Y 1.6g 23.9 ± 0.4 20.0 – 0.1 + 0.4 64 41 0.8 0.35 – 0.1 + 0.15 14.0 – 0.1 + 0.4 17.9 ± 0.4 16.3 0.1 – 0.05 + 0.2 2.75 – 0.15 + 0.35 0.8 ± 0.2 0.15 – 0.05 + 0.1 80PIN Q FP (PLASTIC ) M0.2 0.15 0° to 10° D ETAIL A A SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G

42 ALLO Y

14.0 ± 0.2 ∗ 12.0 ± 0.1 (0.22) 60 41 0.18 – 0.03 + 0.08 A 1.5 – 0.1 + 0.2 0.127 – 0.02 + 0.05 0.5 ± 0.2 (13.0) 0.1 ± 0.1 0.5 ± 0.2 0° to 10° D ETAIL A 80PIN LQ FP (PLASTIC ) 0.5g LQ FP-80P-L01 LQ FP080-P-1212 0.1 N O TE: D im ension “∗” does not include m old protrusion. 0.13 M 0.5

– 27 – CXP84540/84548 SO NY C O DE EIA J C O DE JEDEC C O DE PA C KA G E M A SS PA C KA G E S TR U C TU R E LFLG A -80P-02 O R G A NIC SU BSTR A TE 0.3g PA C KA G E M A TER IA L TER M INA L TR EA TM ENT TER M INA L M A TER IA L G O LD PLA TING NIC KEL PLA TING 80PIN LFLG A D ETA IL X 1.4M A X S S 0.2 S 0.10XPIN 1 IN D EX 9.0 0.2 AS 9.0 0.2 B S 0.15 P-LFLG A 80-9x9-0.8 1 2 3 4 5 6 7 8 9 10 A B A B C D E F G H J K 80 – φ0.40 ± 0.05 φ0.08 M S A B 0.5 3 – φ0.50 0.5 0.9 0.8 0.3 0.3 0.8 0.9 0.3 0.3 0.4 0.4 0.10M A X Package Outline Unit: mm

Product Information

CXP84548 specifications and overview.

Summary

CMOS 8-bit Single Chip Microcomputer

Description

CMOS 8-bit Single Chip Microcomputer

Source title CXP84548 Datasheet(PDF) - Sony Corporation

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