CXP84100

CXP84100 SONY | Alldatasheet

Document overview

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• PDF pages: 5

Technical content

Features

• Wide-range instruction system (213 instructions) to cover various types of data — 16-bit operation/multiplication and division/ Boolean bit operation instructions
• Minimum instruction cycle 400ns at 10MHz operation 122µs at 32kHz operation
• Applicable EPROM LCC type 27C128, LCC type 27C256 (Maximum 24K bytes are available.)
• Incorporated RAM capacity 624 bytes
• Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 32µs/10MHz) — Serial interface Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock sync type, 1 channel — Timer 8-bit timer 8-bit timer/counter 19-bit time base timer 16-bit capture timer/counter 32kHz timer/counter — Remote control reception circuit 8-bit pulse measurement counter with on-chip 6-stage FIFO — PWM output 14 bits, 1 channel
• Interruption 15 factors, 15 vectors, multi-interruption possible
• Standby mode Sleep/stop
• Package 80-pin ceramic QFP Note)Mask option depends on the type of the CXP84100. Refer to the Products List for details. Structure Silicon gate CMOS IC CMOS 8-bit Single Chip Microcomputer – 1 – E93850A79-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP84100 80 pin PQFP (Ceramic) Piggyback/ evaluator type

– 2 – CXP84100 PF3 PF4 PF5 PF6 PF7 PD 0 PD 1 PD 2 PD 3 PD 4 PD 5 PD 6 PD 7 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 PH 0 PH 1 PH 2 PI4 PI3/IN T3 PI2/IN T2 PI1/IN T1 PI0/IN T0 PE5/TO PE4/PW M PE3/N M I PE2/R M C PE1/EC 1 PE0/EC 0 PB7/SO 1 PB6/SI1 PB5/SC K1 PB4/SO 0 PB3/SI0 PB2/SC K0 PB1/C S0 PB0/C IN T PA7/AN 7 PA6/AN 6 PA5/AN 5 PA4/AN 4 PA3/AN 3 PH3 PH4 PH5 PH6 PH7 RST EXTAL XTAL Vss TX TEX AVss AV REF PA0/AN0 PA1/AN1 PA2/AN2 PF2 PF1 PF0 PG7 PG6 PG5 PG4 NC V DD PG3 PG2 PG1 PG0 PI7 PI6 PI5 A11 N C O E A10 C E D 7 D 6 N C D 0 A7 A12 A15 NC V DD A14 A13 D1 D2 GND NC D3 D4 D5 25 26 27 28 29 30 4039383736353431 32 33 70 69 68 67 6566 71727374757677787980 234 14 15 16 17 18 19 20 3031321 Pin Configuration in Piggyback Mode Note)NC (Pin 73) is always connected to VDD .

– 3 – CXP84100 PF3 PF4 PF5 PF6 PF7 PD 0 PD 1 PD 2 PD 3 PD 4 PD 5 PD 6 PD 7 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 PH 0 PH 1 PH 2 PI4 PI3/IN T3 PI2/IN T2 PI1/IN T1 PI0/IN T0 PE5/TO PE4/PW M PE3/N M I PE2/R M C PE1/EC 1 PE0/EC 0 PB7/SO 1 PB6/SI1 PB5/SC K1 PB4/SO 0 PB3/SI0 PB2/SC K0 PB1/C S0 PB0/C IN T PA7/AN 7 PA6/AN 6 PA5/AN 5 PA4/AN 4 PA3/AN 3 PH3 PH4 PH5 PH6 PH7 RST EXTAL XTAL Vss TX TEX AVss AV REF PA0/AN0 PA1/AN1 PA2/AN2 PF2 PF1 PF0 PG7 PG6 PG5 PG4 NC V DD PG3 PG2 PG1 PG0 PI7 PI6 PI5 A11 N C H ALT A10 E/P I/T M O N A6/D 6 A5/D 5 A4/D 4 A3/D 3 A2/D 2 A1/D 1 A0/D 0 N C R D A7/D7 A12 A15 NC V DD A14 A13 W R SYNC GND NC C2 C1 RST 25 26 27 28 29 30 4039383736353431 32 33 70 69 68 67 6566 71727374757677787980 234 14 15 16 17 18 19 20 3031321 Pin Configuration in Evaluator Mode Note)NC (Pin 73) is always connected to VDD .

– 4 – CXP84100 Products List Address fi Data Input delay time Address fi Data Hold time Item Symbol Pins Min. Max. Unit tACC tIH A0 to A15 D0 to D7 A0 to A15 D0 to D7 0 120 ns ns tAC C tIH 0.8VD D 0.8VD D 0.2VD D 0.2VD D Input data Address dataA0 to A15 D 0 to D 7 Products MaskOption item Existent/Non-existent Non-existent CXP84124 Piggyback/evaluator CXP84100-U01Q 80-pin ceramic PQFP 24K bytes Existent Non-existent CXP84120 80-pin plastic QFP 20K bytes 24K bytes EPROM Read Timing (Ta = –20 to +75°C, Vcc = 4.5 to 5.5V, Vss = 0V reference) Package ROM capacitance Pull-up resistance for reset pin Power-on reset circuit

– 5 – CXP84100 Pin 1 index Pin 1 m arking LC C type EPR O M Pin 1 m arking Piggyback m ode Piggyback/evaluator product Evaluator m ode C PU Probe N ote) N ote) Evaluation cap should be connected to C PU probe. Piggyback m ode/evaluator m ode can be sw itched as show n below . SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E W EIG H T C ER AM IC G O LD PLATIN G

42 ALLO Y

5.7g PQ FP-80C -L01 AQ FP080-C -0000-A 80PIN PQ FP (C ER AM IC ) 18.7 16.3 ± 0.2 9.48 11.66 15.58 ± 0.2 4025 6580 22.3 ± 0.25 4.5 6.0 24.7 1.27 ± 0.13 12.02 14.22 18.12 ± 0.2 0.3 PIN N o. 1 IN D EX IN D EX

9.59 M AX

0.15 – 0.02 + 0.05 3.57 ± 0.36 PIN N o. 1 IN D EX 1.3 ± 0.3 1.0 0.7 65 80 2540 0.6 Package Outline Unit: mm