CXP83620

CXP83620 SONY | Alldatasheet

Document overview

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Technical content

Features

Wide-range instruction system (213 instructions) to cover various types of data. — 16-bit arithmetic/multiplication and division/boolean bit operation instructions
Minimum instruction cycle 400ns at 10MHz operation (4.5 to 5.5V) 1µs at 4MHz operation (2.7 to 5.5V) 122µs at 32kHz operation (2.7 to 5.5V)
Incorporated ROM capacity 20K bytes (CXP83620, 83621) 24K bytes (CXP83624, 83625)
Incorporated RAM capacity 736 bytes (includes LCD display data area and serial interface RAM)
Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation method (Conversion time of 12.4µs/10MHz) — Serial interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel 8-bit clock synchronized type (MSB/LSB first selectable), 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer, Sub timer/counter — LCD controller/driver Maximum 128 segment display possible (during 1/4 duty) 4 common output, 32 segment output Display method static, 1/2, 1/3, 1/4 duty Bias method 1/2, 1/3 bias — Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO
Interruption 14 factors, 14 vectors, multi-interruption possible
Standby mode Sleep/stop
Package 80-pin plastic QFP/LQFP
Piggy/evaluation chip CXP83600 (CXP83620, 83624) CXP83601 (CXP83621, 83625) Structure Silicon gate CMOS IC – 1 – E98134B96 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP83620/83624 CXP83621/83625 CXP83620/83624 80 pin QFP (Plastic) 80 pin LQFP (Plastic) CXP83621/83625 80 pin QFP (Plastic)

– 2 – CXP83620/83624, CXP83621/83625 XTAL A/D C O N VER TER R EM O C O N SER IAL IN TER FAC E U N IT (C H 0) 8-BIT TIM ER /C O U N TER 0 8-BIT TIM ER 1 FIFO BU FFER R AM INTERRUPT CONTROLLER SPC 700 C PU C O R E R O M 20K/24K BYTES PR ESC ALER / TIM E-BASE TIM ER SU B TIM ER / C O U N TER R AM

736 BYTES

8 PC 0 to PC 7

1 PH 0

8 PB0 to PB7

8 PA0 to PA7

8 PD 0 to PD 7

8 PF0 to PF7

2 PI0 to PI1

SER IAL IN TER FAC E U N IT (C H 1) Block Diagram

– 3 – CXP83620/83624, CXP83621/83625 PE3/IN T3 PE4/R M C PE5/TO PE6/AD J PB0 PB1/C S0 PB2/SC K0 PB3/SI0 PB4/SO 0 PB5/SC K1 PB6/SI1 PB7/SO 1 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 PH 0/IN T4 PA0/AN 0 PA1/AN 1 PA2/AN 2 PD 6/SEG 22 PD 5/SEG 21 PD 4/SEG 20 PD 3/SEG 19 PD 2/SEG 18 PD 1/SEG 17 PD 0/SEG 16 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 SEG 0 C O M 3 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 RST EXTAL XTAL V SS V L V LC3 V LC2 V LC1 COM COM COM PE2/INT2 PE1/INT1 PE0/INT0/EC PF7/SEG31 PF6/SEG30 NC PI1/TEX PI0/TX V DD PF5/SEG29 PF4/SEG28 PF3/SEG27 PF2/SEG26 PF1/SEG25 PF0/SEG24 PD7/SEG23 25 26 27 28 29 30 4039383736353431 32 33 70 69 68 67 656671727374757677787980 Note) Do not make any connections to NC (Pin 75). Pin Assignment (Top View) CXP83620/83624 (QFP package)

– 4 – CXP83620/83624, CXP83621/83625 Pin Assignment (Top View) CXP83620/83624 (LQFP package) PE5/TO PE6/AD J PB0 PB1/C S0 PB2/SC K0 PB3/SI0 PB4/SO 0 PB5/SC K1 PB6/SI1 PB7/SO 1 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 PH 0/IN T4 PA0/AN 0 PD 4/SEG 20 PD 3/SEG 19 PD 2/SEG 18 PD 1/SEG 17 PD 0/SEG 16 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 RST EXTAL XTAL V SS V L V LC3 V LC2 V LC1 COM COM COM COM SEG0 PE4/RM C PE3/INT3 PE2/INT2 PE1/INT1 PE0/INT0/EC PF7/SEG31 PF6/SEG30 NC PI1/TEX PI0/TX V DD PF5/SEG29 PF4/SEG28 PF3/SEG27 PF2/SEG26 PF1/SEG25 PF0/SEG24 PD7/SEG23 PD6/SEG22 PD5/SEG21 21 22 23 24 25 26 27 28 29 30 4039383736353431 32 33 70 69 68 67 656671727374757677787980 6364 6162 Note) Do not make any connections to NC (Pin 73).

– 5 – CXP83620/83624, CXP83621/83625 Pin Assignment (Top View) CXP83621/83625 (QFP package) PE5/TO PE6/AD J PB0 PB1/C S0 PB2/SC K0 PB3/SI0 PB4/SO 0 PB5/SC K1 PB6/SI1 PB7/SO 1 PC 0 PC 1 PC 2 PC 3 PC 4 PC 5 PC 6 PC 7 PH 0/IN T4 PA0/AN 0 PD 4/SEG 20 PD 3/SEG 19 PD 2/SEG 18 PD 1/SEG 17 PD 0/SEG 16 SEG 15 SEG 14 SEG 13 SEG 12 SEG 11 SEG 10 SEG 9 SEG 8 SEG 7 SEG 6 SEG 5 SEG 4 SEG 3 SEG 2 SEG 1 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 RST EXTAL XTAL V SS V L V LC3 V LC2 V LC1 COM COM COM COM SEG0 PE4/RM C PE3/INT3 PE2/INT2 PE1/INT1 PE0/INT0/EC PF7/SEG31 PF6/SEG30 NC PI1/TEX PI0/TX V DD PF5/SEG29 PF4/SEG28 PF3/SEG27 PF2/SEG26 PF1/SEG25 PF0/SEG24 PD7/SEG23 PD6/SEG22 PD5/SEG21 21 22 23 24 25 26 27 28 29 30 4039383736353431 32 33 70 69 68 67 656671727374757677787980 6364 6162 Note) Do not make any connections to NC (Pin 73).

– 6 – CXP83620/83624, CXP83621/83625 Pin Description Symbol I/O Functions I/O/Analog input PA0/AN0 to PA7/AN7 (Port A) 8-bit I/O port. I/O can be set in a bit unit. Standby release input can be set in a bit unit. Incorporation of pull-up resistor can be set through the program in a bit unit. (8 pins) Analog inputs to A/D converter. (8 pins) I/OPC0 to PC7 PE0/INT0/EC PE1/INT1 PE2/INT2 PE3/INT3 PE4/RMC PE5/TO PE6/ADJ PH0/INT4 PI0/TX PI1/TEX Input/Input/Input Input/Input Input/Input Input/Input Input/Input Output/Output Output/Output I/O/Input Input Input/Input (Port C) 8-bit I/O port. I/O can be set in a bit unit. Capable of driving 12mA sink current. Incorporation of pull-up resistor can be set through the program in a bit unit. (8 pins) (Port E) 7-bit port. Lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins) (Port H) 1-bit I/O port. Incorporation of pull-up resistor can be set through the program. (1 pin) (Port I) 2-bit input port. (2 pins) External interruption request input. (1 pin) Crystal connectors for sub timer/counter clock oscillation. For usage as event counter, input to TEX, and leave TX open. External event inputs for 8-bit timer/counter. External interruption request inputs. (4 pins) Remote control reception circuit input. Output for 8-bit timer/counter rectangular wave. Output for TEX oscillation frequency division. I/O I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output PB0 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 (Port B) 8-bit I/O port. I/O can be set in a bit unit. Incorporation of pull-up resistor can be set through the program in a bit unit. (8 pins) Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1).

– 7 – CXP83620/83624, CXP83621/83625 Symbol I/O Functions Output/Output PF0/SEG24 to PF7/SEG31 (Port F) 8-bit output port. (8 pins) Output/Output PD0/SEG16 to PD7/SEG23 (Port D) 8-bit output port. (8 pins) OutputSEG0 to SEG15 LCD segment signal output. (16 pins) Input Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. EXTAL OutputCOM0 to COM3 LCD common signal output. (4 pins) VLC1 to VLC3 LCD bias power supply. (3 pins) OutputVL Control pin to cut off the current flowing to external LCD bias resistor during standby. XTAL Input Low-level active system reset. NC. Do not make any connections to NC. Positive power supply. GND. RST NC V DD VSS LCD segment signal outputs. (16 pins)

– 8 – CXP83620/83624, CXP83621/83625 ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 150kΩ (VD D = 2.7 to 3.3V) IP Pull-up resistor Port B data Port B direction "0" after a reset R D (Port B) "0" after a reset Internal data bus ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 150kΩ (VD D = 2.7 to 3.3V) IP Pull-up resistor Port B data Port B direction "0" after a reset R D (Port B) "0" after a reset Internal data bus C S0 SI0 SI1 Schm itt input Port B 8 pins Hi-Z Hi-Z After a reset PA0/AN0 to PA7/AN7 PB0 Port B 1 pin 3 pins Hi-Z PB1/CS0 PB3/SI0 PB6/SI1 ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 150kΩ (VD D = 2.7 to 3.3V) IP Pull-up resistor Port A data Port A direction "0" after a reset Port A function select "0" after a reset R D (Port A) A/D converter Input m ultiplexer "0" after a reset Input protection circuit Edge detection circuit Internal data bus Standby release I/O Circuit Format for Pins Port A Pin Circuit format

– 9 – CXP83620/83624, CXP83621/83625 Pull-up resistor "0" after a reset R D (Port B) "0" after a reset Internal data bus Port B data Port B direction IP Serial data output ebable Port B function select "0" after a reset SO "0" after a reset ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 150kΩ (VD D = 2.7 to 3.3V) O utput buffer capability Port B Port C 2 pins Hi-Z Hi-Z After a reset PB2/SCK0 PB5/SCK1 PB4/SO0 PB7/SO1 2 pins Hi-Z PC0 to PC7 8 pins Pull-up resistor "0" after a reset R D (Port B) "0" after a reset Schm itt input SC K in Internal data bus Port B data Port B direction IP Serial clock output ebable Port B function select "0" after a reset SC K out "0" after a reset ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 150kΩ (VD D = 2.7 to 3.3V) O utput buffer capability Port B Pin Circuit format IP Pull-up resistor Port C data Port C direction "0" after a reset R D (Port C ) "0" after a reset Internal data bus ∗2 Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 150kΩ (VD D = 2.7 to 3.3V) ∗1 H igh current drive 12m A (VD D = 4.5 to 5.5V) 4.5m A (VD D = 2.7 to 3.3V)

– 10 – CXP83620/83624, CXP83621/83625 Port E function select R D (Port E) Internal data bus "0" after a reset Port E data "1" after a reset TO Port E Port E Port H 5 pins Hi-Z High level After a reset PE0/INT0/EC PE1/INT1 PE2/INT2 PE3/INT3 PE4/RMC PE5/TO 1 pin PE6/ADJ 1 pin Hi-Z PH0/INT4 1 pin IP Schm itt input IN T0/EC IN T1 IN T2 IN T3 R M C Internal data bus R D (Port E) Port E Pin Circuit format Port E data "1" after a reset M PX AD J2K AD J16K AD J32K Internal reset signal ∗2 ∗1 AD J signals are frequency driver outputs for TEX oscillation frequency adjustm ent. AD J2K provides usage as buzzer output.∗2 Pull-up transistor approx. 150kΩ (VD D = 4.5 to 5.5V) approx. 200kΩ (VD D = 2.7 to 3.3V) Port E function select (upper) Port E function select (low er) R D (Port E) Internal data bus "00" after a reset ∗ Pull-up transistor approx. 100kΩ (VD D = 4.5 to 5.5V) approx. 150kΩ (VD D = 2.7 to 3.3V) IP Pull-up resistor Port H data Port H direction "0" after a reset R D (Port H ) "0" after a reset Internal data bus IN T4 Schm itt input High level High level at ON resistance of pull-up transistor during a reset.

– 11 – CXP83620/83624, CXP83621/83625 Segm ent data Segm ent driver Port/segm ent output select "0" after a reset Port D , F data Port D Port F Segment Common 2 pins Oscillation halted port input Segment Output DD level) After a reset PI0/TX PI1/TEX PD0/SEG16 to PD7/SEG23 PF0/SEG24 to PF7/SEG31 16 pins V DD level SEG0 to SEG15 16 pins VDD level COM0 to COM3 4 pins "1" after a reset R D (Port I) Internal data bus Schm itt input IP IP R D (Port I) Internal data bus C lock inputPI1/TEX PI0/TX TEX oscillation control circuit Port I Pin Circuit format VC H VC L VLC 1 VLC 2 VLC 3 VD D

– 12 – CXP83620/83624, CXP83621/83625 EXTAL XTAL IPIP

D iagram show s circuit com position during oscillation.
Feedback resistor is rem oved during stop. XTAL becom es high level. 1 pin Hi-Z Oscillation After a reset VL EXTAL XTAL 2 pins Low level (during a reset) RST 1 pin LC D control (D SP bit) "0" after a reset Pin Circuit format IP Schm itt input M ask option Pull-up resistor /LiteDiagLines O P

– 13 – CXP83620/83624, CXP83621/83625 *1 VIN and VOUT must not exceed VDD + 0.3V. *2 The high current drive transistor is the N-ch transistor of Port C (PC). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Supply voltage LCD bias voltage Input voltage Output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD VLC1 , VLC2 , VLC3 VIN VOUT IOH SIOH IOL IOLC SIOL Topr Tstg PD –0.3 to +7.0 –0.3 to +7.0*1 –0.3 to +7.0*1 –0.3 to +7.0*1 –50 100 –20 to +75 –55 to +150 600 380 380 V V V V mA mA mA mA mA mW mW mW Output per pin Total for all output pins Value per pin, excluding high current output pins Value per pin for high current output pins*2 Total for all output pins QFP-80P-L01 LQFP-80P-L01 QFP-80P-L03 Item Symbol Rating Unit Remarks Absolute Maximum Ratings (Vss = 0V)

– 14 – CXP83620/83624, CXP83621/83625 LCD bias voltage High level input voltage Low level input voltage Operating temperature Supply voltage 5.5 5.5 5.5 VDD VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 V V V V V V V V Item Symbol Min. Max. Unit Remarks 2.7 2.7 2.5 Vss 0.7VDD 0.8VDD VDD – 0.4 –0.3 –20 VLC1 VLC2 VLC3 VIH VIHS VIHEX VIL VILS VILEX Topr Guaranteed operation range during 1/16 frequency dividing mode or sleep mode Guaranteed operation range with TEX clock Guaranteed data hold range during stop LCD power supply range* Hysteresis input*2 EXTAL *3, TEX*5 Hysteresis input*2 EXTAL *3, TEX*5 VDD *1 Value for each pin of normal input ports (PA, PB0, PB4, PB7, PC and PI). *2 Value of the following pins; RST, CS0, SI0, SI1, SCK0, SCK1, EC/INT0, INT1, INT2, INT3, INT4 and RMC. *3 Specifies only during external clock input. *4 Optimal values are determined by LCD used. *5 Specifies only during external event count input. Recommended Operating Conditions (Vss = 0V) Guaranteed operation range during 1/2 and 1/4 frequency dividing mode fc = 10MHz or less fc = 4MHz or less 4.5 2.7 5.5 5.5

– 15 – CXP83620/83624, CXP83621/83625 VDD = 4.5V, IOH = –1.0mA VDD = 4.5V, IOH = –2.4mA VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL= 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V VIL= 0.4V VDD = 4.5V, VIH = 4.0V VDD = 5.5V VI= 0, 5.5V VDD = 5V VLC1 = 3.75V VLC2 = 2.5V VLC3 = 1.25V High level output voltage I/O leakage current Supply current*5 4.0 3.5 4.0 3.5 0.5 –0.5 0.1 –0.1 –1.5 –2.78 V V V V V V V V µA µA µA µA µA µA µA kΩ kΩ PC PA, PB, PC, PD * 2, PE5, PE6, PF * 2, PH0, VL (VOL only) SCK0 *1, SO0*1 SCK1 *1, SO1*1 EXTAL TEX RST *3 Item Symbol Pins Conditions Min. PA to PC*4, PE0 to PE4, PH * 4, PI, RST *3 VDD IIZ Common output impedance R COM Segment output impedance R SEG COM0 to COM3 SEG0 to SEG15, SEG16 to SEG31 *2 IDD1 High-speed mode operation (1/2 frequency dividing clock) IDDS1 IDDS3 VOL IIHE IILE IIHT IILT IILR IIL IIH Low level output voltage Input current Typ. 0.4 0.6 1.5 –40 –10 –400 –45 ±10 Max. Unit DC Characteristics (VDD = 4.5 to 5.5V)

Electrical Characteristics

(Ta = –20 to +75°C, Vss = 0V) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) Sleep mode Stop mode VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) 12 40 mA 2.6 8 mA VDD = 5.5V, 10MHz and termination of TEX oscillation 10 µA VOH

– 16 – CXP83620/83624, CXP83621/83625 *1 Specifies when Port B output buffer capability switching register (BUFB: 01F4h) selects the buffer capability to high. *2 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PD and PF is the case when the common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output. *3 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. *4 Pins PA to PC, and PH0 specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. *5 When all output pins are left open. Clock 1MHz 0V for all pins excluding measured pins Input capacity 10 20 pF PA to PC, PE0 to PE4, PH, PI, EXTAL, RST Item Symbol Pins Conditions Min. C IN Typ. Max. Unit

– 17 – CXP83620/83624, CXP83621/83625 VDD = 2.7V, IOH = –0.12mA VDD = 2.7V, IOH = –0.45mA VDD = 2.7V, IOL = 1.0mA VDD = 2.7V, IOL = 1.4mA VDD = 2.7V, IOL = 4.5mA VDD = 3.3V, VIH = 3.3V VDD = 3.3V, VIL= 0.3V VDD = 3.3V, VIH = 3.3V VDD = 3.3V VIL= 0.3V VDD = 2.7V, VIH = 2.4V VDD = 3.3V VI= 0, 3.3V VDD = 3V VLC1 = 2.25V VLC2 = 1.5V VLC3 = 0.75V High level output voltage I/O leakage current Supply current*5 2.5 2.1 0.3 –0.3 0.1 –0.1 –0.9 0.9 V V V V V V µA µA µA µA µA µA µA kΩ kΩ PC PA, PB, PC, PD * 2, PE5, PE6, PF * 2, PH0, VL (VOL only) EXTAL TEX RST *3 Item Symbol Pins Conditions Min. PA to PC*4, PE0 to PE4, PH * 4, PI, RST *3 VDD IIZ Common output impedance R COM Segment output impedance R SEG COM0 to COM3 SEG0 to SEG15, SEG16 to SEG31 *2 IDD1 High-speed mode operation (1/2 frequency dividing clock) IDDS1 IDDS3 VOH VOL IIHE IILE IIHT IILT IILR IIL IIH Low level output voltage Input current 4.5 Typ. 0.25 0.4 0.9 –20 –10 –200 –20 ±10 7.5 Max. Unit IDD2 DC Characteristics(VDD = 2.7 to 3.3V) (Ta = –20 to +75°C, Vss = 0V) VDD = 3.3V, 4MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3.3V, TEX*6 crystal oscillation (C1 = C2 = 47pF) Sleep mode Stop mode VDD = 3.3V, 4MHz crystal oscillation (C1 = C2 = 15pF) 2.5 8 mA 30 100 µA 0.6 2 mA IDDS2 VDD = 3.3V, TEX*6 crystal oscillation (C1 = C2 = 47pF) VDD = 3.3V, 4MHz and termination of TEX oscillation 16 30 µA 10 µA SCK0 *1, SO0*1 SCK1 *1, SO1*1 VDD = 2.7V, IOH = –0.24mA VDD = 2.7V, IOH = –0.90mA 2.5 V 2.1 V

– 18 – CXP83620/83624, CXP83621/83625 *1 Specifies when Port B output buffer capability switching register (BUFB: 01F4h) selects the buffer capability to high. *2 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24 to PF7/SEG31, PD and PF is the case when the common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output. *3 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. *4 Pins PA to PC, and PH0 specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. *5 When all output pins are left open. *6 The value when 32.768kHz oscillator is connected to TEX. Clock 1MHz 0V for all pins excluding measured pins Input capacity 10 20 pF PA to PC, PE0 to PE4, PH, PI, EXTAL, RST Item Symbol Pins Conditions Min. C IN Typ. Max. Unit

– 19 – CXP83620/83624, CXP83621/83625 *1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”). EXTAL tXH tXLtC F tC R 0.4V VD D – 0.4V 1/fc /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines C rystal oscillation C eram ic oscillation EXTAL XTAL External clock EXTAL XTAL 74H C 04C 1 C 2 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines TEX clock applied condition C rystal oscillation TEX TX C 1 C 2 TEX EC tEH tELtEF tER 0.2VD D 0.8VD D tTH tTLtTF tTR AC Characteristics (1) Clock timing System clock frequency System clock input pulse width System clock input rise and fall time Event count input clock pulse width Event count input clock rise and fall time System clock frequency Event count input clock input pulse width Event count input clock rise and fall time f C tXL, tXH tCR , tCF tEH , tEL tER , tEF fC tTL, tTH tTR , tTF XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX MHz ns ns ns ms kHz µs ms Fig. 1, Fig. 2 Fig. 1, Fig. 2 external clock drive Fig. 1, Fig. 2 external clock drive Fig. 3 Fig. 3 V DD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 37.5 77.5 tsys + 50*1 32.768 200 (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V) Fig. 2. Clock applied conditions Fig. 1. Clock timing Fig. 3. Event count clock timing Item Symbol Pin Conditions Min. UnitTyp. Max. VDD = 4.5 to 5.5V VDD = 4.5 to 5.5V

– 20 – CXP83620/83624, CXP83621/83625 Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Note 1)tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) Note 2)CS, SCK, SI and SO indicates CS0, SCK0, SI0 and SO0, respectively. Note 3)The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL. Note 4)The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer capability to normal. (2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item CS ﬂ ﬁ SCK delay time CS › ﬁ SCK float delay time CS ﬂ ﬁ SO delay time CS ﬂ ﬁ SO float delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (for SCK ›) SI input hold time (for SCK ›) SCK ﬂ ﬁ SO delay time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO SCK0 SCK0 SO0 SO0 CS0 SCK0 SCK0 SI0 SI0 SO0 Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode ns ns ns ns ns Symbol Pin Min. tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 16000/fc tsys + 100 8000/fc – 100 –tsys + 100 200 2tsys + 100 100 ns ns ns ns ns ns ns ns ns ns tsys + 200 100 Max. UnitConditions

– 21 – CXP83620/83624, CXP83621/83625 Chip select transfer mode (SCK = output mode) Chip select transfer mode (SCK = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Note 1)tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) Note 2)CS, SCK, SI and SO indicates CS0, SCK0, SI0 and SO0, respectively. Note 3)The load condition for the SCK output mode, SO output delay time is 50pF. Note 4)The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer capability to high. Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V) Item CS ﬂ ﬁ SCK delay time CS › ﬁ SCK float delay time CS ﬂ ﬁ SO delay time CS ﬂ ﬁ SO float delay time CS high level width SCK cycle time SCK high and low level widths SI input setup time (for SCK ›) SI input hold time (for SCK ›) SCK ﬂ ﬁ SO delay time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO SCK0 SCK0 SO0 SO0 CS0 SCK0 SCK0 SI0 SI0 SO0 Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode ns ns ns ns ns Symbol Pin Min. tsys + 250 tsys + 200 tsys + 250 tsys + 200 tsys + 200 2tsys + 200 16000/fc tsys + 100 8000/fc – 150 –tsys + 100 200 2tsys + 100 100 ns ns ns ns ns ns ns ns ns ns tsys + 250 125 Max. UnitConditions

– 22 – CXP83620/83624, CXP83621/83625 Fig. 4. Serial transfer CH0 timing C S0 SC K0 0.2VD D 0.8VD D tW H C S tD C SK tD C SKF 0.8VD D 0.2VD D 0.8VD D tKC Y tKL tKH 0.8VD D 0.2VD D SI0 tSIK tKSI Input data tD C SO tKSO tD C SO F O utput data 0.8VD D 0.2VD D SO 0

– 23 – CXP83620/83624, CXP83621/83625 Serial Transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item SCK cycle time tKCY SCK1 Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode 1000 8000/fc 400 4000/fc – 50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns SCK1 SI1 SI1 SO1 tKH tKL tSIK tKSI tKSO SCK high and low level widths SI input setup time (for SCK›) SI input hold time (for SCK›) SCK ﬂ ﬁ SO delay time Symbol Pin Conditions Min. Max. Unit Note 1)tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) Note 2)SCK, SI and SO indicates SCK1, SI1 and SO1, respectively. Note 3)The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. Note 4)The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer capability to normal. Serial Transfer (CH1) (Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V) Item SCK cycle time tKCY SCK1 Input mode Output mode Input mode Output mode SCK input mode SCK output mode SCK input mode SCK output mode SCK input mode SCK output mode 1000 8000/fc 400 4000/fc – 100 100 200 200 100 250 125 ns ns ns ns ns ns ns ns ns ns SCK1 SI1 SI1 SO1 tKH tKL tSIK tKSI tKSO SCK high and low level widths SI input setup time (for SCK›) SI input hold time (for SCK›) SCK ﬂ ﬁ SO delay time Symbol Pin Conditions Min. Max. Unit Note 1)tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) Note 2)SCK, SI and SO indicates SCK1, SI1 and SO1, respectively. Note 3)The load condition for the SCK1 output mode, SO1 output delay time is 50pF. Note 4)The value when Port B output buffer capability switching register (BUFB: 01F4h) selects buffer capability to high.

– 24 – CXP83620/83624, CXP83621/83625 tKC Y tKL tKH 0.2VD D 0.8VD D tSIK tKSI tKSO Input data O utput data 0.2VD D 0.8VD D 0.2VD D 0.8VD D SC K1 SI1 SO 1 Fig. 5. Serial transfer CH1 timing

– 25 – CXP83620/83624, CXP83621/83625 Conversion time Sampling time Analog input voltage tCONV tSAMP VIAN VZT*1 VFT*2 AN0 to AN7 Ta = 25°C VDD = 5.0V VSS = 0V Linearity error Zero transition voltage Full-scale transition voltage Resolution µs µs VVDD 31/fADC *3 10/fADC *3 Item Symbol Pin Conditions Min. Typ. Max. Unit Bits (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) ±3 LSB 70 mV 5030 4970 –10 4910 mV Conversion time Sampling time Analog input voltage tCONV tSAMP VIAN VZT*1 VFT*2 AN0 to AN7 Ta = 25°C VDD = 2.7V VSS = 0V Linearity error Zero transition voltage Full-scale transition voltage Resolution µs µs VVDD 31/fADC *3 10/fADC *3 Item Symbol Pin Conditions Min. Typ. Max. Unit Bits (Ta = –20 to +75°C, VDD = 2.7 to 3.3V, Vss = 0V) ±3 LSB 40 mV 2716 2688 –10 2651 mV Fig. 6. Definition of A/D converter terms Analog input Linearity error VFTVZT 00h 01h FEh FFh Digital conversion value ∗1 VZT: Value at w hich the digital conversion value changes from 00h to 01h and vice versa. ∗2 VFT: Value at w hich the digital conversion value changes from FEh to FFh and vice versa. ∗3 fAD C = fc/4

– 26 – CXP83620/83624, CXP83621/83625 External interruption high and low level widths Reset input low level width INT0 INT1 INT2 INT3 INT4 RST 32/fc µs µs Item Symbol Pin Conditions Min. Max. Unit tIH tIL tRSL (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 2.7 to 5.5V, Vss = 0V) 0.2VD D 0.8VD D tIH tIL tIL tIH IN T0 IN T1 IN T2 IN T3 IN T4 Fig. 7. Interruption input timing tR SL 0.2VD D R ST Fig. 8. RST input timing

– 27 – CXP83620/83624, CXP83621/83625 Appendix C 1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 2 R d /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL (i) M ain clock /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 1 C 2 R d XTAL (ii) M ain clock /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 1 C 2 R d /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines TEX TX (iii) Sub clock Item Content Reset pin pull-up resistor Non-existent Existent Mask Option Table Product name Package CXP83620/83624 CXP83621/83625 80-pin plastic QFP/LQFP 80-pin plastic QFP (0.65mm pitch) Package List Fig. 9. SPC700 series recommended oscillation circuit *1 Those marked with an *1 signify types with built-in ground capacitance (C1, C2). Manufacturer MURATA MFG CO., LTD. RIVER ELETEC CO., LTD. KINSEKI LTD. Model CSA4.19MG CSA8.00MG CST4.19MGW * CST8.00MTW *1 HC-49/U03 CX-5F FCR4.19MC5 *1 FCR8.0MC5 *1 FCR10.0MC5 *1 CCR4.19MC3 *1 CCR8.0MC5 *1 CCR10.0MC5 *1 TDK Corporation Seiko Instruments Inc. VTC-200 SP-T fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 32.768 75.00 C 1 (pF) C 2 (pF) Rd (Ω ) 100 100 30 ( ± 20%) 20 ( ± 20%) 20 ( ± 20%) 36 ( ± 20%) 20 ( ± 20%) 20 ( ± 20%) 100 100 30( ± 20%) 20( ± 20%) 20( ± 20%) 36( ± 20%) 20( ± 20%) 20( ± 20%) 1.0k 100 100 2.2k 330k 100k Circuit example (i) CSA10.0MT (ii) CST10.00MTW * (i) (ii) (iii) Remarks CL = 12.5pF CL = 6.0pF FCR *: Lead-type ceramic oscillator CCR *: Surface mounted-type ceramic oscillator CL : Load Capacitor CL = 12.0pF CL = 12.0pF CL = 12.0pF

– 28 – CXP83620/83624, CXP83621/83625 10.0 1.0 0.1 (100µA) 0.01 (10µA)1 2 3 4 5 6 7 ID D vs. VD D (fc = 10M H z, Ta = 25°C , typical) VD D – Supply voltage [V] IDD – Supply current [m 5.0 0.5 0.05 (50µA) 1/16 frequency dividing m ode Sleep m ode 1/4 frequency dividing m ode 1/2 frequency dividing m ode 32kH z m ode (instruction) 32kH z Sleep m ode 0 5 10 1/2 frequency dividing m ode 1/4 frequency dividing m ode 1/16 frequency dividing m ode Sleep m ode ID D vs. fc (VD D = 5V, Ta = 25°C , typical) fc – System clock [M H z] IDD – Supply current [m Characteristics Curve

– 29 – CXP83620/83624, CXP83621/83625 Package Outline Unit: mm CXP83620/83624 PAC KAG E STR U C TU R E SO N Y C O D E EIAJ C O D E JED EC C O D E Q FP-80P-L01 Q FP080-P-1420 PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G 42/C O PPER ALLO Y 1.6g 23.9 ± 0.4 20.0 – 0.1 + 0.4 64 41 0.8 0.35 – 0.1 + 0.15 14.0 – 0.1 + 0.4 17.9 ± 0.4 16.3 0.1 – 0.05 + 0.2 2.75 – 0.15 + 0.35 0.8 ± 0.2 0.15 – 0.05 + 0.1 80PIN Q FP (PLASTIC ) M0.2 0.15 0° to 10° D ETAIL A A SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G

42 ALLO Y

14.0 ± 0.2 ∗ 12.0 ± 0.1 (0.22) 60 41 0.18 – 0.03 + 0.08 A 1.5 – 0.1 + 0.2 0.127 – 0.02 + 0.05 0.5 ± 0.2 (13.0) 0.1 ± 0.1 0.5 ± 0.2 0° to 10° D ETAIL A 80PIN LQ FP (PLASTIC ) 0.5g LQ FP-80P-L01 LQ FP080-P-1212 0.1 N O TE: D im ension “∗” does not include m old protrusion. 0.13 M 0.5 CXP83620/83624

– 30 – CXP83620/83624, CXP83621/83625 CXP83621/83625 SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G 42/C O PPER ALLO Y Q FP-80P-L03 Q FP080-P-1414 0.6g 80PIN Q FP (PLASTIC ) 16.0 ± 0.4 14.0 – 0.1 + 0.4 0.3 – 0.1 + 0.15 0.1 – 0.1 + 0.15 (15.0) 0.127 – 0.05 + 0.1 1.5 – 0.15 + 0.35 201 4160 M0.24 0.1 0.65

Summary

CMOS 8-bit Single Chip Microcomputer

Description

The CXP83620/83624 and the CXP83621/83625 are CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time-base timer, sub timer/counter, LCD controller/driver and remote control reception circuit besides the basic configurations of 8-bit CPU, ROM, RAM, and I/O port.

Source title CXP83620 Datasheet(PDF) - Sony Corporation

Read CXP83620 online.