CXP83408

CXP83408 SONY | Alldatasheet

Document overview

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Technical content

Features

• A wide instruction set (213 instructions) which covers various types of data – 16-bit arithmetic/multiplication and division/ Boolean bit operation instructions
• Minimum instruction cycle 400ns at 10MHz operation (4.5 to 5.5V) 122µs at 32kHz operation (2.7 to 5.5V)
• Incorporated ROM capacity 8K bytes (CXP83408, 83409) 12K bytes (CXP83412, 83413) 16K bytes (CXP83416, 83417)
• Incorporated RAM capacity 448 bytes (LCD display data area included)
• Peripheral functions – A/D converter 8 bits, 8 channels, successive approximation system (Conversion time: 32µs/10MHz) – Serial interface Incorporated 8-bit and 8-stage FIFO (1 to 8 bytes auto transfer), 1 circuit 2 channels – Timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32kHz timer/counter – LCD controller/driver Maximum 128 segments display possible (During 1/4 duty) 4 common outputs, 32 segment outputs Display method: Static, 1/2, 1/3 and 1/4 duty Bias method: 1/2 and 1/3 bias – Remote control receiving circuit 8-bit pulse measurement counter, 6-stage FIFO – PWM output 14 bits 1 channel, 8 bits 1 channel
• Interruption 12 factors, 12 vectors, multi-interruption possible
• Standby mode SLEEP/STOP
• Package 80-pin plastic QFP/LQFP
• Piggyback/evaluator CXP83400 (CXP83408, 83412, 83416) CXP83401 (CXP83409, 83413, 83417) Structure Silicon gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP83408/83412/83416 80 pin QFP (Plastic) 80 pin LQFP (Plastic) CXP83409/83413/83417 80 pin QFP (Plastic)

– 2 – CXP83408/83412/83416, CXP83409/83413/83417 XTAL A/D CONVERTER 14BIT PWM GENERATOR REMOCON SERIAL INTERFACE UNIT 0 8BIT TIMER/COUNTER 0 8BIT TIMER 1 FIFO FIFO INTERRUPT CONTROLLER SPC700 CPU CORE ROM 8K/12K/16K BYTES PRESCALER/ TIME BASE TIMER 32kHz TIMER/COUNTER RAM

448 BYTES

8 PC0 to PC7

1 PH0

8 PB0 to PB7

8 PA0 to PA7

8 PD0 to PD7

8 PF0 to PF7

– 3 – CXP83408/83412/83416, CXP83409/83413/83417 PE3/INT3/NMI PE4/RMC PE5/PWM0 PE6/TO/ADJ PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0/PWM1 PA0/AN0 PA1/AN1 PA2/AN2 PD6/SEG22 PD5/SEG21 PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 RST EXTALXTAL V SS V L V LC3 V LC2 V LC1 COM0 COM1 COM2 PE2/INT2PE1/INT1 PE0/INT0/EC PF7/SEG31 PF6/SEG30 NC TEX TX V DD PF5/SEG29 PF4/SEG28 PF3/SEG27 PF2/SEG26 PF1/SEG25 PF0/SEG24 PD7/SEG23 25 26 27 28 29 30 4039383736353431 32 33 70 69 68 67 656671727374757677787980 Pin Assignment (Top View) CXP83408/83412/83416 (QFP package) Note)NC (Pin 75) is always connected to VDD .

– 4 – CXP83408/83412/83416, CXP83409/83413/83417 PE5/PWM0 PE6/TO/ADJ PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0/PWM1 PA0/AN0 PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 RST EXTALXTAL V SS V L V LC3 V LC2 V LC1 COM0 COM1 COM2 COM3SEG0 PE4/RMCPE3/INT3/NMI PE2/INT2 PE1/INT1 PE0/INT0/EC PF7/SEG31 PF6/SEG30 NC TEX TX V DD PF5/SEG29 PF4/SEG28 PF3/SEG27 PF2/SEG26 PF1/SEG25 PF0/SEG24 PD7/SEG23 PD6/SEG22 PD5/SEG21 21 22 23 24 25 26 27 28 29 30 4039383736353431 32 33 70 69 68 67 656671727374757677787980 6364 6162 Pin Assignment (Top View) CXP83408/83412/83416 (LQFP package) Note)NC (Pin 73) is always connected to VDD .

– 5 – CXP83408/83412/83416, CXP83409/83413/83417 PE5/PWM0 PE6/TO/ADJ PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PH0/PWM1 PA0/AN0 PD4/SEG20 PD3/SEG19 PD2/SEG18 PD1/SEG17 PD0/SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 PA1/AN1 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 RST EXTALXTAL V SS V L V LC3 V LC2 V LC1 COM0 COM1 COM2 COM3SEG0 PE4/RMCPE3/INT3/NMI PE2/INT2 PE1/INT1 PE0/INT0/EC PF7/SEG31 PF6/SEG30 NC TEX TX V DD PF5/SEG29 PF4/SEG28 PF3/SEG27 PF2/SEG26 PF1/SEG25 PF0/SEG24 PD7/SEG23 PD6/SEG22 PD5/SEG21 21 22 23 24 25 26 27 28 29 30 4039383736353431 32 33 70 69 68 67 656671727374757677787980 6364 6162 Pin Assignment (Top View) CXP83409/83413/83417 (QFP package) Note)NC (Pin 73) is always connected to VDD .

– 6 – CXP83408/83412/83416, CXP83409/83413/83417 Pin Description Symbol I/O Functions I/O/Analog input PA0/AN0 to PA7/AN7 (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Analog inputs to A/D converter. (8 pins) I/OPC0 to PC7 (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sync current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) I/O/OutputPH0/PWM1 (Port H) 1-bit I/O port. Incorporation of pull-up resistor can be set through the software. (1 pin) 8-bit PWM output. Input/Input/Input Input/Input Input/Input Input/Input/Input Input/Input Output/Output Output/Output/ Output PE0/INT0/EC PE1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/PWM0 PE6/TO/ADJ (Port E) 7-bit port. Lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins) External interruption request input. (4 pins) Remote control receiving circuit input. 14-bit PWM output. Rectangular wave output for 8-bit timer/ counter and 32kHz oscillation frequency divider output. I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Chip select input for serial interface (CH1). Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). External event inputs for timer/counter. Non-maskable intrruption request input.

– 7 – CXP83408/83412/83416, CXP83409/83413/83417 Symbol I/O Functions Output/Output PD0/SEG16 to PD7/SEG23 (Port D) 8-bit output port. (8 pins) LCD segment signal output. (16 pins) Output/Output PF0/SEG24 to PF7/SEG31 (Port F) 8-bit output port. (8 pins) Output Output Output SEG0 to SEG15 COM0 to COM3 VLC1 to VLC3 VL Input Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. EXTAL OutputXTAL Input Crystal connectors for 32kHz timer/counter clock generation circuit. For usage as event counter, connect clock oscillation source to TEX, and leave TX open. TEX OutputTX Input Low-level active, system reset.RST NC. Under normal operating conditions, connect to V DD .NC Positive power supply.VDD GND.Vss LCD segment signal output. LCD common signal output. LCD bias power supply. Control pin to cutt off the current flowing to external LCD bias resistor during standby.

– 8 – CXP83408/83412/83416, CXP83409/83413/83417 IP Pull-up resistor Port B data Port B direction “0” when reset RD (Port B) Data bus ∗ Pull-up transistors approx. 100kΩ “0” when reset Schmitt input CS1 CS0 SI0 SI1 Port B 8 pins Hi-Z Hi-Z When reset PA0/AN0 to PA7/AN7 PB0/CS1 PB1/CS0 PB3/SI0 PB6/SI1 Port B 4 pins 2 pins Hi-Z PB2/SCK0 PB5/SCK1 IP Pull-up resistor Port A data Port A direction “0” when reset Port A input selection “0” when reset RD (Port A) Data bus A/D converter ∗ Pull-up resistors approx. 100kΩ Input multiplexer “0” when reset Input protection circuit I/O Circuit Format for Pins Port A Pin Circuit format ∗ Pull-up transistors approx. 100kΩ Pull-up resistor Port B data Port B direction “0” when reset RD (Port B) Data bus IP “0” when reset Schmitt input SCK in Output enable Port B output selection “0” when reset SCK OUT

– 9 – CXP83408/83412/83416, CXP83409/83413/83417 2 pins Hi-Z Hi-Z Pin When resetCircuit format PB4/SO0 PB7/SO1 PC0 to PC7 8 pins 5 pins Hi-Z PE0/INT0/EC PE1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC IP Schmitt input INT0/EC INT1 INT2 INT3/NMI RMC Data bus RD (Port E) IP Pull-up resistor Port C data Port C direction “0” when reset RD (Port C) Data bus ∗1 Large current 12mA∗2 Pull-up transistors approx. 100kΩ “0” when reset ∗ Pull-up transistors approx. 100kΩ Pull-up resistor Port B data Port B direction “0” when reset RD (Port B) Data bus IP “0” when reset Output enable Port B output selection “0” when reset SO Port E Port C Port B

– 10 – CXP83408/83412/83416, CXP83409/83413/83417 1 pin High level with pull-up transistor ON resistor when reset High level Pin When resetCircuit format PE6/TO/ADJ PE5/PWM0 Port E data “1” when reset Port E output selection (upper) MPX Port E output selection (lower) ADJ2K ADJ16K TO Internal reset signal ∗1 Pull-up transistors approx. 150kΩ. ADJ signals are frequency divider outputs for 32kHz oscillation frequency adjustment. ADJ2K provides usage as buzzer output. TO Output enable Port E 1 pin Hi-Z PH0/PWM1 Data bus RD (Port H) /LiteDiagLines/LiteDiagLines IP /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port H data /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port H direction “0” when reset ∗ Pull-up transistors approx. 100kΩ /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Pull-up resistor /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port H output selection PWM1 “0” when reset “0” when reset Port H 1 pin Port E Port E output selection RD (Port E) Data bus “0” when reset Port E data “1” when reset PWM0

– 11 – CXP83408/83412/83416, CXP83409/83413/83417 16 pins VDD level Pin When resetCircuit format SEG0 to SEG15 VCH VCL Segment output DD level) PD0 to PD7 PF0 to PF7 Segment data Segment driver Port/segment output selection “0” when reset Port data PD7 to PD4 PD3 to PD0 PF7 to PF0 by a bit unit by 4-bit unit Port D Port F 4 pins VDD level COM0 to COM3 VLC1 VLC2 VLC3 VDD Common 24 pins Segment 1 pin Hi-Z VL LCD control (DSP bit) “0” when reset

– 12 – CXP83408/83412/83416, CXP83409/83413/83417 2 pins Oscillation Pin When resetCircuit format EXTAL XTAL EXTAL XTAL IPIP 2 pins Oscillation TEX TX TEX TX IPIP 1 pin Low level RST IP Schmitt input Mask option Pull-up resistor /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines OP

• Diagram shows circuit composition during oscillation.
• Feedback resistor is removed during stop, and XTAL becomes “High” level.
• Diagram shows circuit composition during oscillation.
• When the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed and TEX and TX become “Low” level and “High” level respectively.

– 13 – CXP83408/83412/83416, CXP83409/83413/83417 *1 VIN and VOUT must not exceed VDD + 0.3V. *2 The large current drive transistor is the N-ch transistor of Port C (PC). Note)Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Supply voltage LCD bias voltage Input voltage Output voltage High level output current High level total output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD VLC1 , VLC2 , VLC3 VIN VOUT IOH ∑ IOH IOL IOLC ∑ IOL Topr Tstg PD Low level output current –0.3 to +7.0 –0.3 to +7.0*1 –0.3 to +7.0*1 –0.3 to +7.0*1 –50 100 –20 to +75 –55 to +150 600 380 380 V V V V mA mA mA mA mA mW mW mW Output (value per pin) Total for all output pins All pins excluding large current output (value per pin) Large current outputs (value per pin* Total for all output pins QFP-80P-L01 LQFP-80P-L01 QFP-80P-L03 Item Symbol Rating Unit Remarks Absolute Maximum Ratings (Vss = 0V reference)

– 14 – CXP83408/83412/83416, CXP83409/83413/83417 *1 Value for each pin of normal input ports (PA, PB4, PB7, PC and PH0). *2 Value of the following pins: RST, CS0, CS1, SI0, SI1, SCK0, SCK1, EC/INT0, INT1, INT2, NMI/INT3, and RMC. *3 Specifies only during external clock input. *4 Optimal values are determined by LCD used. High level input voltage Low level input voltage Operating temperature Supply voltage LCD bias voltage 5.5 5.5 5.5 5.5 VDD VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 V V V V V V V V Item Symbol Min. Max. Unit Remarks 4.5 3.5 2.7 2.5 Vss 0.7VDD 0.8VDD VDD – 0.4 –0.3 –20 VLC1 VLC2 VLC3 VIH VIHS VIHEX VIL VILS VILEX Topr During 1/2 and 1/4 frequency division operating modes guaranteed operation range During 1/16 frequency division operating mode or sleep mode quaranteed operation range Guaranteed operation range with TEX clock Guaranteed data hold range during STOP LCD power supply range* Hysteresis input*2 EXTAL *3 Hysteresis input*2 EXTAL *3 VDD Recommended Operating Conditions (Vss = 0V reference)

– 15 – CXP83408/83412/83416, CXP83409/83413/83417 VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL= 0.4V VDD = 5.5V, VIH = 5.5V High level output current 4.0 3.5 0.5 –0.5 0.1 –0.1 –1.5 –2.78 V V V V V V µA µA µA mA µA µA µA kΩ kΩ PC PA, PB, PC, PD* PE5, PE6, PF, PH0, V L (VoL only) EXTAL TEX RST *2 Item Symbol Pins Conditions Min. VDD IDD1 IIL IIH IIZ IDD2 IDDS1 IDDS2 IDDS3 VOH VOL IIHE IILE IIHT IILT IILR Low level output current Input current Typ. 0.4 0.6 1.5 –40 –10 –400 –45 ±10 Max. Unit DC Characteristics

Electrical Characteristics

(Ta = –20 to +75°C, Vss = 0V reference) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) VDD = 5.5Vtermination of 10MHz and 32kHz crystal oscillation Supply current*4 VDD = 5.5V, VIL= 0.4V VDD = 4.5V, VIH = 4.0V VDD = 5.5V, VI= 0, 5.5V VDD = 5V, VLC1 = 3.75V VLC2 = 2.5V VLC3 = 1.25V High-speed mode operation (1/2 frequency divider clock) SLEEP mode STOP mode I/O leakage current R COM Common output impedance R SEG Segment output impedance PA to PC* PH *3, PE0 to PE4, RST * COM0 to COM3 SEG0 to SEG15, SEG16 to SEG31 *1 100 1.1 mA µA mA µA µA

– 16 – CXP83408/83412/83416, CXP83409/83413/83417 Item Symbol Pins Conditions Min. PA to PC, PE1 to PE4, EXTAL, TEX, RST Clock 1MHz 0V for all pins excluding measured pins C IN Typ. Max. Unit *1 Common pins of PD0/SEG16 to PD7/SEG23, PF0/SEG24, PF7/SEG31, PD and PF are the case when the common pin is selected as port; SEG16 to SEG31 is when the common pin is selected as segment output. *2 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. *3 PA to PC, and PH0 specify the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. (PE0 to PE4 specify the leakage current.) *4 When all output pins are left open. Input capacity pF2010

– 17 – CXP83408/83412/83416, CXP83409/83413/83417 *1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control registor (CLC: 00FEH ). tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) EXTAL tXH tXLtCF tCR 0.4V VDD – 0.4V 1/fc /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Crystal oscillation Ceramic oscillation EXTAL XTAL External clock EXTAL XTAL 74HC04C 1 C 2 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 32kHz clock applied condition Crystal oscillation TEX TX C 1 C 2 AC Characteristics (1) Clock timing System clock frequency System clock input pulse width System clock input rise and fall time Event count input clock pulse width Event count input clock rise and fall time System clock frequency Event count input clock input pulse width Event count input clock rise and fall time f C tXL, tXH tCR , tCF tEH , tEL tER , tEF fC tTL, tTH tTR , tTF XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX MHz ns ns ns ms kHz µs ms Item Symbol Pin Conditions Min. Unit Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 V DD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 37.5 tsys + 50*1 Typ. 32.768 Max. 200 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Fig. 2. Clock applied conditions Fig. 1. Clock timing TEX EC tEH tELtEF tER 0.2VDD 0.8VDD tTH tTLtTF tTR Fig. 3. Event count clock timing

– 18 – CXP83408/83412/83416, CXP83409/83413/83417 (2) Serial transfer (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item CS0 fl fi SCK0 (CS1 fl fi SCK1) delay time CS0 › fi SCK0 (CS1 › fi SCK1) floating delay time CS0 fl fi SO0 (CS1 fl fi SO1) delay time CS0 › fi SO0 (CS1 › fi SO1) floating delay time CS0 (CS1) high level width SCK0 (SCK1) cycle time SCK0 (SCK1) high and low level widths SI0 (SI1) input setup time (for SCK0› (SCK1 ›) ) SI0 (SI1) input hold time (for SCK0› (SCK1 ›) ) SCK0 fl fi SO0 (SCK1 fl fi SO1) delay time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO SCK0 (SCK1) SCK0 (SCK1) SO0 (SO1) SO0 (SO1) CS0 (CS1) SCK0 (SCK1) SCK0 (SCK1) SI0 (SI1) SI0 (SI1) SO0 (SO1) Input mode Output mode Input mode Output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode ns ns ns ns ns Symbol Pin Min. tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 16000/fc tsys + 100 8000/fc – 50 100 200 tsys + 200 100 ns ns ns ns ns ns ns ns ns ns tsys + 200 100 Max. Unit Chip select transfer mode (SCK0 (SCK1) = output mode) Chip select transfer mode (SCK0 (SCK1) = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Conditions Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (CLC: 00FEH ). tsys (ns) = 2000/fc (upper two bits = “00”), 4000/fc (upper two bits = “01”), 16000/fc (upper two bits = “11”) Note 2)The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.

– 19 – CXP83408/83412/83416, CXP83409/83413/83417 Fig. 4. Serial transfer CH0 timing CS0 (CS1) SCK0 (SCK1) 0.2V DD 0.8VDD tWHCS tDCSK tDCSKF 0.8VDD 0.2VDD 0.8VDD tKCY tKL tKH 0.8VDD 0.2VDD SI0 (SI1) tSIK tKSI Input data tDCSO tKSO tDCSOF Output data 0.8VDD 0.2VDD SO0 (SO1)

– 20 – CXP83408/83412/83416, CXP83409/83413/83417 Conversion time Sampling time Analog input voltage tCONV tSAMP VIAN VZT*1 VFT*2 AN0 to AN7 Ta = 25°C VDD = 5.0V VSS = 0V Linearity error Zero transition voltage Full-scale transition voltage Resolution µs µs VVDD + 0.3 160/fADC *3 12/fADC *3 Item Symbol Pin Conditions Min. Typ. Max. Unit Bits (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD , Vss = 0V reference) ±3 LSB 70 mV 5030 4970 –10 4910 mV Fig. 5. Definition of A/D converter terms Analog input Linearity error VFTVZT 00H 01H FE H FFH Digital conversion value 00 (f = fEX /2) 01 (f = fEX /4) 11 (f = fEX /16) fADC = fc/2 fADC = fc/4 fADC = fc/16 fADC = fc fADC = fc/2 fADC = fc/8 CKS PCK1, PCK0 0 (f/2 selection) 0 (f selection) *1 VZT: Value atwhich the digital conversion value changes from 00H to 01H and vice versa. *2 VFT: Value at which the digital conversion value changes from FEH to FFH and vice versa. *3 fADC indicates the below values due to the contents of bit 6 (CK3) of the A/D control registor (ADC: 00F9H ) and bit 7 (PCK1) and bit 6 (PCK0) of the clock control resistor (CLC: 00FE H ).

– 21 – CXP83408/83412/83416, CXP83409/83413/83417 External interruption high and low level widths Reset input low level width INT0 INT1 INT2 NMI/INT3 RST 32/fc µs µs Item Symbol Pin Conditions Min. Max. Unit tIH tIL tRSL (4) Interruption, reset input(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) 0.2VDD 0.8VDD tIH tIL tIL tIH INT0 INT1 INT2 NMI/INT3 (NMI is specified only for the falling edge) Fig 6. Interruption input timing tRSL 0.2VDD RST Fig. 7. RST input timing

– 22 – CXP83408/83412/83416, CXP83409/83413/83417 Appendix Fig. 8. SPC700 Series recommended oscillation circuit C 1 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines EXTAL XTAL C 2 Rd /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines EXTAL XTAL Rd (i) Main clock /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines EXTAL XTAL C 1 C 2 Rd XTAL (ii) Main clock /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines EXTAL XTAL C 1 C 2 Rd /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines TEX TX (iii) Sub clock Manufacturer MURATA MFG CO., LTD. RIVER ELETEC CO., LTD. KINSEKI LTD. Model CSA4.19MG CSA8.00MG CST4.19MGW * CST8.00MTW *1 HC-49/U03 HC-49/U (-S) fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 18 18 2.2k 470 560 C 1 (pF) C 2 (pF) Rd (Ω ) Circuit example (i) CSA10.0MT (ii) CST10.00MTW *1 (i) Models with an asterisk (*1) have the built-in ground capacitance (C1, C2). Item Content Reset pin pull-up resistor Non-existent Existent Mask Option Table Product name Package CXP83408/83412/83416 CXP83409/83413/83417 80-pin plastic QFP/LQFP 80-pin plastic QFP (0.65mm pitch) Package Table

– 23 – CXP83408/83412/83416, CXP83409/83413/83417 (100µA) 3 45 6 0.1 5.0 1.0 VDD – Supply voltage [V] IDD – Supply current [mA] IDD vs. VDD (fc = 10MHz, Ta = 25°C, Typical) 0.05 (50µA) 0.01 (10µA) 0.5 10.0 20.0 SLEEP mode 32kHz mode (instruction) 32kHz SLEEP mode SLEEP mode fc – System clock [MHz] IDD – Supply current [mA] IDD vs. fc 5 10 16 1/2 dividing mode 1/2 dividing mode (VDD = 5V, Ta = 25°C, typical) Characteristic Curves Package Outline Unit : mm CXP83408/83412/83416 PACKAGE STRUCTURE SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L01 ∗QFP080-P-1420-A PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY 1.6g 23.9 ± 0.4 20.0 – 0.1 + 0.4 64 41 0.8 0.35 – 0.1 + 0.15 14.0 – 0.1 + 0.4 17.9 ± 0.4 16.3 0.1 – 0.05 + 0.2 2.75 – 0.15 + 0.35 0.8 ± 0.2 0.15 – 0.05 + 0.1 80PIN QFP (PLASTIC) M0.12 0.15 0° to 10° DETAIL A A

– 24 – CXP83408/83412/83416, CXP83409/83413/83417 CXP83409/83413/83417 SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY / PHENOL RESIN SOLDER PLATING

42 ALLOY

14.0 ± 0.2 ∗ 12.0 ± 0.1 (0.22) 60 41 + 0.08 A 1.5 – 0.1 + 0.2 0.127 – 0.02 + 0.05 0.5 ± 0.2 (13.0) 0.1 ± 0.1 0.5 ± 0.20° to 10° DETAIL A 80PIN LQFP (PLASTIC) 0.5g LQFP-80P-L01 ∗QFP080-P-1212-A 0.1 NOTE: Dimension “∗” does not include mold protrusion. SONY CODE EIAJ CODE JEDEC CODE PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY QFP-80P-L03 LQFP080-P-1414 0.6g 80PIN QFP (PLASTIC) 16.0 ± 0.4 14.0 – 0.1 + 0.4 0.65 0.3 – 0.1 + 0.15 0.1 – 0.1 + 0.15 (15.0) 0.127 – 0.05 + 0.1 1.5 – 0.15 + 0.35 201 4160 M ± 0.12 0.1 CXP83408/83412/83416