CXP82616

Sony Corporation

CMOS 8-bit Single Chip Microcomputer

Manufacturer: Sony Corporation

Document: 21 Pages / 243Kb

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CXP82612 SONY | Alldatasheet

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Technical content

Features

Instruction set which supports a wide array of data types — 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and boolean bit operations.
Minimum instruction cycle 400ns for 10MHz, 122µs/for 32kHz operation
On-chip ROM 12K bytes (CXP82612) 16K bytes (CXP82616)
On-chip RAM 448 bytes (Including fluorescent display data area)
Peripheral functions — A/D converter 8-bit, 8-channel, successive approximation system (conversion rate 32µs/10MHz) — Serial interface On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer), 1 circuit 2-channel — Timers 8-bit timer 8-bit timer/counter 19-bit time base timer 32kHz timer/counter — Fluorescent display controller/driver Maximum of 336 segments display available 1 to 16 digits dynamic display Dimmer function High voltage tolerance output (40V) On-chip pull-down resistor (Mask option) Hardware key scan function (Maximum of 8
16 key matrix available) — Remote control receiver circuit On-chip 6 stage FIFO 8-bit pulse measurement counter
Interrupts 13 factors, 13 vectors multi-interruption possible
Standby mode Sleep/stop
Package 80-pin plastic QFP
Piggyback/evaluator CXP82600 80-pin ceramic QFP Structure Silicon gate CMOS IC – 1 – E93Y22A79-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP82612/82616 80 pin QFP (Plastic)

8 BIT TIM ER /C O U N TER 0

INTERRUPT CONTROLLER SPC 700 C PU C O R E PR O M 16K BYTES (C XP8xx16) 12K BYTES (C XP8xx12) PR ESC ALER / TIM E BASE TIM ER 32kH z TIM ER /C O U N TER R AM 448BYTES PA0/AN 0 to PA7/AN 7 T0 to T7 PE4/R M C PB1/C S0 PB3/SI0 PB4/SO 0 PB2/SC K0 PB6/SI1 PB7/SO 1 PB5/SC K1 PE0/EC PE0/INT0 PE1/INT1 PE2/INT2 PE3/INT3 PORT C

8 PC 0 to PC 7

8 PF0 to PF7

8 PB0 to PB7

8 BIT TIM ER 1

80 BYTES

8 PA0 to PA7

8 PD 0 to PD 7

2 PH 0 to PH 1

2 PH 2 to PH 3

C LO C K G EN ./ SYSTEM C O N TR O L – 2 – CXP82612/82616 Block Diagram

V DD V FDP T0 T1 T2 T3 T4 T5 25 26 27 28 29 30 4039383736353431 32 33 70 69 68 67 6566 71727374757677787980 – 3 – CXP82612/82616 Pin Assignment(Top View) Note) 1. NC (Pin 75) is always connected to VDD . 2. PH3/TX (Pin 73) is input port during port selection; oscillation output during oscillation selection

– 4 – CXP82612/82616 Pin Description Symbol I/O Functions I/O/Analog Input PA0/AN0 to PA7/AN7 (Port A) 8-bit I/O port. I/O can be set in a bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Analog inputs to A/D converter. (8 pins) I/O/Input PC0/KR0 to PC7/KR7 PE0/INT0/ EC0 PE1/INT1 PE2/INT2 PE3/INT3/ NMI PE4/RMC PE5 PE6 PE7/TO/ ADJ Input/Input/ Input Input/Input Input/Input Input/Input/ Input Input/Input Input Input Output/Output (Port C) 8-bit I/O port. I/O can be set in a bit unit. Capable of driving 12mA sink current. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) (Port E) 8-bit port. Upper 6 bits are for inputs; lower 2 bits are for outputs. (8 pins) Key return input for FDP segment signal which performs key scanning. External event input to timer/counter. (1 pin) External interrupt requests. (4 pins) Non-maskable interruption request input. Input for remote control receiver circuit. Output for timer/counter rectangular waveform and 32kHz oscillation frequency division. I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output PB0/CS1 PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 (Port B) 8-bit I/O port. I/O can be set in a bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) Chip select input for serial interface (CH1). Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1).

– 5 – CXP82612/82616 Symbol I/O Functions I/OPH0 to PH1 (Port H) 2-bit I/O port. I/O can be set in a bit unit. Incorporation of pull-up resistor can be set through the software in a unit of 2 bits. (2 pins) Output/Output T8/S28 to T15/S21 Dual purpose output for FDP timing and segment signals. Output/Output PF0/S8 to PF7/S15 (Port F) 8-bit output port. (8 pins) OutputS16 to S20 Segment signal output for FDP. OutputT0 to T7 Timing signal output for FDP. Output/Output PD0/S0 to PD7/S7 Input Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. EXTAL Provides voltage for FDP when on-chip resistor is selected under mask option.VFDP OutputXTAL Input/Input Crystal connectors for 32kHz timer/counter clock oscillation circuit. Connect a 32kHz crystal oscillator between TEX and TX. For usage as event input, connect clock oscillation source to TEX, and leave TX open. PH2/TEX Input/OutputPH3/TX Input Low-level active. System reset. RST is input pin.RST NC. Under normal operating conditions, connect to V DD .NC Vcc supply.VDD GNDVss (Port D) 8-bit output port. (8 pins) (Port H) 2-bit input port. (2 pins) Segment signal output for FDP. Segment signal output for FDP.

– 6 – CXP82612/82616 Port B D ata bus R D (Port B) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port B direction IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B data "0" w hen reset "0" w hen reset Schm itt input C S0 C S1 SI0 SI1 ∗ Pull-up transistors approx. 100kΩ /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor SI0 and SI1 are not schm itt input. 8 pins Hi-Z Hi-Z When reset PA0/AN0 to PA7/AN7 PB0/CS1 PB1/CS0 PB3/SI0 PB6/SI1 Port B D ata bus R D (Port B) /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port B output selection "0" w hen reset Schm itt input SC K in /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B direction "0" w hen reset "0" w hen reset SC K O U T O utput enable ∗ Pull-up transistors approx. 100kΩ /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor 4 pins 2 pins Hi-Z PB2/SCK0 PB5/SCK1 D ata bus R D (Port A) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port A direction IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort A data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port A input selection Input protection circuit "0" w hen reset "0" w hen reset "0" w hen reset Input m ultiplexer A/D converter ∗ Pull-up transistors approx. 100kΩ I/O Circuit Format for Pins Port A Pin Circuit format

– 7 – CXP82612/82616 2 pins Hi-Z Hi-Z Pin When resetCircuit format PB4/SO0 PB7/SO1 PC0/KR0 to PC7/KR7 8 pins 5 pins 1 pin Hi-Z High level Hi-Z PE0/EC/INT0 PE1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC /LiteDiagLines IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Schm itt input R D (Port E) D ata bus EC /IN T0 IN T1 IN T2 IN T3/N M I R M C D ata bus R D (Port C ) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port C direction IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port C data "0" w hen reset "0" w hen reset ∗2 Pull-up transistors approx. 100kΩ ∗1 Large current drive of 12m A possible /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor Key input signal D ata bus R D (Port B) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort B output selection "0" w hen reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port B data /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port B direction "0" w hen reset SO O utput enable ∗ Pull-up transistors approx. 100kΩ /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPull-up resistor "0" w hen reset Port E PE5 1 pin PE6 /LiteDiagLines IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines R D (Port E) D ata bus Port E D ata bus R D (Port E) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort E data "1" w hen reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port E Port C Port B

– 8 – CXP82612/82616 1 pin PE7/TO/ADJ D ata bus /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port E output selection "0" w hen reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesPort E data "1" w hen reset R D (Port E) ∗ AD J signals are frequency division outputs for 32kH z oscillation frequency adjustm ent. AD J2K provides usage as buzzer output. /LiteDiagLines /LiteDiagLines /LiteDiagLines Port E output selection "00" w hen reset/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port E output selection /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines O utput enable TO AD J16K AD J2K M PX Port E 2 pins Hi-Z PH0 to PH1 D ata bus R D /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port data "0" w hen reset /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port direction "0" w hen reset ∗ Pull-up transistors approx. 100kΩ /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Pull-up resistor Port H 16 pins Hi-Z or Low level (When PD resistor is connected) PD0/S0 to PD7/S7 PF0/S8 to PF7/S15 D ata bus R D (Port D or Port F) /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Port D data or Port F data ("0" w hen reset) Segm ent output data O utput selection control signal O P /LiteDiagLines /LiteDiagLines M ask option Pull-dow n resistor VFD P ∗ H igh voltage tolerance transistor Port D Port F High level High level with 150kΩ resistor when reset( ) When resetPin Circuit format

– 9 – CXP82612/82616 21 pins Hi-Z or Low level (When PD resistor is connected) S16 to S20 T15/S21 to T8/S28 T0 to T7 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines ∗Segm ent output data O utput selection control signal ("0" w hen reset) O P /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines M ask option Pull-dow n resistor VFD P ∗ H igh voltage tolerance transistor 2 pins Oscillation EXTAL XTAL /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL

D iagram show s circuit construction for oscillation.
D uring STO P feedback resistor is disconnected. /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines IP 2 pins Oscillation halted port input PH2/TEX PH3/TX /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLinesIP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines PH 2/TEX PH 3/TX /LiteDiagLines /LiteDiagLines IP 32kH z oscillation circuit control "1" w hen reset D ata bus R D D ata bus R D C lock input 1 pin High level RST /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines Schm itt input Pull-up resistor M ask optionO P /LiteDiagLines /LiteDiagLines IP When resetPin Circuit format

– 10 – CXP82612/82616 *1 VIN and VOUT must not exceed VDD + 0.3V. *2 Specifies output current of general-purpose I/O ports. *3 The large current drive transistor is an N-ch transistor of Port C (PC). Note)If the absolute maximum ratings are exceed, the LSI could reach permanent breakdown. Also, observing recommended operating conditions is desirable; otherwise, the LSI's reliability could be affected. Supply voltage Input voltage Output voltage VDD VIN VOUT VOD IOH IODH1 IODH2 ∑ IOH ∑ IODH IOL IOLC ∑ IOL Topr Tstg P D VDD – 40 to VDD + 0.3 –15 –35 –40 –100 100 –20 to +75 –55 to +150 600 Display output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation –0.3 to +7.0 –0.3 to +7.0* –0.3 to +7.0*1 V V V V mA mA mA mA mA mA mA mA mW Other than display output pins*2: per pin Display output S0 to S20: per pin Display output T0 to T7, T8/S28 to T15/S21: per pin Total of other than display output pins Total of display output pins Port 1 pin Large current port pin* Entire pin toral As P channel transistor is open drain, VDD voltage is determined as standard. Item Symbol Rating Unit Remarks Absolute Maximum Ratings (Vss = 0V)

– 11 – CXP82612/82616 High level input voltage Low level input voltage Operating temperature Supply voltage 5.5 5.5 5.5 5.5 V DD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 V V V V V V V V V V Item Symbol Min. Max. Unit Remarks 4.5 3.5 2.7 2.5 0.7V DD 0.8VDD VDD – 0.4 –0.3 –20 VIH VIHS VIHEX VIL VILS VILEX Topr High speed mode (1/2, 1/4 clock) guaranteed operation range Low speed mode (1/16 clock) guaranteed operation range Guaranteed operation range with TEX clock Guaranteed data hold operation range during stop Hysteresis input*2 EXTAL pin*3 Hysteresis input*2 EXTAL pin*3 VDD *1 All regular input port (PA, PB3, PB4, PB6, PB7, PC, PE5, PH). *2 For pins RST, CS0, CS1, SCK0, SCK1, EC/INT0, INT1, INT2, INT3/NMI, RMC. *3 Specifies only for external clock input. Recommended Operating Conditions (Vss = 0V)

– 12 – CXP82612/82616 VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL= 0.4V VDD = 5.5V, VIL= 5.5V VDD = 5.5V, VIL= 0.4V VDD = 5.5V, VIL= 0.4V VDD = 4.5V, VIL= 4.0V VDD = 4.5V VOH = VDD – 2.5V VDD = 5.5V VOL = VDD – 35V VFDP = VDD – 35V VDD = 5V VOD – VFDP = 30V VDD = 5.5V VI= 0, 5.5V High level output voltage Display output current Open drain output leak current (P-CH Tr off state) Pull down resistor* Input/Output leak current 4.0 3.5 0.5 –0.5 0.1 –0.1 –1.5 –3.3 –20 V V V V V µA µA µA µA µA µA µA mA mA µA kΩ µA PC PA, PB, PC, PE6, PE7, PH0, PH1 EXTAL TEX RST * PA to PC*2 PH0 *2, PH1*2 Item Symbol Pin Condition Min. PA to PC*2, PH0 *2, PH1*2, RST *2 S0 to S20 S21/T15 to S28/T8 T0 to T7 I IZ IIL IOH ILOL R L VOH VOL IIHE IILE IIHT IILT IILR Low level output voltage Input current 100 Typ. 0.4 0.6 1.5 –40 –10 –400 –50 –20 270 ±10 Max. Unit DC Characteristics

Electrical Characteristics

(Ta = –20 to +75°C, Vss = 0V) S0 to S20 S21/T15 to S28/T8 T0 to T7 S21/T15 to S28/T8 T0 to T7 S0 to S20

– 13 – CXP82612/82616 Supply current*4 Item Symbol Pin Codition Min. 100 µA µA 40 mA mA µA 1.2 8 For pins other than S0 to S28, T0 to T7, PE6, PE7, V DD , Vss, VFDP 1MHz clock 0V other than the measured pins VDD = 5.5V, 10MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) High-speed mode operation (1/2 frequency divider clock) VDD IDD1 IDD2 IDDS1 IDDS2 IDDS3 C IN Typ. Max. Unit *1 RST specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. *2 Pins PA to PC, PH0, and PH1 specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. *3 Applies when the on-chip pull-down resistor is selected under the mask option. *4 All output pins are left open. VDD = 5.5V, 10MHzcrystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHzcrystal oscillation (C1 = C2 = 47pF) Sleep mode Stop mode VDD = 5.5V, termination of 32kHz and 10MHz crystal oscillation. Input capacitance pF2010

– 14 – CXP82612/82616 * tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock control register (address: 00FEH ). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") EXTAL tXH tXLtC F tC R 0.4V VD D – 0.4V 1/fc /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines C rystal oscillation C eram ic oscillation EXTAL XTAL External clock EXTAL XTAL 74H C 04C 1 C 2 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 32kH z clock applied condition C rystal oscillation TEX TX C 1 C 2 AC Characteristics (1) Clock timing System clock frequency System clock input pulse width System clock input rise and fall time Event count input clock pulse width Event count input clock rise and fall time System clock frequency Event count input clock input pulse width Event count input clock rise and fall time f C tXL, tXH tCR , tCF tEH , tEL tER , tEF fC tTL, tTH tTR , tTF XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX MHz ns ns ns ms kHz µs ms Item Symbol Pins Conditions Min. Unit Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 V DD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 37.5 tsys+ 50* Typ. 32.768 Max. 200 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Fig. 2. Clock applied conditions Fig. 1. Clock timing TEX EC tEH tELtEF tER 0.2VD D 0.8VD D tTH tTLtTF tTR Fig. 3. Event count clock timing

– 15 – CXP82612/82616 (2) Serial transfer (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item CS0 ﬂ ﬁ SCK0 (CS1 ﬂ ﬁ SCK1) delay time CS0 › ﬁ SCK0 (CS1 › ﬁ SCK1) float delay time CS0 ﬂ ﬁ SO0 (CS1 ﬂ ﬁ SO1) delay time CS0 › ﬁ SO0 (CS1 › ﬁ SO1) float delay time CS0 (CS1) high level width SCK0 (SCK1) cycle time SCK0 (SCK1) high and low level widths SI0 (SI1) input setup time (for SCK0› (SCK1 ›) ) SI0 (SI1) input hold time (for SCK0› (SCK1 ›) ) SCK0 ﬂ ﬁ SO0 (SCK1 ﬂ ﬁ SO1) delay time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO SCK0 (SCK1) SCK0 (SCK1) SO0 (SO1) SO0 (SO1) CS0 (CS1) SCK0 (SCK1) SCK0 (SCK1) SI0 (SI1) SI0 (SI1) SO0 (SO1) Input mode Output mode Input mode Output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode SCK0 (SCK1) input mode SCK0 (SCK1) output mode ns ns ns ns ns Symbol Pin Min. tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 16000/fc tsys + 100 8000/fc – 50 100 200 tsys + 200 100 ns ns ns ns ns ns ns ns ns ns tsys + 200 100 Max. Unit Chip select transfer mode (SCK0 (SCK1) = output mode) Chip select transfer mode (SCK0 (SCK1) = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Condition Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control register clock (address: 00FEH ). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2)The load condition for the SCK0 (SCK1) output mode, SO0 (SO1) output delay time is 50pF + 1TTL.

– 16 – CXP82612/82616 Fig. 4. Serial transfer CH0 timing C S0 (C S1) SC K0 (SC K1) 0.2VD D 0.8VD D tW H C S tD C SK tD C SKF 0.8VD D 0.2VD D 0.8VD D tKC Y tKL tKH 0.8VD D 0.2VD D SI0 (SI1) tSIK tKSI Input data tD C SO tKSO tD C SO F O utput data 0.8VD D 0.2VD D SO 0 (SO 1)

– 17 – CXP82612/82616 tCONV tSAMP VIAN VZT*1 VFT*2 Ta = 25°C VDD = 5.0V VSS = 0V µs µs VAV REFAN0 to AN7 160/fADC *3 12/fADC *3 Item Symbol Pin Condition Min. Typ. Max. Unit Bits (3)A/D converter characteristics(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD , Vss = 0V) ±3 LSB 150 mV 5120 –70 5050 –10 4930 mV Analog input Linearity error VFTVZT 00H 01H FEH FFH Digital conversion value ∗1 VZT : Value at w hich the digital conversion value changes from 00H to 01H and vice versa. ∗2 VFT : Value at w hich the digital conversion value changes from FEH to FFH and vice versa. ∗3 fAD C indicates the below values due to the bit6 (C KS) of A/D control registor (address: 00F9H ) and the Bit7 (PC K1) and Bit6 (PC K0) of clock control registor (address: 00FEH ) 00 (f = fEX/2) 01 (f = fEX/4) 11 (f = fEX/16) fADC = fC /2 fADC = fC /4 fADC = fC /16 fADC = fC CKS PCK1, 0 0 (f /2 selection)1 (f selection) fADC = fC /2 fADC = fC /8 Conversion time Sampling time Analog input voltage Linearity error Zero transition voltage Full-scale transition voltage Resolution Fig. 5. Definition of A/D converter terms

– 18 – CXP82612/82616 External interruption high and low level widths Reset input low level width INT0 INT1 INT2 INT3 NMI RST 32/fc µs µs Item Symbol Pin Condition Min. Max. Unit tIH tIL tRSL (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) 0.2VD D 0.8VD D tIH tIL IN T0 IN T1 IN T2 IN T3 N M I (N M I specifies only for the falling edge) tIL tIH Fig 6. Interruption input timing tR SL 0.2VD D R ST Fig. 7. RST input timing

– 19 – CXP82612/82616 Appendix Fig. 8. Recommended oscillation circuit C 1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 2 R d/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL R d (i) M ain clock /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 1 C 2 R d XTAL (ii) M ain clock /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 1 C 2 R d/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines TEX TX (iii) Sub clock Manufacturer MURATA MFG CO., LTD. RIVER ELETEC CORPORATION KINSEKI LTD. Model CSA4.19MG CSA8.00MTZ CST4.19MGW * CST8.00MTW * HC-49/U03 HC-49/U (-S) fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 20 20 50 22 1M (iii)32.768kHz C 1 (pF) C 2 (pF) Rd (Ω ) Circuit example (i) CSA10.0MTZ (ii) CST10.0MTW * (i) Those marked with an asterisk (*) signify types with built-in ground capacitance (C1, C2). Mask Option Table Item Content Reset pin pull-up resistor High voltage tolerance pull-down resistor Non-existent Non-existent Existent Existent (selected every pin)

– 20 – CXP82612/82616 5 10 15 (100µA) 3 4 5 6 0.1 5.0 1.0 0.05 (50µA) 0.01 (10µA) 0.5 10.0 20.0 VD D – Supply voltage [V] IDD – Supply current [m ID D vs. VD D (fc = 10M H z, Ta = 25°C , Typical) fc – System clock [M H z] IDD – Supply current [m ID D vs. fc (VD D = 5V, Ta = 25°C , Typical) 32kH z Sleep m ode Sleep m ode 32kH z m ode (instruction) 1/16 dividing m ode 1/2 dividing m ode 1/16 dividing m ode Sleep m ode 1/2 dividing m ode Charactreistics Curves

– 21 – CXP82612/82616 Package Outline Unit : mm PAC KAG E STR U C TU R E SO N Y C O D E EIAJ C O D E JED EC C O D E Q FP-80P-L01 Q FP080-P-1420 PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G 42/C O PPER ALLO Y 1.6g 23.9 ± 0.4 20.0 – 0.1 + 0.4 64 41 0.8 0.35 – 0.1 + 0.15 14.0 – 0.1 + 0.4 17.9 ± 0.4 16.3 0.1 – 0.05 + 0.2 2.75 – 0.15 + 0.35 0.8 ± 0.2 0.15 – 0.05 + 0.1 80PIN Q FP (PLASTIC ) M0.2 0.15 0° to 10° D ETAIL A A

Product Information

CXP82616 specifications and overview.

Summary

CMOS 8-bit Single Chip Microcomputer

Description

CMOS 8-bit Single Chip Microcomputer

Source title CXP82616 Datasheet(PDF) - Sony Corporation

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