CXP82316 | DigiCamel IC Datasheet

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CXP82316 SONY | Alldatasheet

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Technical content

Features

Instruction set which supports a wide array of data types — 213 types of instructions which include 16-bit calculations, multiplication and division arithmetic, and boolean bit operations.
Minimum instruction cycle 400ns for 10MHz operation
On-chip ROM 16K bytes (CXP82316) 20K bytes (CXP82320) 24K bytes (CXP82324)
On-chip RAM 704 bytes (Including fluorescent display data area)
Peripheral functions: — A/D converter 8-bit, 8-channel, successive approximation system (conversion rate 32µs/10MHz) — Serial interface On-chip 8-bit, 8-stage FIFO (1 to 8 bytes auto transfer) 1 channel 8-bit clock synchronized 1 channel — Timers 8-bit timer 8-bit timer/counter 19-bit time-base timer 16-bit capture timer/counter — Fluorescent display controller/driver Maximum of 336 segment display available 1 to 16 digits dynamic display Dimmer function High voltage tolerant output (40V) On-chip pull-down resistor (Mask option) — Remote control receiver circuit On-chip noise elimination circuit On-chip 6 stage FIFO 8-bit pulse measurement counter
Interrupts 14 factors, 15 vectors multi-interruption possible
Standby mode Sleep/stop
Package 80-pin plastic QFP
Piggyback/evaluator CXP82300 80-pin ceramic QFP Structure Silicon gate CMOS IC – 1 – E91722B78-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP82316/82320/82324 80 pin QFP (Plastic)

– 2 – CXP82316/82320/82324 INT0 AN0 to AN7 T0 to T7 T8/S28 T15/S21 S0 to S20 VFDP RMC CS0 SI0 SO0 SCK0 EC0 TO CINT EC1 A/D CONVERTER FDP CONTROLLER/ DRIVER REMOCON

8 BIT TIMER/COUNTER 0

8 BIT TIMER 1

16 BIT CAPTURE

80 BYTES

CLOCK GEN./ SYSTEM CONTROL RAM

704 BYTES

PORT A PORT B PORT C PORT D PORT E PORT F PORT G PA0 to PA7 PB0 to PB6 PC0 to PC7 PD0 to PD7 PE0 to PE5 PE6 to PE7 PF0 to PF7 PG0 to PG3 SI1 SO1 SCK1 SERIAL INTERFACE UNIT 1 PB7 Block Diagram

– 3 – CXP82316/82320/82324 PE3/INT3 PE4/RMC PE5 PE6 PE7/TO PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 PC1/KR1 PC2/KR2 PC3/KR3 PC4/KR4 PC5/KR5 PC6/KR6 PC7/KR7 PA0/AN0 PA1/AN1 PA2/AN2 T8/S28 T9/S27 T10/S26 T14/S22 T15/S21 S20 S19 S18 S17 S16 PF5/S13 PF4/S12 PF3/S11 PF2/S10 PF1/S9 PF0/S8 PD7/S7 PA3/AN3PA4/AN4PA5/AN5 RST EXTALXTALV SS PD0/S0PD1/S1PD2/S2 NCPE2/IN2 PG2PG1PG0 V DD V FDP T0 T1 T2 T3 T4 T5 3431 32 33 70 69 68 67 6566 717374757677787980 25 26 27 28 29 30 T12/S24 T13/S23 T11/S25 PA6/AN6PA7/AN7 403938373635 PD3/S3PD4/S4PD5/S5PD6/S6 PF7/S15 PF6/S14 PE1/EC1/INT1PE0/EC0/INT0PG3 Note) NC (Pin 73) is always connected to VDD. Pin Assignment(Top View)

– 4 – Pin Description (Port A) 8-bit port; single bit addressable. (8 pins) (Port B) Single bit addressable from amongst lower 7 bits; highest bit (PB7) dedicated to output. (8 pins) (Port C) 8-bit port; single bit addressable. Can provide 12mA sink current. (8 pins) (Port E) 8-bit port with lower 6 bits dedicated to input and upper 2 bits dedicated to output. (8 pins) Analog inputs to A/D converter. (8 pins) External capture input to 16-bit timer/counter. Chip select input for serial interface (CH0). Serial clock (CH0) input/output. Serial data (CH0) input. Serial data (CH0) output. Serial clock (CH1) input/output. Serial data (CH1) input. Serial data (CH1) output. Key return input for FDP segment signal. which performs key scanning. Input for external interrupt requests. (4 pins) Input for remote control receiver circuit. Output pin for 16-bit timer/counter rectangular waveform. Symbol I/O Description PA0/AN0 to PA7/AN7 PB0/CINT PB1/CS0 PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 PC0/KR0 to PC7/KR7 PE0/INT0/EC0 PE1/INT1/EC1 PE2/INT2 PE3/INT3 PE4/RMC PE5 PE6 PE7/TO PG0 to PG3 PF0/S8 to PF7/S15 S16 to S20 T8/S28 to T15/S21 T0 to T7 PD0/S0 to PD7/S7 I/O/Analog input I/O/Input I/O/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input Output/Output I/O/Input Input/Input/Input Input/Input/Input Input/Input Input/Input Input/Input Input Output Output/Output I/O Output/Output Output Output/Output Output Output/Output (Port G) 4-bit input/output port; single bit addressable. (4 pins) (Port F) 8-bit dedicated output port. (8 pins) Segment signal output for FDP. Dual purpose output for FDP timing and segment signals. Timing signal output for FDP. (Port D) 8-bit dedicated output port. (8 pins) Segment signal output for FDP. External event input to timer/counter. (2 pins) Segment signal output for FDP.

– 5 – CXP82316/82320/82324 Provides voltage for FDP when on-chip resistor is selected under mask option. Connection for system clock oscillation crystal. When using an external clock, input normal signal to EXTAL and reverse phase signal to the XTAL pin. System reset, active "L". The RST pin is an input/output pin which outputs a "L" level from the on-chip power on reset circuit when the power is turned on. (Mask option) NC pin is always connected to V DD . Positive power supply pin. GND Symbol I/O Description VFDP EXTAL XTAL RST NC VDD VSS Input Output I/O

– 6 – CXP82316/82320/82324 When resetPin Circuit format Input/Output Circuit Formats for Pins IP RD (Port B) Data bus Port B direction Port B output select "0" when reset SCK in Schmitt input Port B data "0" when reset SCK OUT Output enable Hi-Z Hi-Z Hi-Z PB0/CINT PB1/CS0 PB3/SI0 PB6/SI1 PB2/SCK0 PB5/SCK1 Port B Port B 2 pins Port A IP Input multiplexer RD (Port A) Data bus Port A detection Port A data "0" when reset Port A input select "0" when reset A/D converter Input protection circuit IP RD (Port B) Data bus Port B direction Port B data "0" when reset CINT CS0 SI0 SI1 Schmitt input PA0/AN0 to PA7/AN7 8 pins 4 pins

– 7 – CXP82316/82320/82324 When resetPin Circuit format IP RD (Port B) Data bus Port B direction Port B output select "0" when reset Port B data "0" when reset SO Output enable Port B Port C Port E 1 pin High level Hi-Z Hi-Z PB4/SO0 PB7/SO1 1 pin 8 pins Hi-Z PC0/KR0 to PC7/KR7 5 pins PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3 PE4/RMC Port B IP RD (Port C) Data bus Port C direction Port C data "0" when reset Key input signal ∗Capable of driving 12mA large current RD (Port E) IP EC0/INT0 EC1/INT1 INT2 INT3 RMC Data bus Schmitt input RD (Port B) Data bus Port B output select "1" when reset Port B data "0" when reset SO Output enable Internal reset signal ∗Pull-up transistor

– 8 – CXP82316/82320/82324 When resetPin Circuit format Port E Port E Port E Hi-Z 1 pin PE5 IP Data bus RD (Port E) High level 1 pin PE6 Port E data "1" when reset High level 1 pin PE7/TO Port G Hi-Z 4 pins PG0 to PG3 RD (Port E) Data bus Port E output select "1" when reset Port E data "0" when reset Output enable (T2OE) TO IP RD (Port G) Data bus Port G direction Port G data "0" when reset

– 9 – CXP82316/82320/82324 VFDP ("0" when reset) Segment output data Output selection control signal ∗High voltage tolerance transistor Mask option Pull-down resistor OP 21 pins Oscillation Low level When reset S16 to S20 T15/S21 to T8/S28 T0 to T7 EXTAL XTAL 2 pins 1 pin RST Hi-Z or Low level (when PD resistor is connected) Port D Port F Pin Circuit format IPIPEXTAL XTAL ∗Diagram shows circuit construction for oscillation. ∗During stop feedback resistor is disconnected.Mask option IP Schmitt input Pull-up resistor From power on reset circuit (Mask option) OP Hi-Z or Low level (when PD resistor is connected) 16 pins PD0/S0 to PD7/S7 PF0/S8 to PF7/S15 VFDP RD (Port D or Port F) Data bus "0" when reset Port D data or Port F data ("0" when reset) Segment output data Output selection control signal ∗High voltage tolerant transistor Mask option Pull-down resistor OP

– 10 – CXP82316/82320/82324 *1 VIN and VOUT cannot exceed VDD + 0.3V. *2 Rating for output current of general input/output port. *3 The large current drive transistor is an N-channel transistor of Port C. Note) If the absolute maximum ratings are exceeded, the LSI could reach permanent breakdown. Also, observing recommended operating conditions is desirable; otherwise, the LSI's reliability could be affected. Supply voltage Input voltage Output voltage Display output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD VIN VOUT VOD IOH IODH1 IODH2 ∑ IOH ∑ IODH IOL IOLC ∑ IOL Topr Tstg P D As P channel transistor is open drain, VDD voltage is determined as standerd. Other than display output pins*2 : per pin Display outputs S0 to S20: per pin Display outputs T0 to T7, T8/S28 to T15/S21: per pin Total of other than display output pins Total of display output pins Port 1 pin Large current port pin * Entire pin total Item Symbol Rating Unit Remarks Absolute Maximum Ratings (Vss = 0V) –0.3 to +7.0 –0.3 to +7.0*1 –0.3 to +7.0*1 VDD – 40 to VDD + 0.3 –15 –35 –40 –100 100 –20 to +75 –55 to +150 600 V V V V mA mA mA mA mA mA mA mA mW

– 11 – CXP82316/82320/82324 High level input voltage Low level input voltage Operating temperature Supply voltage 5.5 5.5 5.5 VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.4 +75 V V V V V V V Item Symbol Min. Max. Unit Remarks 4.5 3.5 2.5 0.7VDD 0.8VDD VDD – 0.4 –0.3 –20 VIH VIHS VIHEX VIL VILS VILEX Topr High-speed mode (1/2, 1/4 clock) guaranteed range during operation Low-speed mode (1/16 clock) guaranteed range during operation Guaranteed data hold operation range during stop Hysteresis input*2 EXTAL pin*3 Hysteresis input EXTAL pin*3 VDD *1 All regular input ports (PA, PB3, PB4, PB6, PC, PE5, PG). *2 For pins RST, CINT, CS0, SCK0, SCK1, EC0/INT0, EC1/INT1 , INT2, INT3, RMC. *3 Rating only for external clock input. Recommended Operating Conditions (Vss = 0V)

– 12 – CXP82316/82320/82324 VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL= 0.4V VDD = 5.5V, VIL= 0.4V High level output voltage 4.0 3.5 0.5 –0.5 –1.5 –20 V V V V V µA µA µA mA mA µA kΩ µA mA mA µA pF PC EXTAL RST * Item Symbol Pins Conditions Min. VDD IDD1 IDDSL IDDST IOH ILOL C IN VOH VOL IIHE IILE IILR Low level output voltage Input current Typ. 0.4 0.6 1.5 –40 –400 –20 270 –10 Max. Unit

Electrical Characteristics

DC Characteristics (Ta = –20 to +75°C, Vss = 0V) 10MHz crystal oscillator 1 = C2 = 15pF) Sleep mode Stop mode Supply current* Input capacitance VDD = 4.5V VOH = VDD – 2.5V VDD = 5.5V VOL = VDD – 35V VFDP = VDD – 35V VDD = 5.5V High-speed mode (1/2 clock) operation 1MHz clock 0V other than measured Display output current I IZ Input/output leak current Open drain output leakage current (P-CH Tr off state) S0 to S20 S21/T15 to S28/T8 T0 to T7 S0 to S20 S21/T15 to S28/T8 T0 to T7 R L VDD = 5V VOD – VFDP = 30V VDD = 5.5V VI= 0, 5.5V Pull-down resistor*3 S0 to S20 S21/T15 to S28/T8 T0 to T7 PA to PC, PE, PG, RST * 100 PA, PB, PC, PE6, PE7, PG, RST*1 (for VOL only) For pins other than S0 to S28, T0 to T7, PB7, PE6, PE7, V DD , VSS , VFDP *1 RST pin is rated only when the power-on reset circuit is selected under the mask option. *2 RST pin is rated for input current when the pull-up resistor is selected; otherwise it is rated for leak current. *3 Applies when the on-chip pull-down resistor is selected under the mask option. *4 All output pins are left open.

– 13 – CXP82316/82320/82324 * tsys is determind by the upper two bits of the clock control resister (Address: 00FEH ; CPU clock selected) resulting in one of the 3 following values: tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") EXTAL tXH tXLtCF tCR 0.4V VDD – 0.4V 1/fc /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines External clock EXTAL XTAL 74HC04/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Crystal oscillation Ceramic oscillation EXTAL XTAL C 1 C 2 AC Characteristics (1) Clock timing System clock frequency System clock input pulse width System clock input rising and falling times Event count input clock pulse width Event count input clock rising and falling times fC tXL, tXH tCR , tCF tEH , tEL tER , tEF XTAL EXTAL EXTAL EXTAL EC0, EC1 EC0, EC1 MHz ns ns ns ms Item Symbol Pins Conditions Unit Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock driver Fig. 1, Fig. 2 External clock driver Fig. 3 Fig. 3 Min. tsys +50* Max. 200 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Fig. 1. Clock timing Fig. 2. Clock applying condition tEH tELtEF tER 0.2VDD 0.8VDD tTH tTLtTF tTR EC0 EC1 Fig. 3. Event count clock timing

– 14 – CXP82316/82320/82324 Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Note 1) tsys is determind by the upper two bits of the clock control resister (Address: 00FEH ; CPU clock selected) resulting in one of the 3 following values: tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. (2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item CS0 ﬂ ﬁ SCK0 delay time CS0 › ﬁ SCK0 float delay time CS0 ﬂ ﬁ SO0 delay time CS0 › ﬁ SO0 float delay time CS0 high level width SCK0 cycle time SCK0 high and low level width SI0 input setup time (against SCK0 ›) SI0 input hold time (against SCK0 ›) SCK0 ﬂ ﬁ SO0 delay time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO SCK0 SCK0 SO0 SO0 CS0 SCK0 SCK0 SI0 SI0 SO0 Symbol Pin Min. tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 100 tsys + 200 2tsys + 200 16000/fc tsys + 100 8000/fc – 50 100 200 tsys + 200 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max. Unit Condition

Fig. 4. Serial transfer CH0 timing CS0 SCK0 0.2VDD 0.8VDD tWHCS tDCSK tDCSKF 0.8VDD 0.2VDD 0.8VDD tKCY tKL tKH 0.8VDD 0.2VDD SI0 tSIK tKSI Input data tDCSO tKSO tDCSOF Output data 0.8VDD 0.2VDD SO0 – 15 –

– 16 – CXP82316/82320/82324 Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol Pin Min. Max. Condition SCK1 cycle time SCK1 high and low level width SI1 input setup time (against SCK1 ›) SI1 input hold time (against SCK1 ›) SCK1 ﬂ ﬁ SO1 delay time tKCY tKH tKL tSIK tKSI tKSO SCK1 SCK1 SI1 SI1 SO1 Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode 1000 16000/fc 400 8000/fc – 50 100 200 200 100 200 100 Unit ns ns ns ns ns ns ns ns ns ns Note)The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL. Fig. 5. Serial transfer CH1 timing SCK1 SI1 SO1 tKCY tKL tKH 0.2VDD 0.8VDD tSIK tKSI tKSO Input data Output data 0.2VDD 0.8VDD 0.2VDD 0.8VDD

– 17 – CXP82316/82320/82324 (3) A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) VZT*1 VFT*2 tCONV tSAMP VIAN A/D converter operation only Ta = 25°C V DD = 5.0V VSS = 0V –10 4930 160/fADC *3 12/fADC *3 Item Symbol Pin Condition Min. Typ. Max. Unit BitsResolution Linearity error Zero transition voltage Full-scale transition voltage Conversion time Sampling time Analog input voltage 150 5120 V DD 5050 LSB mV mV µs µs V Analog input Linearity error 00H 01H FE H FFH Digital conversion value VZT VFT Fig. 6. Definition of A/D converter terms AN0 to AN7 *1 VZT : Digital Value converted between 00H to 01H. *2 VFT : Digital Value converted between FEH to FFH . *3 fADC : ADC operation clock selection (MSC: Bit 0 of address 01FFH ) and assumes following values: fADC = fc/2 when PS2 is selected. fADC = fc when PS1 is selected.

– 18 – CXP82316/82320/82324 External interrupt high and low level widths Reset input low level width INT0 INT1 INT2 INT3 RST 8/fc µs µs Item Symbol Pin Condition Min. Max. Unit tIH tIL tRSL (4) Interrupts, reset inputs (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) 0.8VDD 0.2VDD tIH tIL INT0 INT1 INT2 INT3 tIL tIH 0.8VDD 0.2VDD Fig. 7. Interrupt input timing tRSL 0.2VDD RST Fig. 8. RST input timing 0.2V 0.2V 4.5V VDD tOFFtR The power supply should be rise smoothly Fig. 9. Power-on reset Power supply rising time Power supply cut-off time tR tOFF VDD Item Symbol Pin Condition Min. Max. Unit ms ms (5) Power-on reset Power-on reset* (Ta = –20 to +75°C, VDD = 4.5 to 5.0V, VSS = 0V) * Specifies only when power-on reset function is selected. 50Power-on reset Repetitive power-on reset 0.05

– 19 – CXP82316/82320/82324 Supplement Fig. 10. Recommended Oscillation Circuit /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines EXTAL XTAL C 1 C 2 (i) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines EXTAL XTAL C 2 (ii) C 1 Manufacturer MURATA MFG CO., LTD FUJI SANGYO CO., LTD KINSEKI LTD. CSA4.19MG CSA8.00MG CSA10.0MT CST4.19MGW * CST8.00MTW * CST10.00MTW * HC-49/U03 HC-49/U (-S) Model fc (MHz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 C 1 (pF) C 2 (pF) Circuit Example (i) (ii) (i) * Indicates types with on-chip grounding capacitors (C1 and C2).

– 20 – CXP82316/82320/82324 Package Outline Unit: mm PACKAGE STRUCTURE SONY CODE EIAJ CODE JEDEC CODE QFP-80P-L01 QFP080-P-1420 PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.6g 23.9 ± 0.4 20.0 – 0.1 + 0.4 64 41 0.8 0.35 – 0.1 + 0.15 14.0 – 0.1 + 0.4 17.9 ± 0.4 16.3 0.1 – 0.05 + 0.2 2.75 – 0.15 + 0.35 0.8 ± 0.2 0.15 – 0.05 + 0.1 80PIN QFP (PLASTIC) M0.12 0.15 0° to 10° DETAIL A A

Product Information

CXP82316 specifications and overview.

Summary

CMOS 8-bit Single Chip Microcomputer

Description

The CXP82316/82320/82324 microcomputer is composed of a CPU, ROM and RAM, and I/O ports. These chips feature many other high-performance circuits in a single-chip CMOS design, including an A/D converter, serial interface, timer/counter, time base timer, capture timer/counter, fluorescent display controller/driver, remote control receiver.

Source title CXP82316 Datasheet(PDF) - Sony Corporation

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