CXP820P60 SONY | Alldatasheet

Document overview

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Technical content

Features

  • Wide-range instruction system (213 instructions) to cover various types of data — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
  • Minimum instruction cycle 250ns at 16MHz operation 122µs at 32kHz operation
  • Incorporated PROM capacity 60K bytes
  • Incorporated RAM capacity 3984 bytes (including fluorescent display area)
  • Peripheral functions — A/D converter 8 bits, 8 channels, successive approximation method (Conversion time of 3.25µs/16MHz) — Serial interface Incorporated buffer RAM (Auto transfer for 1 to 32 bytes), 1 channel 8-bit clock synchronized type, (MSB/LSB first selectable), 1 channel Start-stop synchronization (UART), 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer 16-bit capture timer/counter, 32kHz timer/counter — Fluorescent display panel Supports the universal grid fluorescent display panel controller/driver High voltage drive output port of 56 pins (40V) Maximum of 640 segments display possible Display timing number of 1 to 20 Dimmer function Incorporated pull-down resistor (mask option) Hardware key scan function (Maximum of 16
  • 8 key matrix supportable) — Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO — PWM output 14 bits, 1 channel
  • Interruption 17 factors, 15 vectors, multi-interruption possible
  • Standby mode Sleep/stop
  • Package 100-pin plastic QFP
  • Piggy/Evaluation chip CXP82000 100-pin ceramic QFP – 1 – E97638-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXP820P60 100 pin QFP (Plastic) Structure Silicon gate CMOS IC

– 2 – CXP820P60 8-BIT TIM ER /C O U N TER 0 8-BIT TIM ER 1 U AR T BAU D R ATE G EN ER ATO R U AR T R EC EIVER U AR T TR AN SM ITTER INT2 XTAL PW M R AM

3984 BYTES

PORT A PORT B PORT C PORT D PORT E PORT F PORT G PB0 to PB7 PC 0 to PC 7 PD 0 to PD 7 PE0 to PE5 PF0 to PF7 PG 0 to PG 7 PE6 to PE7 TEX EXTAL TX C S0 PR O M 60K BYTES R AM KEY SC AN PORT H PH 0 to PH 78 CLO CK G ENERATO R/ SYSTEM CO NTRO L 14-BIT PW M G EN ER ATO R FIFOR EM O C O NR M C SI0 SO 0 SC K0 SI1 SO 1 SC K1 EC 0 TO C IN T EC 1 AD J G 0/A0 to G 15/A15 A16 to A23 A24 to A56 VFD P KR 0 to KR 7 SER IAL IN TER FAC E (C H 1) 16-BIT C APTU R E TIM ER /C O U N TER 2 SER IAL IN TER FAC E (C H 0) BU FFER R AM PORT I PI0 to PI44 TxD R xD INTERRUPT CONTROLLER R AM Vpp Block Diagram

– 3 – CXP820P60 Pin Assignment (Top View) G 1/A1 G 0/A0 Vpp PE0/EC 0/IN T0 PE1/EC 1/IN T1 PE2/IN T2 PE3/IN T3/N M I PE4/R M C PE5/C IN T PE6/PW M PE7/TO /AD J PC 0/KR 0 PC 1/KR 1 PC 2/KR 2 PC 3/KR 3 PC 4/KR 4 PC 5/KR 5 PC 6/KR 6 PC 7/KR 7 PB0/TxD PB1/C S0/R xD PB2/SC K0 PB3/SI0 PB4/SO 0 PB5/SC K1 PB6/SI1 PB7/SO 1 PI0 PA0/AN 0 PA1/AN 1 4039383736353431 32 33 41 42 43 44 45 46 47 48 49 50 81828384 88 87 86 85 8990100 99 98 97 96 95 94 919293 PA2/AN2 PA3/AN3 PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 PI1 RST EXTAL XTAL Vss PI2/TX PI3/TEX V DD V FDP PD0/A55 PD1/A54 PD2/A53 PD3/A52 PD4/A51 A21 A22 A23 PH 7/A24 PH 6/A25 PH 5/A26 PH 4/A27 PH 3/A28 PH 2/A29 PH 1/A30 PH 0/A31 PG 7/A32 PG 6/A33 PG 5/A34 PG 4/A35 PG 3/A36 PG 2/A37 PG 1/A38 PG 0/A39 PF7/A40 PF6/A41 PF5/A42 PF4/A43 PF3/A44 PF2/A45 PF1/A46 PF0/A47 PD 7/A48 PD 6/A49 PD 5/A50 G2/A2 G3/A3 G4/A4 G5/A5 G6/A6 G7/A7 G8/A8 G9/A9 G10/A10 G11/A11 G12/A12 V DD G13/A13 G14/A14 G15/A15 A16 A17 A18 A19 A20 Note) 1. Vpp (Pin 3) is left open. 2. VDD (Pins 44 and 89) are both connected to VDD .

– 4 – CXP820P60 Pin Description Symbol I/O Functions I/O/ Analog input PA0/AN0 to PA7/AN7 (Port A) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the pull-up resistor can be set through the program in a unit of 4 bits. (8 pins) Analog inputs to A/D converter. (8 pins) I/O/Input PC0/KR0 to PC7/KR7 PE0/INT0/ EC0 PE1/INT1/ EC1 PE2/INT2 PE3/INT3/ NMI PE4/RMC PE5/CINT PE6/PWM PE7/TO/ ADJ Input/Input/Input Input/Input/Input Input/Input Input/Input/Input Input/Input Input/Input Output/Output Output/Output/ Output (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Capable of driving 12mA sink current. Incorporation of the pull-up resistor can be set through the program in a unit of 4 bits. (8 pins) Serves as key return inputs when operating key scan with fluorescent display panel (FDP) segment signal. (8 pins) I/O/Output PD0/A55 to PD7/A48 (Port D) 8-bit I/O port. I/O can be set in a unit of single bits. (8 pins) FDP segment signal (anode connection) outputs. (Port E) 8-bit port. Lower 6 bits are for inputs; upper 2 bits are for outputs. (8 pins) External event inputs for timer/counter. (2 pins) Inputs for external interruption request. (4 pins) Non-maskable interruption request input. Remote control reception circuit input. External capture input for 16-bit timer/counter. 14-bit PWM output. Output for the 16-bit timer/counter rectangular waves, and 32kHz oscillation frequency division. I/O/Output I/O/Input/Input I/O/I/O I/O/Input I/O/Output I/O/I/O I/O/Input I/O/Output PB0/TxD PB1/CS0/RxD PB2/SCK0 PB3/SI0 PB4/SO0 PB5/SCK1 PB6/SI1 PB7/SO1 (Port B) 8-bit I/O port. I/O can be set in a unit of single bits. Incorporation of the pull-up resistor can be set through the program in a unit of 4 bits. (8 pins) UART transmission data output. Chip select input for serial interface (CH0). Serial clock I/O (CH0). Serial data input (CH0). Serial data output (CH0). Serial clock I/O (CH1). Serial data input (CH1). Serial data output (CH1). UART reception data input.

– 5 – CXP820P60 (Port F) 8-bit output port. I/O can be set in a unit of single bits. (8 pins) FDP segment signal (anode connection) outputs. (8 pins) Symbol I/O Functions OutputA16 to A23 FDP segment signal (anode connection) outputs. (8 pins) Output/Output G0/A0 to G15/A15 Outputs for FDP timing signals (grid connection)/segment signals (anode connection). (16 pins) Output/Output PH0/A31 to PH7/A24 InputPI0 InputPI1 InputPI2/TX Input/InputPI3/TEX Output/Output PG0/A39 to PG7/A32 (Port H) 8-bit output port. (8 pins) (Port I) 4-bit input port. (4 pins) V FDP EXTAL XTAL RST Vpp VDD VSS Input FDP voltage supply for incorporated pull-down (PD) resistor. Crystal connectors for system clock oscillation. When the clock is supplied externally, input to EXTAL; opposite phase clock should be input to XTAL. Low-level active, system reset. Vcc supply for incorporated PROM writing. Leave this pin open during normal operation. Positive power supply. GND. FDP segment signal (anode connection) outputs. (8 pins) Crystal connectors for 32kHz timer/counter clock oscillation. For usage as event counter, input to TEX, and leave TX open. (Port G) 8-bit output port. (8 pins) FDP segment signal (anode connection) outputs. (8 pins) Input PF0/A47 to PF7/A40 I/O/Output

– 6 – CXP820P60 I/O Circuit Format for Pins ∗ Pull-up transistor approx. 100kΩ Pull-up registor Port B data Port B direction "0" after a reset R D (Port B) Internal data bus IP "0" after a reset U AR T output selection "0" after a reset TxD IP Pull-up registor Port B data Port B direction "0" after a reset R D (Port B) Internal data bus ∗ Pull-up transistor approx. 100kΩ "0" after a reset Schm itt input C S0 SI0 SI1 R xD Port B 8 pins Hi-Z Hi-Z After a reset PA0/AN0 to PA7/AN7 1 pin PB0/TxD PB1/CS0/RxD PB3/SI0 PB6/SI1 Port B 3 pins Hi-Z IP Pull-up registor Port A data Port A direction "0" after a reset Port A input selecton "0" after a reset R D (Port A) Internal data bus A/D converter ∗ Pull-up transistor approx. 100kΩ Input m ultiplexer "0" after a reset Input protection circuit Port A Pin Circuit format

– 7 – CXP820P60 2 pins Hi-Z Hi-Z Pin After a resetCircuit format PB4/SO0 PB7/SO1 PC0/KR0 to PC7/KR7 8 pins IP Pull-up registor Port C data Port C direction "0" after a reset R D (Port C ) Internal data bus ∗1 Large current 12m A∗2 Pull-up transistor approx. 100kΩ "0" after a reset Key input signal ∗ Pull-up transistor approx. 100kΩ Pull-up registor Port B data Port B direction "0" after a reset R D (Port B) Internal data bus IP "0" after a reset Serial data output enable Port B outputput selecton "0" after a reset SO Port C Port B ∗ Pull-up transistor approx. 100kΩ Pull-up registor Port B data Port B direction "0" after a reset R D (Port B) Internal data bus IP "0" after a reset Schm itt input SC K IN Serial clock output enable Port B output selecton "0" after a reset SC K O U T Port B 2 pins Hi-Z PB2/SCK0 PB5/SCK1

– 8 – CXP820P60 Pin After a resetCircuit format 1 pin PE7/TO/ADJ ∗1 AD J signal is a frequency dividing output for 32kH z oscillation frequency adjustm ent. AD J2K can be used for buzzer output. ∗2 Pull-up transistor approx. 150kΩ Port E data "00" after a reset TO output enable TO AD J16K∗1 AD J2K∗2 M PX Internal reset signal Port E output selecton (upper) Port E output selecton (low er) "1" after a reset Port E 16 pins Hi-Z PD0/A55 to PD7/A48 PF0/A47 to PF7/A40 Port D Port F High level (High level at ON resistance of pull-up transistor during a reset) ∗ H igh voltage drive transistor R D (Port D and F) Internal data bus "1" after a reset Port D and F data Port D and F direction Segm ent output data O utput selection control signal ("0" after a reset) IP 1 pin PE6/PWM Port E output selecton Port E data R D (Port E) Internal data bus "1" after a reset "0" after a reset PW M O utput enable Port E High level 6 pins Hi-Z PE0/EC0/INT0 PE1/EC1/INT1 PE2/INT2 PE3/INT3/NMI PE4/RMC PE5/CINT IP Schm itt input Internal data bus EC 0/IN T0 EC 1/IN T1 IN T2 IN T3/N M I R M C C IN T R D (Port E) Port E

– 9 – CXP820P60 Hi-Z PG0/A39 to PG7/A32 PH0/A31 to PH7/A24 Port G Port H R D (Port G and H ) Internal data bus O utput selection control signal ("0" after a reset) Port G and H data "0" after a reset Segm ent output data ∗ H igh voltage drive transistor 16 pins Pin After a resetCircuit format 16 pins G0/A0 to G15/A15 2 pins 2 pins EXTAL XTAL Oscillation Hi-Z PI0 PI1 Hi-Z or Low level (when PD resistor is connected) O utput selection control signal ("0" after a reset) Segm ent output data Tim ing output data ∗ ∗ H igh voltage drive transistor Pull-dow n registor VFD P 8 pins A16 to A23 Hi-Z or Low level (when PD resistor is connected) O utput selection control signal Segm ent output data ∗ H igh voltage drive transistor Pull-dow n registor VFD P ("0" after a reset) EXTAL XTAL IPIP

  • Diagram shows circuit composition during oscillation.
  • Feedback resistor is removed and XTAL becomes High level during stop. IP R D (Port I) Internal data bus

– 10 – CXP820P60 Pin After a resetCircuit format 2 pins Oscillation stop port input Low level PI2/TX PI3/TEX 1 pin RST /LiteDiagLines /LiteDiagLines /LiteDiagLines IP /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines PI3/TEX PI2/TX /LiteDiagLines IP TEX oscillation circuit control "1" after a reset Internal data bus R D Internal data bus R D C lock input IP Schm itt input Pull-up registor

– 11 – CXP820P60 *1 VIN, VOUT and VOD must not exceed VDD + 0.3V. *2 VFDP and VOD must not exceed VDD – 40V. *3 Specifies output current of general-purpose I/O ports. *4 The large current drive transistor is the N-CH transistor of Port C (PC). Note)Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding these conditions may adversely affect the reliability of the LSI. Supply voltage FDP display supply voltage Input voltage Output voltage Display output voltage High level output current High level total output current Low level output current Low level total output current Operating temperature Storage temperature Allowable power dissipation V DD Vpp VFDP VIN VOUT VOD IOH IODH1 IODH2 ∑ IOH ∑ IODH IOL IOLC ∑ IOL Topr Tstg P D –0.3 to +7.0 –0.3 to +13.0 –40*2 to +7.0*1 –0.3 to +7.0*1 –0.3 to +7.0*1 –40*2 to +7.0*1 –15 –50 –30 –120 100 –20 to +75 –55 to +150 600 V V V V V V mA mA mA mA mA mA mA mA mW Incorporated PROM All pins excluding display outputs* (value per pin) Display outputs A20 to A55 (value per pin) Display outputs G0/A0 to G15/A15, and A16 to A19 (value per pin) Total for all pins excluding display outputs Total for all display outputs Pins excluding large current output (value per pin) Large current output pins* 4 (value per pin) Total for all output pins Item Symbol Rating Unit Remarks Absolute Maximum Ratings (Vss = 0V reference)

– 12 – CXP820P60 Low level input voltage Operating temperature Supply voltage 5.5 5.5 5.5 5.5 V DD VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.7 0.4 +75 V V V V V V V V V V V V Item Symbol Min. Max. Unit Remarks 4.5 3.5 2.7 2.5 0.7V DD 0.8VDD 0.7VDD VDD – 0.4 –0.3 –20 VIH VIHS VIHH VIHEX VIL VILS VILH VILEX Topr Guaranteed operation range during 1/2, 1/4 frequency dividing clock modes Guaranteed operation range during 1/16 frequency dividing clock or sleep modes Guaranteed operation range with TEX clock Guaranteed data hold range during stop EXTAL *4 EXTAL *4 VDD *1 Value for each pin of normal input port (PA, PB0, PB4, PB7, PC). *2 Value of the following pins: RST, CINT, CS0/RxD, SI0, SI1,SCK0, SCK1, EC0/INT0, EC1/INT1, INT2, INT3/NMI, RMC. *3 Value for each pin (PD, PF). *4 Specifies only during external clock input. Recommended Operating Conditions (Vss = 0V reference) High level input voltage

– 13 – CXP820P60 VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL= 0.4V VDD = 5.5V, VIL= 5.5V VDD = 5.5V, VIL= 0.4V VDD = 5.5V, VIL= 0.4V VDD = 4.5V, VIL= 4.0V VDD = 4.5V VOH = VDD – 2.5V VDD = 5.5V VOL = VDD – 35V VFDP = VDD – 35V VDD = 5V VOD – VFDP = 30V VDD = 5.5V VI= 0, 5.5V High level output current Display output current 4.0 3.5 0.5 –0.5 0.1 –0.1 –1.5 –3.3 –30 V V V V V µA µA µA µA µA µA µA mA mA µA kΩ µA PC PA to PD, PE6, PE7, PF to PH PA to PC, PE6, PE7 EXTAL TEX RST Item Symbol Pins Conditions Min. PA to PC* A20 to A55 G0/A0 to G15/A15, A16 to A19 G0/A0 to G15/A15, A16 to A55 G0/A0 to G15/A15, A16 to A23 PA to PC* PD *2, PE0 to PE5, PF * 2, PI IOH Open drain output leakage current (P-CH Tr off state) ILOL Pull-down resistance I/O leakage current R L IIZ VOH VOL IIHE IILE IIHT IILT IILR IIL Low level output current Input current Typ. 0.4 0.6 1.5 –40 –10 –400 –50 –20 220 ±10 Max. Unit DC Characteristics

Electrical Characteristics

(Ta = –20 to +75°C, VSS = 0V reference)

– 14 – CXP820P60 Item Symbol Pins Conditions Min. Typ. Max. Unit Supply current*3 Input capacity VDD PA to PC, PD *2, PE0 to PE5, PF * 2, PI, EXTAL, RST I DD1 1/2 frequency dividing clock mode operation IDDS1 IDDS2 IDDS3 IDD2 VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) Sleep mode Stop mode VDD = 5.5V, termination of 16MHz and 32kHz oscillation VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation (C1 = C2 = 47pF) 27 55 mA 35 110 µA 1.5 8 mA 15 30 µA 10 µA C IN Clock 1MHz 0V for all pins excluding measured pins 10 20 pF 1 PA to PC pins specify the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. *2 PD and PF pins specify when they are used as input pins by program. *3 When all pins are open.

– 15 – CXP820P60 EXTAL tXH tXLtC F tC R 0.4V VD D – 0.4V 1/fc /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines C rystal oscillation C eram ic oscillation EXTAL XTAL External clock EXTAL XTAL 74H C 04C 1 C 2 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 32kH z clock applied condition C rystal oscillation TEX TX C 1 C 2 TEX EC 0 EC 1 tEH tELtEF tER 0.2VD D 0.8VD D tTH tTLtTF tTR *1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control clock register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") AC Characteristics (1) Clock timing System clock frequency System clock input pulse width System clock input rise time, fall time Event count input clock pulse width Event count input clock rise time, fall time System clock frequency Event count input pulse width Event count input rise time, fall time fC tXL tXH tCR tCF tEH tEL tER tEF fC tTL tTH tTR tTF XTAL EXTAL EXTAL EXTAL EC0, EC1 EC0, EC1 TEX TX TEX TEX MHz ns ns ns ms kHz µs ms Item Symbol Pin Conditions Min. Unit Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 V DD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 tsys + 50*1 Typ. 32.768 Max. 200 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Fig. 2. Clock applied conditions Fig. 1. Clock timing Fig. 3. Event count clock timing

– 16 – CXP820P60 Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Note 1)tsys indicates the three values below according to the upper two bits (CPU clock selection) of the control clock register (CLC: 00FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") Note 2)The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL. (2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item CS0 fl fi SCK0 delay time CS0 › fi SCK0 float delay time CS0 fl fi SO0 delay time CS0 › fi SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High, Low level width SI0 input setup time (for SCK0 ›) SI0 input hold time (for SCK0 ›) SCK0 fl fi SO0 delay time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO SCK0 SCK0 SO0 SO0 CS0 SCK0 SCK0 SI0 SI0 SO0 Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode ns ns ns ns ns Symbol Pin Min. tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 16000/fc tsys + 100 8000/fc – 50 100 200 tsys + 200 100 ns ns ns ns ns ns ns ns ns ns tsys + 200 100 Max. UnitCondition

– 17 – CXP820P60 C S0 SC K0 0.2VD D 0.8VD D tW H C S tD C SK tD C SKF 0.8VD D 0.8VD D tKC Y tKL tKH 0.8VD D 0.2VD D SI0 tSIK tKSI Input data tD C SO tKSO tD C SO F O utput data 0.8VD D 0.2VD D SO 0 0.2VD D Fig. 4. Serial transfer CH0 timing

– 18 – CXP820P60 SC K1 0.2VD D 0.8VD D tKL tKH SO 1 tKC Y tSIK tKSI 0.2VD D 0.8VD D tKSO 0.2VD D 0.8VD D O utput dat Input dataSI1 Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item SCK1 cycle time tKCY SCK1 Input mode Ouput mode Input mode Ouput mode SCK1 input mode SCK1 ouput mode SCK1 input mode SCK1 ouput mode SCK1 input mode SCK1 ouput mode 1000 16000/fc 400 8000/fc – 50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns SCK1 SI1 SI1 SO1 tKH tKL tSIK tKSI tKSO SCK1 High, Low level width SI1 input setup time (for SCK1 ›) SI1 input hold time (for SCK1 ›) SCK1 fl fi SO1 delay time Symbol Pin Condition Min. Max. Unit Note) The load condition for the SCK1 output mode, SO1 output delay time is 50pF + 1TTL. Fig. 5. Serial transfer CH1 timing

– 19 – CXP820P60 Conversion time Sampling time Analog input voltage tCONV tSAMP VIAN VZT*1 VFT*2 AN0 to AN7 Ta = 25°C VDD = 5.0V VSS = 0V Linearity error Zero transition voltage Full-scale transition voltage Resolution µs µs VVDD 26/fADC *3 6/fADC *3 Item Symbol Pin Condition Min. Typ. Max. Unit Bits (3)A/D converter characteristics (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) ±3 LSB 70 mV 5030 4970 –10 4910 mV Fig. 6. Definition of A/D converter terms Analog input Linearity error VFTVZT 00h 01h FEh FFh Digital conversion value *1 VZT: Value at which the digital conversion value changes from 00h to 01h and vice versa. *2 VFT: Value at which the digital conversion value changes from FEh to FFh and vice versa. *3 fADC indicates the below values due to the contents of bit 6 (CKS) of the A/D control register (ADC: 00F9h) and bits 7 (PCK1) and 6 (PCK0) of the clock control register (CLC: 00FEh). However, the selection for f ADC = fC (CKS = "0") is limited in the clock range of fC = 1 to 14MHz (VDD = 4.5 to 5.5V).

– 20 – CXP820P60 0.2VD D 0.8VD D tIH tIL tIL tIH IN T0 IN T1 IN T2 N M I/IN T3 (N M I specifies only for the falling edge.) tR SL 0.2VD D R ST External interruption High, Low level width Reset input Low level width INT0 INT1 INT2 NMI/INT3 RST 32/fc µs µs Item Symbol Pin Condition Min. Max. Unit tIH tIL tRSL (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference) Fig. 7. Interruption input timing Fig. 8. RSTinput timing

– 21 – CXP820P60 Appendix C 1 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 2 /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL R d (i) M ain clock /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 1 C 2 R d XTAL (ii) M ain clock /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines EXTAL XTAL C 1 C 2 R d /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines TEX TX (iii) Sub clock Fig. 9. Recommended oscillation circuit Models marked with an asterisk (*) have the built-in ground capacitance (C1, C2). Manufacturer RIVER ELETEC CO., LTD MURATA MFG CO., LTD. CSA10.0MTZ CSA12.0MTZ CSA16.00MXZ040 CST10.0MTW * CST12.0MTW * CST16.00MXW0C1 * KINSEKI LTD. Seiko Instruments Inc. Model HC-49/U03 HC-49/U (-S) VTC-200 SP-T fc (MHz) 10.0 12.0 16.0 10.0 12.0 16.0 8.0 12.0 16.0 8.0 12.0 16.0 Open Open 330 32.768kHz 330k (iii) C 1 (pF) C 2 (pF) Rd (Ω ) Circuit example (i) (i) (ii) C L = 12.5pF Remarks Mask Option Table Item Package ROM capacitance Reset pin pull-up resistor High voltage drive pin pull-down resistor 100-pin plastic QFP 52K/60K byte Existent/Non-existent Existent/Non-existent 100-pin plastic QFP PROM 60K byte Existent Non-existent (PH7/A24 to PD0/A55) Existent (G0/A0 to A23) Mask ROM CXP820P60Q-1-

– 22 – CXP820P60 Characteristics Curve 0.1 0.01 100 0 1 2 3 4 5 6 7 ID D vs. VD D VD D – Supply voltage [V] IDD – Supply current [m 1/4 dividing m ode Sleep m ode 1/16 dividing m ode 32kH z m ode 32kH z Sleep m ode 1/2 dividing m ode 0 5 10 15 20 1/2 dividing m ode 1/4 dividing m ode 1/16 dividing m ode Sleep m ode ID D vs. fc fc – System clock [M H z] IDD – Supply current [m

– 23 – CXP820P60 Package Outline Unit: mm SO N Y C O D E EIAJ C O D E JED EC C O D E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G 42/C O PPER ALLO Y PAC KAG E STR U C TU R E 23.9 ± 0.4 Q FP-100P-L01 100PIN Q FP (PLASTIC ) 20.0 – 0.1 + 0.4 0.15 – 0.05 + 0.1 15.8 ± 0.4 17.9 ± 0.4 14.0 – 0.1 + 0.4 2.75 – 0.15 + 0.35 A 0.65 M0.13 Q FP100-P-1420 1.7g 100 80 51 0.3 – 0.1 + 0.15 D ETAIL A 0° to 10° 0.8 ± 0.2 (16.3) 0.150.1 – 0.05 + 0.2