CXP81724B

CXP81720B SONY | Alldatasheet

Document overview

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Technical content

Features

A wide instruction set (213 instructions) which covers various types of data — 16-bit arithmetic/multiplication and division/Boolean bit operation instructions
Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V) 122µs at 32kHz operation (2.7 to 5.5V)
Incorporated ROM capacity 20K bytes (CXP81720B) 24K bytes (CXP81724B)
Incorporated RAM capacity 800 bytes
Peripheral functions — A/D converter 8 bits, 12 channels, successive approximation method (Conversion time of 20.0µs at 16MHz) — Serial interface Incorporated 8-bit and 8-stage FIFO, 1 channel (Auto transfer for 1 to 8 bytes) 8-bit clock sync type, 1 channel — Timer 8-bit timer, 8-bit timer/counter, 19-bit time-base timer 32kHz timer/counter — High-precision timing pattern generator PPG: maximum of 19 pins, 32 stages programmable RTG: 5 pins, 2 channels — PWM/DA gate output PWM: 12 bits, 2 channels (Repetitive frequency 62kHz/16MHz) DA gate pulse output: 12 bits, 4 channels — FRC capture unit Incorporated 26-bit and 8-stage FIFO — PWM output 14 bits, 1 channel — Remote control reception circuit 8-bit pulse measuring counter, 6-stage FIFO
Interruption 20 factors, 15 vectors, multi-interruption possible
Standby mode Sleep/stop
Package 100-pin plastic QFP/LQFP
Piggyback/evaluator CXP81800 – 1 – CXP81720B/81724B E97737-PS CMOS 8-bit Single Chip Microcomputer Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. Structure Silicon gate CMOS IC 100 pin QFP (PIastic) 100 pin LQFP (PIastic)

– 2 – CXP81720B/81724B SO1 EC /LiteDiagLines PA0 to PA7 PB0 to PB7 PC0 to PC7 PD0 to PD7 PE0 to PE1 PE2 to PE7 PF0 to PF3 PF4 to PF7 PG0 to PG7 PI1 to PI7 PJ0 to PJ7 Vss VDD MP XTAL EXTAL CLOCK GENERATOR/ SYSTEM CONTROL RAM

800 BYTES

(CH0) FIFO

8 BIT TIMER/COUNTER 0

8 BIT TIMER 1

14 BIT PWM GENERATOR

12 BIT PWM GENERATOR CH0

12 BIT PWM GENERATOR CH1 4DAB1

/LiteDiagLinesNMI PRESCALER/ TIME BASE TIMER REMOCON INPUT FIFO SERIAL INTERFACE UNIT (CH1) CH0 CH1 PORT J PPO0/PPO18 RTO3/RTO7 ADJ Block Diagram

– 3 – CXP81720B/81724B Pin Assignment(Top View) 100-pin QFP package PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PI6/SO1 PI7/SI1 PE0/INT0 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0 PG1 PG2 PG3 PG4 PG5 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3/AN7 AV DD AV REF AV SS PF4/AN8 PB6/PPO14 PB7/PPO15 PA0/PPO0 PA1/PPO1 PA2/PPO2 PA3/PPO3 PA4/PPO4 PA5/PPO5 PA6/PPO6 PA7/PPO7 NC V DD V SS TX TEX PI1/RMC PI2/PWM PI3/TO/ADJ PI4/INT1/NMI PI5/SCK1 PH7PH6 PH5 PH4 PH3 PH2 PH1 PH0MP RSTV SS XTALEXTAL CS0SI0SO0SCK0 PF7/AN11 PF6/AN10PF5/AN9 4039383736353431 32 33 41 42 43 44 45 46 47 48 49 50 8182838488 87 86 85899010 099 98 97 96 95 94 919293 Note) 1. NC (Pin 90) is always connected to VDD . 2. Vss (Pins 41 and 88) are both connected to GND.

– 4 – CXP81720B/81724B Pin Assignment(Top View) 100-pin LQFP package PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PD7 PD6 PD5 PD4 PD3 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 PG0 PG1 PG2 PG3 PG4 PG5 PG6/EXI0 PG7/EXI1 AN0 AN1 AN2 AN3 PF0/AN4 PF1/AN5 PF2/AN6 PF3AN7 AV DD AV REF PB4/PPO12 PB5/PPO13 PB6/PPO14 PB7/PPO15 PA0/PPO0 PA1/PPO1 PA2/PPO2 PA3/PPO3 PA4/PPO4 PA5/PPO5 PA6/PPO6 PA7/PPO7 NC V DD V SS TX TEX PI1/RMC PI2/PWM PI3/TO/ADJ PI4/INT1/NMI PI5/SCK1 PI6/SO1 PI7/SI1 PE0/INT0 PD2 PD1 PD0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0MP RSTV SS XTALEXTAL CS0SI0SO0SCK0 PF7/AN11 PF6/AN10PF5/AN9 PF4/AN8 AV SS 7677787980 26 27 28 29 30 4039383736353431 32 33 41 42 43 44 45 46 47 48 49 50 8182838488 87 86 85899010 099 98 97 96 95 94 919293 Note) 1. NC (Pin 88) is always connected to VDD . 2. Vss (Pins 39 and 86) are both connected to GND.

– 5 – CXP81720B/81724B Output/ Real time output Output/ Real time output I/O/ Real time output I/O/ Real time output I/O Input/input Input/input/input Output/output Output/output Output/output Output/output Output/output Output/output Input Input/input Output/input I/O Ouput Input Input (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RTO contents by OR-gate and they are output. (8 pins) (Port D) 8-bit I/O port. I/O can be set in a unit of 4 bits. Can drive 12mA sink current. (8 pins) (Port E) 8-bit port. Lower 2 bits are for input; upper 6 bits are for output. (8 pins) Analog inputs to A/D converter. (12 pins) (Port F) 8-bit port. Lower 4 bits are for input; upper 4 bits are for output. Lower 4 bits also serve as standby release input pin. (8 pins) Serial clock I/O (CH0). Serial data output (CH0). Serial data input (CH0). Serial chip select input (CH0). External event input for timer/counter. Input to request external interruption. Active at the falling edge. Input to request external interruption. Active at the falling edge. PWM outputs. (2 pins) DA gate pulse outputs. (4 pins) Programmable pattern generator (PPG) output. Functions as high-precision real-time pulse output port. (19 pins) Real-time pulse generator (RTG) output. Functions as high-precision real-time pulse output port. (5 pins) Symbol I/O Description PA0/PPO0 to PA7/PPO7 PB0/PPO8 to PB7/PPO15 PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7 PD0 to PD7 PE0/INT0 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 PE6/DAB0 PE7/DAB1 AN0 to AN3 PF0/AN4 to PF3/AN7 PF4/AN8 to PF7/AN11 SCK0 SO0 SI0 CS0 Pin Description

– 6 – CXP81720B/81724B PG0 to PG5 PG6/EXI0 PG7/EXI1 PH0 to PH7 PI1/RMC PI2/PWM PI3/TO/ADJ PI4/INT1/ NMI PI5/SCK1 PI6/SO1 PI7/SI1 PJ0 to PJ7 EXTAL XTAL TEX TX RST MP AV DD AV REF AVss V DD Vss Input Input/input Input/input Output I/O/input I/O/output I/O/output/output I/O/input/input I/O/I/O I/O/output I/O/input I/O Input Output Input Output Input Input Input External input to FRC capture unit. (2 pins) (Port G) 8-bit input port. (8 pins) (Port H) N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) Remote control reception circuit input. 14-bit PWM output. Timer/counter, 32kHz oscillation adjustment output. Input to request external interruption and non maskable interruption. Active at the falling edge. Serial clock I/O (CH1). Serial data output (CH1). Serial data input (CH1). (Port I) 7-bit I/O port. I/O port can be set in a unit of single bits. (7 pins) (Port J) 8-bit I/O port. I/O and standby release input function can be set in a unit of single bits. Connnects a crystal oscillator for system clock. When supplying the external clock, input the external clock to EXTAL pin and input opposite phase clock to XTAL pin. Connects a crystal oscillator for 32kHz timer/counter clock. When used as event counter, input to TEX pin and leave TX pin open. System reset; active at Low level. Test mode pin. Always connect to GND. Positive power supply of A/D converter. Reference voltage input of A/D converter. GND of A/D converter. Positive power supply. GND. Connect both Vss pins to GND. Symbol I/O Description

– 7 – CXP81720B/81724B Data bus RD (Port D) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesPort D direction/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port D data Large current 12mA IP /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines "0" when reset PPO, RTO data Data bus RD (Port C) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesPort C direction/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port C data Input protection circuit IP /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines "0" when reset Port C 16 pins Hi-Z Hi-Z When reset PA0/PPO0 to PA7/PPO7 PB0/PPO8 to PB7/PPO15 PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7 Port D 8 pins 8 pins Hi-Z PD0 to PD7 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesPPO data Data bus Output becomes active from high impedance by data writing to port register. Ports A, B data RD (Port A or B) Input/Output Circuit Formats for Pins Port A Port B Pin Circuit format

– 8 – CXP81720B/81724B RD (Port F) Data bus /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines IP Input multiplexer A/D converter 2 pins Hi-Z Hi-Z Pin When resetCircuit format PE0/INT0 PE1/EC/INT2 PE2/PWM0 PE3/PWM1 PE4/DAA0 PE5/DAA1 4 pins 2 pins 4 pins Hi-Z Hi-Z H level PE6/DAB0 PE7/DAB1 Data bus RD (Port E) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DA gate output Hi-Z control MPX /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port E data Port/DA output select "1" when reset Data bus RD (Port E) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines DA gate output, PWM output Hi-Z control MPX /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port E data Port/DA output select "0" when reset /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines IP RD (Port E) Data bus Schmitt input Interruption circuit/ event counter Port E AN0 to AN3 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines IP A/D converter Input multiplexer 4 pins PF0/AN4 to PF3/AN7 Port F Port E Port E

– 9 – CXP81720B/81724B Timer/counter, 32kHz timer /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines PI2: 14-bit PWM PI3: MPX /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port I data /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines IP Data bus RD (Port I) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port I/O direction /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port I function selection "0" when reset "0" when reset Data bus RD (Port H) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines Port H data ∗ Large current 12mA Medium drive voltage 12V 4 pins Hi-Z Pin When resetCircuit format PF4/AN8 to PF7/AN11 A/D converterData bus RD (Port F) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines Port F function selection IP /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port F data Input multiplexer"0" when reset Port F 8 pins Hi-Z PG0 to PG5 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines IP RD (Port G) Schmitt input Data bus Note) For PG4 and PG5, CMOS Schmitt input or TTL Schmitt input can be selected with the mask option. Port G 6 pins Hi-Z Hi-Z PG6/EXI0 PG7/EXI1 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines IP RD (Port G) Data bus FRC capture unit Port G 2 pins PH0 to PH7 Port H 2 pins Hi-Z PI2/PWM PI3/TO/ADJ Port I

– 10 – CXP81720B/81724B SO output enable /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines SO Serial interface CH0 3 pins Hi-Z Hi-Z PIn When resetCircuit format PI1/RMC PI4/INT1/NMI PI7/SI1 PI5/SCK1 PI6/SO1 2 pins 8 pins 1 pin Hi-Z Hi-Z Hi-Z PJ0 to PJ7 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Standby release /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port J data /LiteDiagLines /LiteDiagLines IP Data bus RD (Port J) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port J direction /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines Edge detection "0" when reset /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines MPX /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port I data /LiteDiagLines IP Data bus RD (Port I) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port I direction /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port I function selection /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines MPX Serial interface CH1 Serial interface CH1 PI6 is not Schmitt input "0" when reset /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines PI1: Remote control circuit PI4: Interruption circuit PI7: Serial interface CH1 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port I data /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines IP Data bus RD (Port I) /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Port I direction Schmitt input "0" when reset Port J CS0 SI0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines IP Schmitt input CS SI Serial interface CH0 2 pins SO0 Port I Port I

– 11 – CXP81720B/81724B 2 pins Oscillation PIn When resetCircuit format EXTAL XTAL /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines IP /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines EXTAL XTAL

Diagram shows the circuit composition during oscillation.
Feedback resistor is removed during stop mode. XTAL becomes High level. 2 pins Oscillation TEX TX /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines IP /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines TEX TX
Diagram shows the circuit composition during oscillation.
Feedback resistor is removed during oscillation circuit stop by software. At this time TEX pin outputs Low level and TX pin outputs High level. 32kHz timer counter 1 pin Hi-Z SCK0 Serial interface CH0 /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLinesSCK /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines IP Schmitt input SCK output enable SCK 1 pin L level RST /LiteDiagLines/LiteDiagLines /LiteDiagLines IP Schmitt input Pull-up resistor Mask optionOP

– 12 – CXP81720B/81724B *1 AV DD and VDD should be set to the same voltage. *2 VIN and VOUT should not exceed VDD + 0.3V. *3 The large current drive transistors are the N-CH transistors of the PD and PH ports. Note)Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should be conducted under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. Supply voltage Input voltage Output voltage Medium drive output voltage High level output current High level total output current Low level total output current Operating temperature Storage temperature Allowable power dissipation VDD AV DD AV SS VIN VOUT VOUTP IOH ∑ IOH IOL IOLC ∑ IOL Topr Tstg PD Low level output current –0.3 to +7.0 AVss to +7.0*1 –0.3 to +0.3 –0.3 to +7.0*2 –0.3 to +7.0*2 –0.3 to +15.0 –50 130 –20 to +75 –55 to +150 600 380 V V V V V V mA mA mA mA mA mW Port H pin Total of all output pins Ports excluding large current outputs Large current outputs* Total of all output pins QFP package type LQFP package type Item Symbol Rating Unit Remarks Absolute Maximum Ratings (Vss = 0V)

– 13 – CXP81720B/81724B Analog voltage High level input voltage Low level input voltage Operating temperature Supply voltage 5.5 5.5 5.5 5.5 5.5 V DD VDD VDD VDD + 0.3 0.3VDD 0.2VDD 0.8 0.4 +75 V V V V V V V V V V Item Symbol Min. Max. Unit Remarks 4.5 3.5 2.7 2.5 4.5 0.7V DD 0.8VDD 2.2 VDD – 0.4 –0.3 –20 AV DD VIH VIHS VIHTS VIHEX VIL VILS VILTS VILEX Topr Guaranteed operation range for 1/2 and 1/4 frequency dividing clocks Guaranteed operation range for 1/16 frequency dividing clock and sleep mode Guaranteed operation range by TEX clock Guaranteed data hold range during stop mode CMOS Schmitt input*3 TTL Schmitt input*4 EXTAL pin*5 TEX pin*6 CMOS Schmitt input*3 TTL Schmitt input*4 EXTAL pin*5 TEX pin*6 VDD *1 AV DD and VDD should be set to the same voltage. *2 Normal input port (PC, PD, PE0, PE1, PF0 to PF3, PG, PI and PJ pins), MP pin. *3 CS0, SI0, SCK0, RST, INT0, EC/INT2, PG (For PG4 and PG5, when CMOS Schmitt input is selected with mask option), RMC, INT1/NMI, SCK1 and SI1 pins. *4 PG4 and PG5 pins (When TTL Schmitt input is selected with mask option) *5 Specifies only when the external clock is input. *6 Specifies only when the event count clock is input. Recommended Operating Conditions (Vss=0V)

– 14 – CXP81720B/81724B VDD = 4.5V, IOH = –0.5mA VDD = 4.5V, IOH = –1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V High level output voltage 4.0 3.5 0.5 –0.5 0.1 –0.1 –1.5 V V V V V µA µA µA µA µA µA µA PD, PH PA to PD, PE2 to PE7, PF4 to PF7, PH (V OL only) PI1 to PI7 PJ, SO0, SCK0 EXTAL TEX RST *1 Item Symbol Pins Conditions Min. Other than VDD , Vss, AVDD , and AVss Clock 1MHz 0V for no-measured pins VDD IDD1 IIZ ILOH IDDS1 IDD2 IDDS2 IDDS3 C IN VOH VOL IIHE IILE IIHT IILT IILR Low level output voltage Input current Typ. 0.4 0.6 1.5 –40 –10 –400 ±10 Max. Unit DC Characteristics(VDD = 4.5 to 5.5V)

Electrical Characteristics

(Ta = –20 to +75°C, Vss = 0V) *1 RST pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when non-resistor is selected. *2 When entire output pins are open. VDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation and termination of 16MHz crystal oscillation (C 1 = C2 = 47pF) Supply current* Input capacity VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VI = 0, 5.5V VDD = 5.5V VOH = 12V 1/2 frequency dividing clock operation Stop mode V DD = 5.5V, termination of 16MHz and 32kHz crystal oscillation I/O leakage current Open drain output leakage current (in N-ch Tr OFF state) PA to PG, PI, PJ, MP AN0 to AN3, CS0, SI0, SO0 SCK0, RST PH 22 45 mA 35 100 µA 93 0 µ A 10 µA 10 20 pF 1.1 8 mAVDD = 5.5V, 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 3V, 32kHz crystal oscillation, termination of 16MHz crystal oscillation (C 1 = C2 = 47pF) Sleep mode

– 15 – CXP81720B/81724B EXTAL tXH tXLtCF tCR 0.4V VDD – 0.4V 1/fc /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines External clock EXTAL XTAL 74HC04/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Crystal oscillation Ceramic oscillation EXTAL XTAL C 1 C 2 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 32kHz clock applied condition crystal oscillation TEX TX C 1 C 2 Fig. 1. Clock timing Fig. 2. Clock applied condition TEX EC tEH tELtEF tER 0.2VDD 0.8VDD tTH tTLtTF tTR Fig. 3. Event count clock timing *1 tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") AC Characteristics (1) Clock timing System clock frequency System clock input pulse width System clock input rise and fall times Event count input clock pulse width Event count input clock rise and fall times System clock frequency Event count input clock pulse width Event count input clock rise and fall times f C tXL, tXH tCR , tCF tEH , tEL tER , tEF fC tTL, tTH tTR , tTF XTAL EXTAL EXTAL EXTAL EC EC TEX TX TEX TEX MHz ns ns ns ns kHz µs ms Item Symbol Pins Conditions Unit Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 Fig. 2 V DD = 2.7 to 5.5V (32kHz clock applied condition) Fig. 3 Fig. 3 Min. 4tsys*1 32.768 Max. 200 (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V)

– 16 – CXP81720B/81724B Input mode Output mode Input mode Output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode SCK0 input mode SCK0 output mode Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Note 1) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2)The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL. (2) Serial transfer (CH0) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item CS0 ﬂﬁ SCK0 delay time CS0 ›ﬁ SCK0 float delay time CS0 ﬂﬁ SO0 delay time CS0 ›ﬁ SO0 float delay time CS0 High level width SCK0 cycle time SCK0 High and Low level widths SI0 input setup time (for SCK0 ›) SI0 input hold time (for SCK0 ›) SCK0 ﬂﬁ SO0 delay time tDCSK tDCSKF tDCSO tDCSOF tWHCS tKCY tKH tKL tSIK tKSI tKSO SCK0 SCK0 SO0 SO0 CS0 SCK0 SCK0 SI0 SI0 SO0 ns ns ns ns ns Symbol Pin Min. tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200 2tsys + 200 16000/fc tsys + 100 8000/fc – 50 100 200 tsys + 200 100 ns ns ns ns ns ns ns ns ns ns tsys + 200 100 Max. UnitCondition

– 17 – CXP81720B/81724B Fig. 4. Serial transfer CH0 timing CS0 SCK0 0.2VDD 0.8VDD tWHCS tDCSK tDCSKF 0.8VDD 0.2VDD 0.8VDD tKCY tKL tKH 0.8VDD 0.2VDD SI0 tSIK tKSI Input data tDCSO tKSO tDCSOF Output data 0.8VDD 0.2VDD SO0

– 18 – CXP81720B/81724B Fig. 5. Serial transfer CH1 timing SCK1 SI1 SO1 tKCY tKL tKH 0.2VDD 0.8VDD tSIK tKSI tKSO Input data Output data 0.2VDD 0.8VDD 0.2VDD 0.8VDD Serial transfer (CH1) (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol Pins Min. Max. UnitConditions SCK1 cycle time SCK1 High and Low level widths SI1 input setup time (for SCK1 ›) SI1 input hold time (for SCK1 ›) SCK1 ﬂﬁ SO1 delay time tKCY tKH tKL tSIK tKSI tKSO SCK1 SCK1 SI1 SI1 SO1 Input mode Output mode Input mode Output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode SCK1 input mode SCK1 output mode 1000 16000/fc 400 8000/fc – 50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.

– 19 – CXP81720B/81724B Conversion time Sampling time Reference input voltage Analog input voltage tCONV tSAMP VREF VIAN IREF Ta = 25°C VDD = AVDD = AVREF = 5.0V VSS = AVSS = 0V Operating mode Sleep mode Stop mode 32kHz operating mode Linearity error Absolute error Resolution AV REF current AV REF IREFS µs µs V V AV DD 1.0 mA 10 µA 0.6 160/fADC *1 12/fADC *1 AV DD – 0.5 Item Symbol Pins Conditions Min. Typ. Max. Unit Bits (3) A/D converter characteristics(Ta = –20 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD , Vss = AVSS = 0V) LSB LSB Analog input Linearity error 00h 01h FE h FFh Digital conversion value ∗1 The value of fADC is as follows by selecting ADC operation clock (MSC: Address 01FFh bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc Fig. 6. Definitions of A/D converter terms AV REF AN0 to AN11

– 20 – CXP81720B/81724B External interruption High and Low level widths Reset input low level width INT0 INT1 INT2 NMI PJ0 to PJ7 RST 32/fc µs µs Item Symbol Pin Condition Min. Max. Unit tIH tIL tRSL (4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) 0.2VDD 0.8VDD tIH tIL INT0 INT1 INT2 NMI PJ0 to PJ7 (During standby release input) (Falling edge) Fig. 7. Interruption input timing tRSL 0.2VDD RST Fig. 8. Reset input timing Note) tsys indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") tFRC [ns] = 1000/fc (5) Others (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item EXI input High and Low level widths tEIH tEIL EXI0 EXI1 ns Symbol Pin Min. tsys + 200 Max. Unit tsys = 2000/fc Condition 0.8VDDEXI0 EXI1 tEIH tEIL 0.2VDD Fig. 9. Other timings

– 21 – CXP81720B/81724B Appendix Fig. 10. Recommended oscillation circuit /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines EXTAL XTAL C 1 C 2 Rd (i) (ii) C 2 Rd /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines TEX TX C 1 Manufacturer RIVER ELETEC CO., LTD. KINSEKI LTD. Model HC-49/U03 HC-49/U (-S) fc (MHz) 8.00 10.00 12.00 8.00 10.00 12.00 12 12 30 18 470k (ii)32.768kHz 16.00 16 12 C 1 (pF) C 2 (pF) Rd ( Ω ) Circuit example (i) (i) Models with an asterisk (*) have the built-in ground capacitance (C1, C2). *1 The input circuit format can be selected each for PG4 pin and PG5 pin. Item Content Reset pin pull-up resistor Non-existent Existent Input circuit format*1 CMOS Schmitt TTL Schmitt Mask option table 16.00 12 12

– 22 – CXP81720B/81724B Characteristics Curve (100µA) 3 45 6 0.1 5.0 1.0 VDD – Supply voltage [V] IDD – Supply current [mA] IDD vs. VDD (fc = 16MHz, Ta = 25°C, Typical) 0.05 (50µA) 0.01 (10µA) 0.5 10.0 20.0 1/16 dividing mode 32kHz mode (instruction) 32kHz Sleep mode 1/2 dividing mode 1/4 dividing mode 1/16 dividing mode Sleep mode fc – System clock [MHz] IDD – Supply current [mA] IDD vs. fc (VDD = 5V, Ta = 25°C, Typical) 5 10 16 1/2 dividing mode Sleep mode 1/4 dividing mode

– 23 – CXP81720B/81724B Package Outline Unit: mm SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PLATING COPPER / 42 ALLOY PACKAGE STRUCTURE 23.9 ± 0.4 QFP-100P-L01 DETAIL A M 100PIN QFP (PLASTIC) 20.0 – 0.1 + 0.4 0° to 15° 0.15 – 0.05 + 0.1 + 0.4 2.75 – 0.15 + 0.35 A 0.65 ±0.12 0.15 0.8 ± 0.2 (16.3) ∗QFP100-P-1420-A 1.4g SONY CODE EIAJ CODE JEDEC CODE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY/PHENOL RESIN SOLDER PLATING

42 ALLOY

∗QFP100-P-1414-A 100PIN LQFP (PLASTIC) 16.0 ± 0.2 ∗ 14.0 ± 0.1 75 51 251 + 0.08 (0.22) A 1.5 – 0.1 + 0.2 0.127 – 0.02 + 0.05 0.5 ± 0.2 (15.0) 0° to 10° 0.1 ± 0.1 0.5 ± 0.2 100 0.1 NOTE: Dimension “∗” does not include mold protrusion.

Summary

CMOS 8-bit Single Chip Microcomputer

Description

The CXP81720B/81724B is a CMOS 8-bit microcomputer which consists of A/D converter, serial interface, timer/counter, time-base timer, high precision timing pattern generation circuit, PWM output, 32kHz timer/counter, remote control reception circuit, as well as basic configurations like 8-bit CPU, ROM, RAM and I/O port. They are integrated into a single chip.

Source title CXP81724B Datasheet(PDF) - Sony Corporation

Read CXP81724B online.